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Thu, 12 May 2022 06:53:21 -0700 From: Venkateshwar Rao Gannavarapu To: , CC: , , , , Venkateshwar Rao Gannavarapu Subject: [LINUX PATCH 1/2] dt-bindings: display: xlnx: Add DSI 2.0 Tx subsystem documentation Date: Thu, 12 May 2022 19:23:12 +0530 Message-ID: <1652363593-45799-2-git-send-email-venkateshwar.rao.gannavarapu@xilinx.com> X-Mailer: git-send-email 2.1.1 In-Reply-To: <1652363593-45799-1-git-send-email-venkateshwar.rao.gannavarapu@xilinx.com> References: <1652363593-45799-1-git-send-email-venkateshwar.rao.gannavarapu@xilinx.com> MIME-Version: 1.0 Content-Type: text/plain X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 1fdfee2e-e127-4a61-11de-08da341ec6e8 X-MS-TrafficTypeDiagnostic: CY4PR02MB3381:EE_ X-Microsoft-Antispam-PRVS: X-Auto-Response-Suppress: DR, RN, NRN, OOF, AutoReply X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: NJMEMYLOxsPwYTZDRKmCbWNLNj3gIl2XIXitF0aZvhnkERIhwP5a7+at+R31rwZv23OD3OxCGrMnCy7Akxm3siR//98WHF6iNP8lMd66gjjRgAaI578uD7+ZZ9ntcbAXQPHCXoNrjH3tqci6oA1PtvmlaOg/2O5b6QxkZjBz/KXFIpCErvzi5HjPGbKlfC9ZbARPv2XGPYLShPAZu1kpPCWJ40XPhSBI66k+v3NFYsKn1qAk4Os+LQ/4petAwm6UEXklX7AcckiVINkDpj7559NrZjMATlM96ksNmA2w7LiZs1pd8dQSVk0Y7l10OoFkpVCnhgxqQXIt8D1NFlP5qmfmlep3SdPgI9n+SXF6LcwVlekT+yEn00Vc4tg7G04jn0xpLhXNDZ2QIhKPl8Iqexx9yOVZXh7nK3M4KWH62tbtMqlH7iMrBGrnE/3E/OsbH602zq4j7PxS0aMx+pQ9e49I1hAWfZxvmu5I4EVoVlOQrl6QH+hlHzGY2TFQxnE1WQvv/IVXUBKLVZWkbcNSZMr5J19Uaj9GgYNSDhbV/M7pC6hYttEId0kK0eDbNHo5MYup7xrmt5uWcJb93HXk1NdoJyIQRIYAZfjJt9KQfOahN+OJIRMl/7bahb+Dxu/NNwkz8++pgsgRuaZmDQCPpfd81LIS03oXwfvsvR3xSP8VVzMl/0W3dmpnb9VcddHGzz+BiEJlw/R41foG+MBrChSm0yqUjp2sM3AsnrakEoVLFdtJJXw+9DUvrdMJb1tf6PpIquai1d781dN8co/fVHF2AS/Niz3jxjo635UELKf0yi5BHIm6J+37I9KEkPeG1RoYUmdYYpcahAULCnfpdA== X-Forefront-Antispam-Report: CIP:149.199.62.198;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:xsj-pvapexch01.xlnx.xilinx.com;PTR:unknown-62-198.xilinx.com;CAT:NONE;SFS:(13230001)(4636009)(40470700004)(46966006)(36840700001)(2906002)(36756003)(82310400005)(8936002)(36860700001)(107886003)(9786002)(5660300002)(8676002)(70206006)(70586007)(4326008)(54906003)(83380400001)(40460700003)(186003)(966005)(110136005)(2616005)(336012)(26005)(7696005)(7636003)(316002)(47076005)(426003)(6666004)(356005)(508600001)(102446001);DIR:OUT;SFP:1101; X-OriginatorOrg: xilinx.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 12 May 2022 13:53:21.6169 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 1fdfee2e-e127-4a61-11de-08da341ec6e8 X-MS-Exchange-CrossTenant-Id: 657af505-d5df-48d0-8300-c31994686c5c X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=657af505-d5df-48d0-8300-c31994686c5c;Ip=[149.199.62.198];Helo=[xsj-pvapexch01.xlnx.xilinx.com] X-MS-Exchange-CrossTenant-AuthSource: SN1NAM02FT0037.eop-nam02.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CY4PR02MB3381 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org This patch adds dt binding for Xilinx DSI TX subsystem. The Xilinx MIPI DSI (Display serial interface) Transmitter Subsystem implements the Mobile Industry Processor Interface (MIPI) based display interface. It supports the interface with the programmable logic (FPGA). Signed-off-by: Venkateshwar Rao Gannavarapu --- .../bindings/display/xlnx/xlnx,dsi-tx.yaml | 105 +++++++++++++++++++++ 1 file changed, 105 insertions(+) create mode 100644 Documentation/devicetree/bindings/display/xlnx/xlnx,dsi-tx.yaml diff --git a/Documentation/devicetree/bindings/display/xlnx/xlnx,dsi-tx.yaml b/Documentation/devicetree/bindings/display/xlnx/xlnx,dsi-tx.yaml new file mode 100644 index 0000000..8e23cf5 --- /dev/null +++ b/Documentation/devicetree/bindings/display/xlnx/xlnx,dsi-tx.yaml @@ -0,0 +1,105 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/display/xlnx/xlnx,dsi-tx.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Xilinx DSI Transmitter subsystem + +maintainers: + - Venkateshwar Rao Gannavarapu + +description: | + The Xilinx DSI Transmitter Subsystem implements the Mobile Industry + Processor Interface based display interface. It supports the interface + with the programmable logic (FPGA). + + For more details refer to PG238 Xilinx MIPI DSI-V2.0 Tx Subsystem. + +properties: + compatible: + const: xlnx,dsi-tx-v2.0 + + reg: + maxItems: 1 + + clocks: + description: List of clock specifiers + items: + - description: AXI Lite CPU clock + - description: D-phy clock + + clock-names: + items: + - const: s_axis_aclk + - const: dphy_clk_200M + + ports: + $ref: /schemas/graph.yaml#/properties/ports + + properties: + port@0: + $ref: /schemas/graph.yaml#/$defs/port-base + description: + Input port node to receive pixel data from the + display controller. Exactly one endpoint must be + specified. + properties: + endpoint: + $ref: /schemas/graph.yaml#/properties/endpoint + description: sub-node describing the input from CRTC + + port@1: + $ref: /schemas/graph.yaml#/properties/port + description: + DSI output port node to the panel or the next bridge + in the chain + +required: + - compatible + - reg + - clocks + - clock-names + - ports + +additionalProperties: false + +examples: + - | + dsi_tx@80020000 { + compatible = "xlnx,dsi-tx-v2.0"; + reg = <0x80020000 0x20000>; + clock-names = "s_axi_aclk", "dphy_clk_200M"; + clocks = <&misc_clk_0>, <&misc_clk_1>; + + panel@0 { + compatible = "auo,b101uan01"; + reg = <0>; + port { + panel_in: endpoint { + remote-endpoint = <&mipi_dsi_out>; + }; + }; + }; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + #size-cells = <0>; + #address-cells = <1>; + reg = <0>; + mipi_dsi_in: endpoint@0 { + reg = <0>; + remote-endpoint = <&pl_disp_crtc>; + }; + }; + port@1 { + reg = <1>; + mipi_dsi_out: endpoint { + remote-endpoint = <&panel_in>; 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Thu, 12 May 2022 06:53:21 -0700 From: Venkateshwar Rao Gannavarapu To: , Subject: [LINUX PATCH 1/2] dt-bindings: display: xlnx: Add DSI 2.0 Tx subsystem documentation Date: Thu, 12 May 2022 19:23:12 +0530 Message-ID: <1652363593-45799-2-git-send-email-venkateshwar.rao.gannavarapu@xilinx.com> X-Mailer: git-send-email 2.1.1 In-Reply-To: <1652363593-45799-1-git-send-email-venkateshwar.rao.gannavarapu@xilinx.com> References: <1652363593-45799-1-git-send-email-venkateshwar.rao.gannavarapu@xilinx.com> MIME-Version: 1.0 Content-Type: text/plain X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 1fdfee2e-e127-4a61-11de-08da341ec6e8 X-MS-TrafficTypeDiagnostic: CY4PR02MB3381:EE_ X-Microsoft-Antispam-PRVS: X-Auto-Response-Suppress: DR, RN, NRN, OOF, AutoReply X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: NJMEMYLOxsPwYTZDRKmCbWNLNj3gIl2XIXitF0aZvhnkERIhwP5a7+at+R31rwZv23OD3OxCGrMnCy7Akxm3siR//98WHF6iNP8lMd66gjjRgAaI578uD7+ZZ9ntcbAXQPHCXoNrjH3tqci6oA1PtvmlaOg/2O5b6QxkZjBz/KXFIpCErvzi5HjPGbKlfC9ZbARPv2XGPYLShPAZu1kpPCWJ40XPhSBI66k+v3NFYsKn1qAk4Os+LQ/4petAwm6UEXklX7AcckiVINkDpj7559NrZjMATlM96ksNmA2w7LiZs1pd8dQSVk0Y7l10OoFkpVCnhgxqQXIt8D1NFlP5qmfmlep3SdPgI9n+SXF6LcwVlekT+yEn00Vc4tg7G04jn0xpLhXNDZ2QIhKPl8Iqexx9yOVZXh7nK3M4KWH62tbtMqlH7iMrBGrnE/3E/OsbH602zq4j7PxS0aMx+pQ9e49I1hAWfZxvmu5I4EVoVlOQrl6QH+hlHzGY2TFQxnE1WQvv/IVXUBKLVZWkbcNSZMr5J19Uaj9GgYNSDhbV/M7pC6hYttEId0kK0eDbNHo5MYup7xrmt5uWcJb93HXk1NdoJyIQRIYAZfjJt9KQfOahN+OJIRMl/7bahb+Dxu/NNwkz8++pgsgRuaZmDQCPpfd81LIS03oXwfvsvR3xSP8VVzMl/0W3dmpnb9VcddHGzz+BiEJlw/R41foG+MBrChSm0yqUjp2sM3AsnrakEoVLFdtJJXw+9DUvrdMJb1tf6PpIquai1d781dN8co/fVHF2AS/Niz3jxjo635UELKf0yi5BHIm6J+37I9KEkPeG1RoYUmdYYpcahAULCnfpdA== X-Forefront-Antispam-Report: CIP:149.199.62.198; CTRY:US; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:xsj-pvapexch01.xlnx.xilinx.com; PTR:unknown-62-198.xilinx.com; CAT:NONE; SFS:(13230001)(4636009)(40470700004)(46966006)(36840700001)(2906002)(36756003)(82310400005)(8936002)(36860700001)(107886003)(9786002)(5660300002)(8676002)(70206006)(70586007)(4326008)(54906003)(83380400001)(40460700003)(186003)(966005)(110136005)(2616005)(336012)(26005)(7696005)(7636003)(316002)(47076005)(426003)(6666004)(356005)(508600001)(102446001); DIR:OUT; SFP:1101; X-OriginatorOrg: xilinx.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 12 May 2022 13:53:21.6169 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 1fdfee2e-e127-4a61-11de-08da341ec6e8 X-MS-Exchange-CrossTenant-Id: 657af505-d5df-48d0-8300-c31994686c5c X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=657af505-d5df-48d0-8300-c31994686c5c; Ip=[149.199.62.198]; Helo=[xsj-pvapexch01.xlnx.xilinx.com] X-MS-Exchange-CrossTenant-AuthSource: SN1NAM02FT0037.eop-nam02.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CY4PR02MB3381 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: airlied@linux.ie, vgannava@xilinx.com, Venkateshwar Rao Gannavarapu , linux-kernel@vger.kernel.org Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" This patch adds dt binding for Xilinx DSI TX subsystem. The Xilinx MIPI DSI (Display serial interface) Transmitter Subsystem implements the Mobile Industry Processor Interface (MIPI) based display interface. It supports the interface with the programmable logic (FPGA). Signed-off-by: Venkateshwar Rao Gannavarapu --- .../bindings/display/xlnx/xlnx,dsi-tx.yaml | 105 +++++++++++++++++++++ 1 file changed, 105 insertions(+) create mode 100644 Documentation/devicetree/bindings/display/xlnx/xlnx,dsi-tx.yaml diff --git a/Documentation/devicetree/bindings/display/xlnx/xlnx,dsi-tx.yaml b/Documentation/devicetree/bindings/display/xlnx/xlnx,dsi-tx.yaml new file mode 100644 index 0000000..8e23cf5 --- /dev/null +++ b/Documentation/devicetree/bindings/display/xlnx/xlnx,dsi-tx.yaml @@ -0,0 +1,105 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/display/xlnx/xlnx,dsi-tx.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Xilinx DSI Transmitter subsystem + +maintainers: + - Venkateshwar Rao Gannavarapu + +description: | + The Xilinx DSI Transmitter Subsystem implements the Mobile Industry + Processor Interface based display interface. It supports the interface + with the programmable logic (FPGA). + + For more details refer to PG238 Xilinx MIPI DSI-V2.0 Tx Subsystem. + +properties: + compatible: + const: xlnx,dsi-tx-v2.0 + + reg: + maxItems: 1 + + clocks: + description: List of clock specifiers + items: + - description: AXI Lite CPU clock + - description: D-phy clock + + clock-names: + items: + - const: s_axis_aclk + - const: dphy_clk_200M + + ports: + $ref: /schemas/graph.yaml#/properties/ports + + properties: + port@0: + $ref: /schemas/graph.yaml#/$defs/port-base + description: + Input port node to receive pixel data from the + display controller. Exactly one endpoint must be + specified. + properties: + endpoint: + $ref: /schemas/graph.yaml#/properties/endpoint + description: sub-node describing the input from CRTC + + port@1: + $ref: /schemas/graph.yaml#/properties/port + description: + DSI output port node to the panel or the next bridge + in the chain + +required: + - compatible + - reg + - clocks + - clock-names + - ports + +additionalProperties: false + +examples: + - | + dsi_tx@80020000 { + compatible = "xlnx,dsi-tx-v2.0"; + reg = <0x80020000 0x20000>; + clock-names = "s_axi_aclk", "dphy_clk_200M"; + clocks = <&misc_clk_0>, <&misc_clk_1>; + + panel@0 { + compatible = "auo,b101uan01"; + reg = <0>; + port { + panel_in: endpoint { + remote-endpoint = <&mipi_dsi_out>; + }; + }; + }; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + #size-cells = <0>; + #address-cells = <1>; + reg = <0>; + mipi_dsi_in: endpoint@0 { + reg = <0>; + remote-endpoint = <&pl_disp_crtc>; + }; + }; + port@1 { + reg = <1>; + mipi_dsi_out: endpoint { + remote-endpoint = <&panel_in>; + }; + }; + }; + }; -- 1.8.3.1