All of lore.kernel.org
 help / color / mirror / Atom feed
From: Dan Williams <dan.j.williams@intel.com>
To: linux-cxl@vger.kernel.org
Cc: Jonathan.Cameron@huawei.com, ben.widawsky@intel.com,
	ira.weiny@intel.com, alison.schofield@intel.com,
	vishal.l.verma@intel.com
Subject: [PATCH 09/14] cxl/mem: Fix CXL DVSEC Range Sizing
Date: Thu, 12 May 2022 11:15:05 -0700	[thread overview]
Message-ID: <165237930521.3832067.16931437806464317011.stgit@dwillia2-desk3.amr.corp.intel.com> (raw)
In-Reply-To: <165237925642.3832067.15995008431029494571.stgit@dwillia2-desk3.amr.corp.intel.com>

Per CXL 2.0 Section 8.1.3.8.4 "DVSEC CXL Range 1 Base Low" there is no
way to specify decode sizes smaller than 256M. Fix cxl_dvsec_ranges()
and cxl_hdm_decode_init() to account for that default decode range.
Note, that this means that any BIOS implementation that sets mem_enable,
but not HDM Decoder Capability enable will cause the driver to fail to
attach. A later change validates the DVSEC ranges against platform CXL
decode (CXL CFMWS) to make a decision about overriding the default DVSEC
Range configuration.

Fixes: 560f78559006 ("cxl/pci: Retrieve CXL DVSEC memory info")
Signed-off-by: Dan Williams <dan.j.williams@intel.com>
---
 drivers/cxl/core/pci.c |   10 +++++++---
 drivers/cxl/mem.c      |   10 +---------
 2 files changed, 8 insertions(+), 12 deletions(-)

diff --git a/drivers/cxl/core/pci.c b/drivers/cxl/core/pci.c
index f3e59f8b6621..f1c0677a4f52 100644
--- a/drivers/cxl/core/pci.c
+++ b/drivers/cxl/core/pci.c
@@ -236,7 +236,12 @@ int cxl_dvsec_ranges(struct cxl_dev_state *cxlds,
 		if (rc)
 			return rc;
 
-		size = (u64)temp << 32;
+		/*
+		 * Per CXL 2.0 Section 8.1.3.8.4 "DVSEC CXL Range 1 Base
+		 * Low", the minimum decode size is 256MB
+		 */
+		size = SZ_256M;
+		size |= (u64)temp << 32;
 
 		rc = pci_read_config_dword(
 			pdev, d + CXL_DVSEC_RANGE_SIZE_LOW(i), &temp);
@@ -264,8 +269,7 @@ int cxl_dvsec_ranges(struct cxl_dev_state *cxlds,
 			.end = base + size - 1
 		};
 
-		if (size)
-			ranges++;
+		ranges++;
 	}
 
 	info->ranges = ranges;
diff --git a/drivers/cxl/mem.c b/drivers/cxl/mem.c
index 902d1f6e189e..af4a88d3c5fa 100644
--- a/drivers/cxl/mem.c
+++ b/drivers/cxl/mem.c
@@ -84,15 +84,7 @@ __mock bool cxl_hdm_decode_init(struct cxl_dev_state *cxlds,
 			    CXL_HDM_DECODER_CTRL_OFFSET);
 	global_enable = global_ctrl & CXL_HDM_DECODER_ENABLE;
 
-	/*
-	 * Per CXL 2.0 Section 8.1.3.8.3 and 8.1.3.8.4 DVSEC CXL Range 1 Base
-	 * [High,Low] when HDM operation is enabled the range register values
-	 * are ignored by the device, but the spec also recommends matching the
-	 * DVSEC Range 1,2 to HDM Decoder Range 0,1. So, non-zero info->ranges
-	 * are expected even though Linux does not require or maintain that
-	 * match.
-	 */
-	if (!global_enable && info->mem_enabled && info->ranges)
+	if (!global_enable && info->mem_enabled)
 		goto out;
 
 	retval = true;


  parent reply	other threads:[~2022-05-12 18:15 UTC|newest]

Thread overview: 46+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-05-12 18:14 [PATCH 00/14] cxl: Fix "mem_enable" handling Dan Williams
2022-05-12 18:14 ` [PATCH 01/14] cxl/mem: Drop mem_enabled check from wait_for_media() Dan Williams
2022-05-18 17:21   ` Jonathan Cameron
2022-05-12 18:14 ` [PATCH 02/14] cxl/pci: Consolidate wait_for_media() and wait_for_media_ready() Dan Williams
2022-05-18 17:22   ` Jonathan Cameron
2022-05-12 18:14 ` [PATCH 03/14] cxl/pci: Drop wait_for_valid() from cxl_await_media_ready() Dan Williams
2022-05-18 17:22   ` Jonathan Cameron
2022-05-12 18:14 ` [PATCH 04/14] cxl/mem: Fix cxl_mem_probe() error exit Dan Williams
2022-05-18 17:23   ` Jonathan Cameron
2022-05-12 18:14 ` [PATCH 05/14] cxl/mem: Validate port connectivity before dvsec ranges Dan Williams
2022-05-18 16:13   ` Jonathan Cameron
2022-05-18 16:41     ` Dan Williams
2022-05-18 17:21       ` Jonathan Cameron
2022-05-12 18:14 ` [PATCH 06/14] cxl/pci: Move cxl_await_media_ready() to the core Dan Williams
2022-05-18 16:21   ` Jonathan Cameron
2022-05-18 16:37     ` Dan Williams
2022-05-18 17:20       ` Jonathan Cameron
2022-05-18 18:22         ` Dan Williams
2022-05-12 18:14 ` [PATCH 07/14] cxl/mem: Consolidate CXL DVSEC Range enumeration in " Dan Williams
2022-05-18 16:31   ` Jonathan Cameron
2022-05-18 16:52     ` Dan Williams
2022-05-18 17:24       ` Jonathan Cameron
2022-05-12 18:14 ` [PATCH 08/14] cxl/mem: Skip range enumeration if mem_enable clear Dan Williams
2022-05-18 17:25   ` Jonathan Cameron
2022-05-12 18:15 ` Dan Williams [this message]
2022-05-18 16:40   ` [PATCH 09/14] cxl/mem: Fix CXL DVSEC Range Sizing Jonathan Cameron
2022-05-18 17:06     ` Dan Williams
2022-05-12 18:15 ` [PATCH 10/14] cxl/mem: Merge cxl_dvsec_ranges() and cxl_hdm_decode_init() Dan Williams
2022-05-12 18:15 ` [PATCH 11/14] cxl/pci: Drop @info argument to cxl_hdm_decode_init() Dan Williams
2022-05-18 16:45   ` Jonathan Cameron
2022-05-12 18:15 ` [PATCH 12/14] cxl/port: Move endpoint HDM Decoder Capability init to port driver Dan Williams
2022-05-18 16:50   ` Jonathan Cameron
2022-05-12 18:15 ` [PATCH 13/14] cxl/port: Reuse 'struct cxl_hdm' context for hdm init Dan Williams
2022-05-18 16:50   ` Jonathan Cameron
2022-05-12 18:15 ` [PATCH 14/14] cxl/port: Enable HDM Capability after validating DVSEC Ranges Dan Williams
2022-05-16 18:41   ` Ariel.Sibley
2022-05-16 18:52     ` Dan Williams
2022-05-16 19:31       ` Ariel.Sibley
2022-05-16 20:07         ` Dan Williams
2022-05-18  0:38   ` [PATCH v2 " Dan Williams
2022-05-18  2:07     ` Ariel.Sibley
2022-05-18  2:44       ` Dan Williams
2022-05-18 15:33         ` Jonathan Cameron
2022-05-18 17:17     ` Jonathan Cameron
2022-05-18 18:00       ` Dan Williams
2022-05-18  0:50 ` [PATCH 00/14] cxl: Fix "mem_enable" handling Ira Weiny

Reply instructions:

You may reply publicly to this message via plain-text email
using any one of the following methods:

* Save the following mbox file, import it into your mail client,
  and reply-to-all from there: mbox

  Avoid top-posting and favor interleaved quoting:
  https://en.wikipedia.org/wiki/Posting_style#Interleaved_style

* Reply using the --to, --cc, and --in-reply-to
  switches of git-send-email(1):

  git send-email \
    --in-reply-to=165237930521.3832067.16931437806464317011.stgit@dwillia2-desk3.amr.corp.intel.com \
    --to=dan.j.williams@intel.com \
    --cc=Jonathan.Cameron@huawei.com \
    --cc=alison.schofield@intel.com \
    --cc=ben.widawsky@intel.com \
    --cc=ira.weiny@intel.com \
    --cc=linux-cxl@vger.kernel.org \
    --cc=vishal.l.verma@intel.com \
    /path/to/YOUR_REPLY

  https://kernel.org/pub/software/scm/git/docs/git-send-email.html

* If your mail client supports setting the In-Reply-To header
  via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line before the message body.
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.