From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from phobos.denx.de (phobos.denx.de [85.214.62.61]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id DA0B2C433EF for ; Wed, 1 Jun 2022 18:26:55 +0000 (UTC) Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) by phobos.denx.de (Postfix) with ESMTP id A435A842EC; Wed, 1 Jun 2022 20:26:45 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de Authentication-Results: phobos.denx.de; dkim=pass (2048-bit key; unprotected) header.d=linaro.org header.i=@linaro.org header.b="LVMQ+QgO"; dkim-atps=neutral Received: by phobos.denx.de (Postfix, from userid 109) id 8438983F24; Wed, 1 Jun 2022 20:26:42 +0200 (CEST) Received: from mail-wr1-x435.google.com (mail-wr1-x435.google.com [IPv6:2a00:1450:4864:20::435]) (using TLSv1.3 with cipher TLS_AES_128_GCM_SHA256 (128/128 bits)) (No client certificate requested) by phobos.denx.de (Postfix) with ESMTPS id 08912842F2 for ; Wed, 1 Jun 2022 20:26:38 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=loic.poulain@linaro.org Received: by mail-wr1-x435.google.com with SMTP id k16so3486478wrg.7 for ; Wed, 01 Jun 2022 11:26:38 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=pVML34C0RVOhrh1vp8HIbwYce19Tv309oZoJ8AIERs8=; b=LVMQ+QgO7x4lEa/jRM27YUN89ZthqY9qmk71SYTxASin+FKBpTL+bOudWzW4DCvgr+ d5YYb4IZnSI8VMDJpjnvkFs1qQKf6fQJ014Z59LaeSKV8jxjYLBHsoWDSDwL/4F5AtQ0 aaHCd9KOJ6PvmiDli4CzVq7NFvh8BhWkiNxF8m5cuG6Bj5xVSVM/+M4zelx4sF9z8Ooe eLqwFNMdd2tTQ6E9daLfDizqVBrctcf97E6qSZkFXUd/rk1F0JPfEVwKsCQviRBvx5ZK 9DHP597bieObolxrtkDPg4UYqOrVjFqbR06EbdnUIX/U0h3XY+mU68Vs98XNmMrmcVk9 caaQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=pVML34C0RVOhrh1vp8HIbwYce19Tv309oZoJ8AIERs8=; b=FkSS+CriQ2qdunE4w8l8QIq4XN1CtS1vDPjzU+EaQHRoA1yQg4Go+uoNADhOhzmt53 fnGvs7ZFc5G+VLnFoU0jQWqI2kD7aP+mE9b370pKzpDnmb0QGQHJ2Nb6XZTpS7wmO769 dmGn1pm/PhCkPpSTQRlB6TVj6P5pS/mDAvOH5m+2pwk83eyzOZDSI+ZYOqdwwU7oQLp2 T33ZJ7n5PXb+2HcJ0EJVNSiU8O0gyACylKoAh6uaegnFv7ZFjgnXShGyf3YxL3Snupd9 OTlN0sDpEIu50HkMk8e5zMkMf4r33Sn11WxatAFkGmGMqn6r2fY5jXrGEz2OJEZ+wg+L kV2w== X-Gm-Message-State: AOAM530HoX7lCdIoowK+mp/8lRpdApVDO9kGEpaTuGLOpU3ugvMJeGnm utPBnwmYXJk7e2Lc41kQyE/ZwBnEhjVY0g== X-Google-Smtp-Source: ABdhPJzclgMp9SrNXAS8WSVZaDiuc/wpQbDhQ1dggUQ1McF9kW7JdgRuMng0tsuEoR4EdVTcYNyqgA== X-Received: by 2002:adf:eb8e:0:b0:20c:b378:67b2 with SMTP id t14-20020adfeb8e000000b0020cb37867b2mr621042wrn.164.1654107997640; Wed, 01 Jun 2022 11:26:37 -0700 (PDT) Received: from localhost.localdomain ([2a01:e0a:82c:5f0:58:ccc3:729d:30c2]) by smtp.gmail.com with ESMTPSA id m30-20020a05600c3b1e00b00395f15d993fsm6672837wms.5.2022.06.01.11.26.36 (version=TLS1_2 cipher=ECDHE-ECDSA-AES128-GCM-SHA256 bits=128/128); Wed, 01 Jun 2022 11:26:37 -0700 (PDT) From: Loic Poulain To: trini@konsulko.com Cc: u-boot@lists.denx.de, michal.simek@xilinx.com, kettenis@openbsd.org, Loic Poulain Subject: [PATCH v2 3/5] armv8 SHA-1 using ARMv8 Crypto Extensions: Date: Wed, 1 Jun 2022 20:26:29 +0200 Message-Id: <1654107991-598-4-git-send-email-loic.poulain@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1654107991-598-1-git-send-email-loic.poulain@linaro.org> References: <1654107991-598-1-git-send-email-loic.poulain@linaro.org> X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.5 at phobos.denx.de X-Virus-Status: Clean This patch adds support for the SHA-1 Secure Hash Algorithm for CPUs that have support for the SHA-1 part of the ARM v8 Crypto Extensions. It greatly improves sha-1 based operations, about 10x faster on iMX8M evk board. ~12ms vs ~165ms for a 20MiB kernel sha-1 verification. asm implementation is a simplified version of the Linux version (from Ard Biesheuvel). Signed-off-by: Loic Poulain --- arch/arm/cpu/armv8/Kconfig | 11 ++++ arch/arm/cpu/armv8/Makefile | 1 + arch/arm/cpu/armv8/sha1_ce_core.S | 132 ++++++++++++++++++++++++++++++++++++++ arch/arm/cpu/armv8/sha1_ce_glue.c | 21 ++++++ 4 files changed, 165 insertions(+) create mode 100644 arch/arm/cpu/armv8/sha1_ce_core.S create mode 100644 arch/arm/cpu/armv8/sha1_ce_glue.c diff --git a/arch/arm/cpu/armv8/Kconfig b/arch/arm/cpu/armv8/Kconfig index 9967376..0b11ca8 100644 --- a/arch/arm/cpu/armv8/Kconfig +++ b/arch/arm/cpu/armv8/Kconfig @@ -171,4 +171,15 @@ config ARMV8_SECURE_BASE endif +menuconfig ARMV8_CRYPTO + bool "ARM64 Accelerated Cryptographic Algorithms" + +if ARMV8_CRYPTO + +config ARMV8_CE_SHA1 + bool "SHA-1 digest algorithm (ARMv8 Crypto Extensions)" + default y if SHA1 + +endif + endif diff --git a/arch/arm/cpu/armv8/Makefile b/arch/arm/cpu/armv8/Makefile index 85fe047..ff2495c 100644 --- a/arch/arm/cpu/armv8/Makefile +++ b/arch/arm/cpu/armv8/Makefile @@ -44,3 +44,4 @@ obj-$(CONFIG_TARGET_HIKEY) += hisilicon/ obj-$(CONFIG_ARMV8_PSCI) += psci.o obj-$(CONFIG_TARGET_BCMNS3) += bcmns3/ obj-$(CONFIG_XEN) += xen/ +obj-$(CONFIG_ARMV8_CE_SHA1) += sha1_ce_glue.o sha1_ce_core.o diff --git a/arch/arm/cpu/armv8/sha1_ce_core.S b/arch/arm/cpu/armv8/sha1_ce_core.S new file mode 100644 index 0000000..fbf2714 --- /dev/null +++ b/arch/arm/cpu/armv8/sha1_ce_core.S @@ -0,0 +1,132 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * sha1_ce_core.S - SHA-1 secure hash using ARMv8 Crypto Extensions + * + * Copyright (C) 2014 Linaro Ltd + * Copyright (C) 2022 Linaro Ltd + */ + +#include +#include +#include +#include + + .text + .arch armv8-a+crypto + + k0 .req v0 + k1 .req v1 + k2 .req v2 + k3 .req v3 + + t0 .req v4 + t1 .req v5 + + dga .req q6 + dgav .req v6 + dgb .req s7 + dgbv .req v7 + + dg0q .req q12 + dg0s .req s12 + dg0v .req v12 + dg1s .req s13 + dg1v .req v13 + dg2s .req s14 + + .macro add_only, op, ev, rc, s0, dg1 + .ifc \ev, ev + add t1.4s, v\s0\().4s, \rc\().4s + sha1h dg2s, dg0s + .ifnb \dg1 + sha1\op dg0q, \dg1, t0.4s + .else + sha1\op dg0q, dg1s, t0.4s + .endif + .else + .ifnb \s0 + add t0.4s, v\s0\().4s, \rc\().4s + .endif + sha1h dg1s, dg0s + sha1\op dg0q, dg2s, t1.4s + .endif + .endm + + .macro add_update, op, ev, rc, s0, s1, s2, s3, dg1 + sha1su0 v\s0\().4s, v\s1\().4s, v\s2\().4s + add_only \op, \ev, \rc, \s1, \dg1 + sha1su1 v\s0\().4s, v\s3\().4s + .endm + + .macro loadrc, k, val, tmp + movz \tmp, :abs_g0_nc:\val + movk \tmp, :abs_g1:\val + dup \k, \tmp + .endm + + /* + * void sha1_armv8_ce_process(uint32_t state[5], uint8_t const *src, + * uint32_t blocks) + */ +ENTRY(sha1_armv8_ce_process) + /* load round constants */ + loadrc k0.4s, 0x5a827999, w6 + loadrc k1.4s, 0x6ed9eba1, w6 + loadrc k2.4s, 0x8f1bbcdc, w6 + loadrc k3.4s, 0xca62c1d6, w6 + + /* load state (4+1 digest states) */ + ld1 {dgav.4s}, [x0] + ldr dgb, [x0, #16] + + /* load input (64 bytes into v8->v11 16B vectors) */ +0: ld1 {v8.4s-v11.4s}, [x1], #64 + sub w2, w2, #1 +#if __BYTE_ORDER == __LITTLE_ENDIAN + rev32 v8.16b, v8.16b + rev32 v9.16b, v9.16b + rev32 v10.16b, v10.16b + rev32 v11.16b, v11.16b +#endif + +1: add t0.4s, v8.4s, k0.4s + mov dg0v.16b, dgav.16b + + add_update c, ev, k0, 8, 9, 10, 11, dgb + add_update c, od, k0, 9, 10, 11, 8 + add_update c, ev, k0, 10, 11, 8, 9 + add_update c, od, k0, 11, 8, 9, 10 + add_update c, ev, k1, 8, 9, 10, 11 + + add_update p, od, k1, 9, 10, 11, 8 + add_update p, ev, k1, 10, 11, 8, 9 + add_update p, od, k1, 11, 8, 9, 10 + add_update p, ev, k1, 8, 9, 10, 11 + add_update p, od, k2, 9, 10, 11, 8 + + add_update m, ev, k2, 10, 11, 8, 9 + add_update m, od, k2, 11, 8, 9, 10 + add_update m, ev, k2, 8, 9, 10, 11 + add_update m, od, k2, 9, 10, 11, 8 + add_update m, ev, k3, 10, 11, 8, 9 + + add_update p, od, k3, 11, 8, 9, 10 + add_only p, ev, k3, 9 + add_only p, od, k3, 10 + add_only p, ev, k3, 11 + add_only p, od + + /* update state */ + add dgbv.2s, dgbv.2s, dg1v.2s + add dgav.4s, dgav.4s, dg0v.4s + + /* loop on next block? */ + cbz w2, 2f + b 0b + + /* store new state */ +2: st1 {dgav.4s}, [x0] + str dgb, [x0, #16] + mov w0, w2 + ret +ENDPROC(sha1_armv8_ce_process) diff --git a/arch/arm/cpu/armv8/sha1_ce_glue.c b/arch/arm/cpu/armv8/sha1_ce_glue.c new file mode 100644 index 0000000..780b119 --- /dev/null +++ b/arch/arm/cpu/armv8/sha1_ce_glue.c @@ -0,0 +1,21 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * sha1_ce_glue.c - SHA-1 secure hash using ARMv8 Crypto Extensions + * + * Copyright (C) 2022 Linaro Ltd + */ + +#include +#include + +extern void sha1_armv8_ce_process(uint32_t state[5], uint8_t const *src, + uint32_t blocks); + +void sha1_process(sha1_context *ctx, const unsigned char *data, + unsigned int blocks) +{ + if (!blocks) + return; + + sha1_armv8_ce_process(ctx->state, data, blocks); +} -- 2.7.4