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Wed, 29 Jun 2022 11:29:10 -0700 From: Kartik To: , , , , , , , , , , , , , , , , Subject: [PATCH v2 1/6] dt-bindings: timer: Add Tegra186 & Tegra234 Timer Date: Wed, 29 Jun 2022 23:58:59 +0530 Message-ID: <1656527344-28861-2-git-send-email-kkartik@nvidia.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1656527344-28861-1-git-send-email-kkartik@nvidia.com> References: <1656527344-28861-1-git-send-email-kkartik@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 Content-Type: text/plain X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 98435ca9-c36e-4ff4-f97c-08da59fd4783 X-MS-TrafficTypeDiagnostic: CY5PR12MB6598:EE_ X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: W5FrsudLE7i+y3Jbx11m27iUrHrU6Lsn7b6eV3huQwWuWr6Rec49Oqfb1d8AMDBeg5wVRjM2LvY3y9o7dzdQAuh7prj/TXNAfyc/37XDnx4rDocbhwmOYC+WFARTCQjY3if8V2qCvsDB5h3skHcq0qlMaGVuTwaISFbCYmW6QgBljPHq+j+BD7/vuWBVW4pujT2GnLwVMxSdADNHGdxnGXditJsm8zPyqXVP5HGODi3Bkt7IOvAmufvuGvF0lQbOMVK/OEG7bgufN0IrWmQWSv1dbUSbHFJR2Srk98NIPPVUooh/6+NHCO5Kv0JkkCtAQAh71a4gCNgVnaHw8oMd+TUEP9RnGp8wjW12ALGedbR5NMuMv/7Uk67DsZgklnw5TqoYa1PhUYSUR0ztFhmMKVd48ah+MZ1HibxR7pPme+O6wmEj/+HjeezYHV0E0M4TQksRTwfp/0JLXzql+JAcDDVrLNVAtC0QduxW7WXr2FCAfu9uxOrqH8j5by7gctUbXRQRyE0j0CzEaQqG/ZQZEN13+VjlZ6lwQNb1abdMOLjzo3jtsyitCQDGI3kr9K7ROpALjVDOZzCrrRSwh60Ptei5cQfWQZL8heTYWsjFWzYLBD+Fo7f/f5LdfhwlF2Dq4ddEgdoENc6BBewZpWZ0u45SSmc0vtwzC2BjuE7SO8ghMm+2lnCh4C6tFmuG2FB2ZzLCbah9KEAeVRiR63KAj3MIMOYlTGmNJx2tPFF5F2eM6Kb4s7fB+eM2g3X3L1oJ1VouvWeaMZ2NwdZgZoeQZssx5c4FLczaYdDaR52Asw024z6hJbyvIO87cNs+8f870aVqKEQP5J6t3eaLVgh1b0IQOuZAcU/8hRpGORK6y9/6i5AtiYyRcu7rPeMxAtQRjEV/IKdE5kGyEWLIHqKbJKyt71KRfNNgoYDYeynN5VGURjgpPqo13vITG+k/PCPB X-Forefront-Antispam-Report: CIP:203.18.50.15;CTRY:HK;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:hkhybrid04.nvidia.com;CAT:NONE;SFS:(13230016)(4636009)(39860400002)(396003)(376002)(136003)(346002)(40470700004)(36840700001)(46966006)(2906002)(70586007)(478600001)(70206006)(8936002)(40460700003)(36756003)(40480700001)(5660300002)(316002)(110136005)(82310400005)(8676002)(2616005)(86362001)(7049001)(26005)(6666004)(186003)(47076005)(41300700001)(336012)(426003)(82740400003)(7696005)(921005)(356005)(36860700001)(7636003);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 29 Jun 2022 18:29:18.4338 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 98435ca9-c36e-4ff4-f97c-08da59fd4783 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[203.18.50.15];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: CO1NAM11FT006.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CY5PR12MB6598 Precedence: bulk List-ID: X-Mailing-List: linux-tegra@vger.kernel.org The Tegra186 timer provides ten 29-bit timer counters and one 32-bit timestamp counter. The Tegra234 timer provides sixteen 29-bit timer counters and one 32-bit timestamp counter. Each NV timer selects its timing reference signal from the 1 MHz reference generated by USEC, TSC or either clk_m or OSC. Each TMR can be programmed to generate one-shot, periodic, or watchdog interrupts. Signed-off-by: Kartik --- .../bindings/timer/nvidia,tegra186-timer.yaml | 111 ++++++++++++++++++ 1 file changed, 111 insertions(+) create mode 100644 Documentation/devicetree/bindings/timer/nvidia,tegra186-timer.yaml diff --git a/Documentation/devicetree/bindings/timer/nvidia,tegra186-timer.yaml b/Documentation/devicetree/bindings/timer/nvidia,tegra186-timer.yaml new file mode 100644 index 000000000000..5dc091532cd7 --- /dev/null +++ b/Documentation/devicetree/bindings/timer/nvidia,tegra186-timer.yaml @@ -0,0 +1,111 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: "http://devicetree.org/schemas/timer/nvidia,tegra186-timer.yaml#" +$schema: "http://devicetree.org/meta-schemas/core.yaml#" + +title: NVIDIA Tegra186 timer + +maintainers: + - Thierry Reding + +description: > + The Tegra timer provides 29-bit timer counters and a 32-bit timestamp + counter. Each NV timer selects its timing reference signal from the 1 MHz + reference generated by USEC, TSC or either clk_m or OSC. Each TMR can be + programmed to generate one-shot, periodic, or watchdog interrupts. + + +properties: + compatible: + oneOf: + - const: nvidia,tegra186-timer + description: > + The Tegra186 timer provides ten 29-bit timer counters. + - const: nvidia,tegra234-timer + description: > + The Tegra234 timer provides sixteen 29-bit timer counters. + + reg: + maxItems: 1 + + interrupts: true + +allOf: + - if: + properties: + compatible: + contains: + const: nvidia,tegra186-timer + then: + properties: + interrupts: + minItems: 1 + maxItems: 10 + description: > + A list of 10 interrupts; one per each timer channels 0 through 9. + + - if: + properties: + compatible: + contains: + const: nvidia,tegra234-timer + then: + properties: + interrupts: + minItems: 1 + maxItems: 16 + description: > + A list of 16 interrupts; one per each timer channels 0 through 15. + +required: + - compatible + - reg + - interrupts + +additionalProperties: false + +examples: + - | + #include + #include + + timer@3010000 { + compatible = "nvidia,tegra186-timer"; + reg = <0x03010000 0x000e0000>; + interrupts = , + , + , + , + , + , + , + , + , + ; + }; + + - | + #include + #include + + timer@2080000 { + compatible = "nvidia,tegra234-timer"; + reg = <0x02080000 0x00121000>; + interrupts = , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + }; -- 2.17.1