[PATCH V14 00/15] irqchip: Add LoongArch-related irqchip drivers

[PATCH V14 00/15] irqchip: Add LoongArch-related irqchip drivers

[Jianmin Lv]

LoongArch is a new RISC ISA, which is a bit like MIPS or RISC-V.
LoongArch includes a reduced 32-bit version (LA32R), a standard 32-bit
version (LA32S) and a 64-bit version (LA64). LoongArch use ACPI as its
boot protocol LoongArch-specific interrupt controllers (similar to APIC)
are already added in the ACPI Specification 6.5(which may be published in
early June this year and the board is reviewing the draft).

Currently, LoongArch based processors (e.g. Loongson-3A5000) can only
work together with LS7A chipsets. The irq chips in LoongArch computers
include CPUINTC (CPU Core Interrupt Controller), LIOINTC (Legacy I/O
Interrupt Controller), EIOINTC (Extended I/O Interrupt Controller),
HTVECINTC (Hyper-Transport Vector Interrupt Controller), PCH-PIC (Main
Interrupt Controller in LS7A chipset), PCH-LPC (LPC Interrupt Controller
in LS7A chipset) and PCH-MSI (MSI Interrupt Controller).

CPUINTC is a per-core controller (in CPU), LIOINTC/EIOINTC/HTVECINTC are
per-package controllers (in CPU), while PCH-PIC/PCH-LPC/PCH-MSI are all
controllers out of CPU (i.e., in chipsets). These controllers (in other
words, irqchips) are linked in a hierarchy, and there are two models of
hierarchy (legacy model and extended model). 

Legacy IRQ model:

In this model, the IPI (Inter-Processor Interrupt) and CPU Local Timer
interrupt go to CPUINTC directly, CPU UARTS interrupts go to LIOINTC,
while all other devices interrupts go to PCH-PIC/PCH-LPC/PCH-MSI and
gathered by HTVECINTC, and then go to LIOINTC, and then CPUINTC.

 +---------------------------------------------+
 |                                             |
 |    +-----+     +---------+     +-------+    |
 |    | IPI | --> | CPUINTC | <-- | Timer |    |
 |    +-----+     +---------+     +-------+    |
 |                     ^                       |
 |                     |                       |
 |                +---------+     +-------+    |
 |                | LIOINTC | <-- | UARTs |    |
 |                +---------+     +-------+    |
 |                     ^                       |
 |                     |                       |
 |               +-----------+                 |
 |               | HTVECINTC |                 |
 |               +-----------+                 |
 |                ^         ^                  |
 |                |         |                  |
 |          +---------+ +---------+            |
 |          | PCH-PIC | | PCH-MSI |            |
 |          +---------+ +---------+            |
 |            ^     ^           ^              |
 |            |     |           |              |
 |    +---------+ +---------+ +---------+      |
 |    | PCH-LPC | | Devices | | Devices |      |
 |    +---------+ +---------+ +---------+      |
 |         ^                                   |
 |         |                                   |
 |    +---------+                              |
 |    | Devices |                              |
 |    +---------+                              |
 |                                             |
 |                                             |
 +---------------------------------------------+

Extended IRQ model:

In this model, the IPI (Inter-Processor Interrupt) and CPU Local Timer
interrupt go to CPUINTC directly, CPU UARTS interrupts go to LIOINTC,
while all other devices interrupts go to PCH-PIC/PCH-LPC/PCH-MSI and
gathered by EIOINTC, and then go to to CPUINTC directly.

 +--------------------------------------------------------+
 |                                                        |
 |         +-----+     +---------+     +-------+          |
 |         | IPI | --> | CPUINTC | <-- | Timer |          |
 |         +-----+     +---------+     +-------+          |
 |                      ^       ^                         |
 |                      |       |                         |
 |               +---------+ +---------+     +-------+    |
 |               | EIOINTC | | LIOINTC | <-- | UARTs |    |
 |               +---------+ +---------+     +-------+    |
 |                ^       ^                               |
 |                |       |                               |
 |         +---------+ +---------+                        |
 |         | PCH-PIC | | PCH-MSI |                        |
 |         +---------+ +---------+                        |
 |           ^     ^           ^                          |
 |           |     |           |                          |
 |   +---------+ +---------+ +---------+                  |
 |   | PCH-LPC | | Devices | | Devices |                  |
 |   +---------+ +---------+ +---------+                  |
 |        ^                                               |
 |        |                                               |
 |   +---------+                                          |
 |   | Devices |                                          |
 |   +---------+                                          |
 |                                                        |
 |                                                        |
 +--------------------------------------------------------+

The hierarchy model is constructed by parsing irq contronler structures
in MADT. Some controllers((e.g. LIOINTC, HTVECINTC, EIOINTC and PCH-LPC)
are hardcodingly connected to their parents, so their irqdomins are
separately routed to their parents in a fixed way. Some controllers
(e.g. PCH-PIC and PCH-MSI) could be routed to different parents for different
CPU. The firmware will config EIOINTC for the newer CPU and config HTVECINTC
for old CPU in MADT. By this way, PCH-PIC and PCH-MSI irqdomain can only be
routed one parent irqdomin: HTVECINTC or EIOINTC.


Example of irqchip topology in a system with  two chipsets:

 +------------------------------------------------------------+
 |                                                            |
 |                     +------------------+                   |
 |                     |      CPUINTC     |                   |
 |                     +------------------+                   |
 |                     ^                  ^                   |
 |                     |                  |                   |
 |          +----------+                  +----------+        |
 |          | EIOINTC 0|                  | EIOINTC 1|        |
 |          +----------+                  +----------+        |
 |          ^          ^                  ^          ^        |
 |          |          |                  |          |        |
 | +----------+   +----------+   +----------+    +----------+ |
 | | PCH-PIC 0|   | PCH-MSI 0|   | PCH-PIC 1|    | PCH-MSI 1| |
 | +----------+   +----------+   +----------+    +----------+ |
 |                                                            |
 |                                                            |
 +------------------------------------------------------------+

For systems with two chipsets, there are tow group(consists of EIOINTC, PCH-PIC and PCH-MSI) irqdomains, 
and each group has same node id. So we defined a structure to mantain the relation of node and it's parent irqdomain.

struct acpi_vector_group {
        int node;
	int pci_segment;
        struct irq_domain *parent;
};

The initialization and use of acpi_vector_group array are following:

1 Entry of struct acpi_vector_group array initialization:

By parsing MCFG, the node id（from bit44-47 of Base Address）and pci segment are extracted. And from MADT, we have the node id of each EIOINTC.

entry.node = node id of pci segment
entry.pci_segment = pci segment (only for msi irqdomain)

By matching node id of entry and EIOINTC to set parent.

entry.parent = EIOINTC irqdomain(node id of EIOINTC == node id of pci segment)

2 Get parent irqdomain for PCH-PIC:

From MADT, we have the node id of each PCH-PIC(from bit44-47 of Base Address).
if (node of entry i == node of PCH-PIC)
	return entrys[i].parent;

3 Get parent irqdomain for PCH-MSI of pci segment:

	return entrys[i].parent; (i is the index of msi irqdomain)

4 How to select a correct irqdomain to map irq for a device?
For devices using legacy irq behind PCH-PIC, GSI is used to select correct PCH-PIC irqdomain.
For devices using msi irq behind PCH-MSI, the pci segmen of the device is used to select correct PCH-MSI irqdomain.

V1 -> V2:
1, Remove queued patches;
2, Move common logic of DT/ACPI probing to common functions;
3, Split .suspend()/.resume() functions to separate patches.

V2 -> V3:
1, Fix a bug for loongson-pch-pic probe;
2, Some minor improvements for LPC controller.

V3 -> V4:
1, Rework the CPU interrupt controller driver;
2, Some minor improvements for other controllers.

V4 -> V5:
1, Add a description of LoonArch's IRQ model;
2, Support multiple EIOINTCs in one system;
3, Some minor improvements for other controllers.

V5 -> V6:
1, Attach a fwnode to CPUINTC irq domain;
2, Use raw spinlock instead of generic spinlock;
3, Improve the method of restoring EIOINTC state;
4, Update documentation, comments and commit messages.

V6 -> V7:
1, Fix build warnings reported by kernel test robot.

V7 -> V8:
1, Add arguments sanity checking for irqchip init functions;
2, Support Loongson-3C5000 (One NUMA Node includes 4 EIOINTC Node).

V8 -> V9:
1, Rebase on 5.17-rc5;
2, Update cover letter;
3, Some small improvements.

V9 -> V10:
1, Rebase on 5.17-rc6;
2, Fix build warnings reported by kernel test robot.

V10 -> V11:
1, Rebase on 5.18-rc4;
2, Fix irq affinity setting for EIOINTC;
3, Fix hwirq allocation failure for EIOINTC.

V11 -> RFC:
1, Refactored the way to build irqchip hierarchy topology.

RFC -> RFC V2:
1, Move all IO-interrupt related code to driver/irqchip from arch directory.
2. Add description for an example of two chipsets system.

RFC V2 -> RFC V3:
1, Add support for multiple GSI domains
2, Use ACPI_GENERIC_GSI for GSI handling
3, Drop suspend-resume stuff
4, Export fwnode handles instead of irq domain handles

RFC V3 -> V12:
1, Address patch attributions of the patch series

V12 -> V13
1 Based on 5.19-rc2
2 Remove arch specified gsi code
3 Split some 'common' code into the various drivers where they belong.
4 Allow acpi_gsi_to_irq() to have an arch-specific fallback

V13 -> V14
1 Add LoongArch-specified APICs definition
2 Use the way in CPUINTC driver to call pch-pic and pch-msi entry
3 Fix compiling and regression issue for OF path

Huacai Chen (8):
  ACPICA: MADT: Add LoongArch APICs support
  irqchip: Add Loongson PCH LPC controller support
  irqchip/loongson-pch-pic: Add ACPI init support
  irqchip/loongson-pch-msi: Add ACPI init support
  irqchip/loongson-htvec: Add ACPI init support
  irqchip/loongson-liointc: Add ACPI init support
  irqchip: Add Loongson Extended I/O interrupt controller support
  irqchip: Add LoongArch CPU interrupt controller support

Jianmin Lv (5):
  genirq/generic_chip: export irq_unmap_generic_chip
  LoongArch: Use ACPI_GENERIC_GSI for gsi handling
  LoongArch: prepare to support multiple pch-pic and pch-msi irqdomain
  irqchip / ACPI: Introduce ACPI_IRQ_MODEL_LPIC for LoongArch
  LoongArch: Fix irq number for timer and ipi

Marc Zyngier (2):
  APCI: irq: Add support for multiple GSI domains
  ACPI: irq: Allow acpi_gsi_to_irq() to have an arch-specific fallback

 arch/loongarch/Kconfig                      |   1 +
 arch/loongarch/include/asm/irq.h            |  42 ++-
 arch/loongarch/kernel/acpi.c                |  65 -----
 arch/loongarch/kernel/irq.c                 |  45 ++-
 arch/loongarch/kernel/time.c                |   2 +-
 arch/mips/include/asm/mach-loongson64/irq.h |   2 +-
 drivers/acpi/bus.c                          |   3 +
 drivers/acpi/irq.c                          |  58 ++--
 drivers/irqchip/Kconfig                     |  28 ++
 drivers/irqchip/Makefile                    |   3 +
 drivers/irqchip/irq-gic-v3.c                |  18 +-
 drivers/irqchip/irq-gic.c                   |  18 +-
 drivers/irqchip/irq-loongarch-cpu.c         | 169 ++++++++++++
 drivers/irqchip/irq-loongson-eiointc.c      | 413 ++++++++++++++++++++++++++++
 drivers/irqchip/irq-loongson-htvec.c        | 145 +++++++---
 drivers/irqchip/irq-loongson-liointc.c      | 227 ++++++++++-----
 drivers/irqchip/irq-loongson-pch-lpc.c      | 207 ++++++++++++++
 drivers/irqchip/irq-loongson-pch-msi.c      | 131 ++++++---
 drivers/irqchip/irq-loongson-pch-pic.c      | 177 +++++++++---
 include/acpi/actbl2.h                       | 127 ++++++++-
 include/linux/acpi.h                        |   4 +-
 include/linux/cpuhotplug.h                  |   1 +
 include/linux/irq.h                         |   1 +
 kernel/irq/generic-chip.c                   |   2 +-
 24 files changed, 1578 insertions(+), 311 deletions(-)
 create mode 100644 drivers/irqchip/irq-loongarch-cpu.c
 create mode 100644 drivers/irqchip/irq-loongson-eiointc.c
 create mode 100644 drivers/irqchip/irq-loongson-pch-lpc.c

-- 
1.8.3.1

[PATCH V14 01/15] ACPICA: MADT: Add LoongArch APICs support

[Jianmin Lv]

From: Huacai Chen <chenhuacai@loongson.cn>

LoongArch-specific interrupt controllers (similar to APIC) are added
in the next revision of ACPI Specification (current revision is 6.4),
which including CORE_PIC (CPUINTC), LIO_PIC (LIOINTC), EIO_PIC (EIOINTC),
HT_PIC (HTVECINTC), BIO_PIC (PCHINTC), LPC_PIC (PCHLPC) and MSI_PIC
(PCHMSI). This patch add their definition.

ACPI changes of LoongArch-specific interrupt controllers have already
been approved in the ECRs, and will be public in the next revision of
ACPI Specification.

Reference: https://mantis.uefi.org/mantis/view.php?id=2203
Reference: https://mantis.uefi.org/mantis/view.php?id=2313
Signed-off-by: Jianmin Lv <lvjianmin@loongson.cn>
Signed-off-by: Huacai Chen <chenhuacai@loongson.cn>
---
 include/acpi/actbl2.h | 127 +++++++++++++++++++++++++++++++++++++++++++++++++-
 1 file changed, 125 insertions(+), 2 deletions(-)

diff --git a/include/acpi/actbl2.h b/include/acpi/actbl2.h
index 655102b..323bdd6 100644
--- a/include/acpi/actbl2.h
+++ b/include/acpi/actbl2.h
@@ -865,7 +865,14 @@ enum acpi_madt_type {
 	ACPI_MADT_TYPE_GENERIC_REDISTRIBUTOR = 14,
 	ACPI_MADT_TYPE_GENERIC_TRANSLATOR = 15,
 	ACPI_MADT_TYPE_MULTIPROC_WAKEUP = 16,
-	ACPI_MADT_TYPE_RESERVED = 17,	/* 17 to 0x7F are reserved */
+	ACPI_MADT_TYPE_CORE_PIC = 17,
+	ACPI_MADT_TYPE_LIO_PIC = 18,
+	ACPI_MADT_TYPE_HT_PIC = 19,
+	ACPI_MADT_TYPE_EIO_PIC = 20,
+	ACPI_MADT_TYPE_MSI_PIC = 21,
+	ACPI_MADT_TYPE_BIO_PIC = 22,
+	ACPI_MADT_TYPE_LPC_PIC = 23,
+	ACPI_MADT_TYPE_RESERVED = 24,	/* 24 to 0x7F are reserved */
 	ACPI_MADT_TYPE_OEM_RESERVED = 0x80	/* 0x80 to 0xFF are reserved for OEM use */
 };
 
@@ -1096,7 +1103,123 @@ struct acpi_madt_multiproc_wakeup_mailbox {
 
 #define ACPI_MP_WAKE_COMMAND_WAKEUP    1
 
-/* 17: OEM data */
+/* Values for Version field above */
+
+enum acpi_madt_core_pic_version {
+	ACPI_MADT_CORE_PIC_VERSION_NONE = 0,
+	ACPI_MADT_CORE_PIC_VERSION_V1 = 1,
+	ACPI_MADT_CORE_PIC_VERSION_RESERVED = 2	/* 2 and greater are reserved */
+};
+
+enum acpi_madt_lio_pic_version {
+	ACPI_MADT_LIO_PIC_VERSION_NONE = 0,
+	ACPI_MADT_LIO_PIC_VERSION_V1 = 1,
+	ACPI_MADT_LIO_PIC_VERSION_RESERVED = 2	/* 2 and greater are reserved */
+};
+
+enum acpi_madt_eio_pic_version {
+	ACPI_MADT_EIO_PIC_VERSION_NONE = 0,
+	ACPI_MADT_EIO_PIC_VERSION_V1 = 1,
+	ACPI_MADT_EIO_PIC_VERSION_RESERVED = 2	/* 2 and greater are reserved */
+};
+
+enum acpi_madt_ht_pic_version {
+	ACPI_MADT_HT_PIC_VERSION_NONE = 0,
+	ACPI_MADT_HT_PIC_VERSION_V1 = 1,
+	ACPI_MADT_HT_PIC_VERSION_RESERVED = 2	/* 2 and greater are reserved */
+};
+
+enum acpi_madt_bio_pic_version {
+	ACPI_MADT_BIO_PIC_VERSION_NONE = 0,
+	ACPI_MADT_BIO_PIC_VERSION_V1 = 1,
+	ACPI_MADT_BIO_PIC_VERSION_RESERVED = 2	/* 2 and greater are reserved */
+};
+
+enum acpi_madt_msi_pic_version {
+	ACPI_MADT_MSI_PIC_VERSION_NONE = 0,
+	ACPI_MADT_MSI_PIC_VERSION_V1 = 1,
+	ACPI_MADT_MSI_PIC_VERSION_RESERVED = 2	/* 2 and greater are reserved */
+};
+
+enum acpi_madt_lpc_pic_version {
+	ACPI_MADT_LPC_PIC_VERSION_NONE = 0,
+	ACPI_MADT_LPC_PIC_VERSION_V1 = 1,
+	ACPI_MADT_LPC_PIC_VERSION_RESERVED = 2	/* 2 and greater are reserved */
+};
+
+/* Core Interrupt Controller */
+
+struct acpi_madt_core_pic {
+	struct acpi_subtable_header header;
+	u8 version;
+	u32 processor_id;
+	u32 core_id;
+	u32 flags;
+};
+
+/* Legacy I/O Interrupt Controller */
+
+struct acpi_madt_lio_pic {
+	struct acpi_subtable_header header;
+	u8 version;
+	u64 address;
+	u16 size;
+	u8 cascade[2];
+	u32 cascade_map[2];
+};
+
+/* Extend I/O Interrupt Controller */
+
+struct acpi_madt_eio_pic {
+	struct acpi_subtable_header header;
+	u8 version;
+	u8 cascade;
+	u8 node;
+	u64 node_map;
+};
+
+/* HT Interrupt Controller */
+
+struct acpi_madt_ht_pic {
+	struct acpi_subtable_header header;
+	u8 version;
+	u64 address;
+	u16 size;
+	u8 cascade[8];
+};
+
+/* Bridge I/O Interrupt Controller */
+
+struct acpi_madt_bio_pic {
+	struct acpi_subtable_header header;
+	u8 version;
+	u64 address;
+	u16 size;
+	u16 id;
+	u16 gsi_base;
+};
+
+/* MSI Interrupt Controller */
+
+struct acpi_madt_msi_pic {
+	struct acpi_subtable_header header;
+	u8 version;
+	u64 msg_address;
+	u32 start;
+	u32 count;
+};
+
+/* LPC Interrupt Controller */
+
+struct acpi_madt_lpc_pic {
+	struct acpi_subtable_header header;
+	u8 version;
+	u64 address;
+	u16 size;
+	u8 cascade;
+};
+
+/* 80: OEM data */
 
 struct acpi_madt_oem_data {
 	u8 oem_data[0];
-- 
1.8.3.1

[PATCH V14 02/15] APCI: irq: Add support for multiple GSI domains

[Jianmin Lv]

From: Marc Zyngier <maz@kernel.org>

In an unfortunate departure from the ACPI spec, the LoongArch
architecture split its GSI space across multiple interrupt
controllers.

In order to be able to reuse the core code and prevent
architectures from reinventing an already square wheel, offer
the arch code the ability to register a dispatcher function
that will return the domain fwnode for a given GSI.

The ARM GIC drivers are updated to support this (with a single
domain, as intended).

Signed-off-by: Marc Zyngier <maz@kernel.org>
Cc: Hanjun Guo <guohanjun@huawei.com>
Cc: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Signed-off-by: Jianmin Lv <lvjianmin@loongson.cn>
---
 drivers/acpi/irq.c           | 40 +++++++++++++++++++++++++---------------
 drivers/irqchip/irq-gic-v3.c | 18 ++++++++++++------
 drivers/irqchip/irq-gic.c    | 18 ++++++++++++------
 include/linux/acpi.h         |  2 +-
 4 files changed, 50 insertions(+), 28 deletions(-)

diff --git a/drivers/acpi/irq.c b/drivers/acpi/irq.c
index c68e694..f0de768 100644
--- a/drivers/acpi/irq.c
+++ b/drivers/acpi/irq.c
@@ -12,7 +12,7 @@
 
 enum acpi_irq_model_id acpi_irq_model;
 
-static struct fwnode_handle *acpi_gsi_domain_id;
+static struct fwnode_handle *(*acpi_get_gsi_domain_id)(u32 gsi);
 
 /**
  * acpi_gsi_to_irq() - Retrieve the linux irq number for a given GSI
@@ -26,9 +26,10 @@
  */
 int acpi_gsi_to_irq(u32 gsi, unsigned int *irq)
 {
-	struct irq_domain *d = irq_find_matching_fwnode(acpi_gsi_domain_id,
-							DOMAIN_BUS_ANY);
+	struct irq_domain *d;
 
+	d = irq_find_matching_fwnode(acpi_get_gsi_domain_id(gsi),
+					DOMAIN_BUS_ANY);
 	*irq = irq_find_mapping(d, gsi);
 	/*
 	 * *irq == 0 means no mapping, that should
@@ -53,12 +54,12 @@ int acpi_register_gsi(struct device *dev, u32 gsi, int trigger,
 {
 	struct irq_fwspec fwspec;
 
-	if (WARN_ON(!acpi_gsi_domain_id)) {
+	fwspec.fwnode = acpi_get_gsi_domain_id(gsi);
+	if (WARN_ON(!fwspec.fwnode)) {
 		pr_warn("GSI: No registered irqchip, giving up\n");
 		return -EINVAL;
 	}
 
-	fwspec.fwnode = acpi_gsi_domain_id;
 	fwspec.param[0] = gsi;
 	fwspec.param[1] = acpi_dev_get_irq_type(trigger, polarity);
 	fwspec.param_count = 2;
@@ -73,13 +74,14 @@ int acpi_register_gsi(struct device *dev, u32 gsi, int trigger,
  */
 void acpi_unregister_gsi(u32 gsi)
 {
-	struct irq_domain *d = irq_find_matching_fwnode(acpi_gsi_domain_id,
-							DOMAIN_BUS_ANY);
+	struct irq_domain *d;
 	int irq;
 
 	if (WARN_ON(acpi_irq_model == ACPI_IRQ_MODEL_GIC && gsi < 16))
 		return;
 
+	d = irq_find_matching_fwnode(acpi_get_gsi_domain_id(gsi),
+				     DOMAIN_BUS_ANY);
 	irq = irq_find_mapping(d, gsi);
 	irq_dispose_mapping(irq);
 }
@@ -97,7 +99,8 @@ void acpi_unregister_gsi(u32 gsi)
  * The referenced device fwhandle or NULL on failure
  */
 static struct fwnode_handle *
-acpi_get_irq_source_fwhandle(const struct acpi_resource_source *source)
+acpi_get_irq_source_fwhandle(const struct acpi_resource_source *source,
+			     u32 gsi)
 {
 	struct fwnode_handle *result;
 	struct acpi_device *device;
@@ -105,7 +108,7 @@ void acpi_unregister_gsi(u32 gsi)
 	acpi_status status;
 
 	if (!source->string_length)
-		return acpi_gsi_domain_id;
+		return acpi_get_gsi_domain_id(gsi);
 
 	status = acpi_get_handle(NULL, source->string_ptr, &handle);
 	if (WARN_ON(ACPI_FAILURE(status)))
@@ -194,7 +197,7 @@ static acpi_status acpi_irq_parse_one_cb(struct acpi_resource *ares,
 			ctx->index -= irq->interrupt_count;
 			return AE_OK;
 		}
-		fwnode = acpi_gsi_domain_id;
+		fwnode = acpi_get_gsi_domain_id(irq->interrupts[ctx->index]);
 		acpi_irq_parse_one_match(fwnode, irq->interrupts[ctx->index],
 					 irq->triggering, irq->polarity,
 					 irq->shareable, ctx);
@@ -207,7 +210,8 @@ static acpi_status acpi_irq_parse_one_cb(struct acpi_resource *ares,
 			ctx->index -= eirq->interrupt_count;
 			return AE_OK;
 		}
-		fwnode = acpi_get_irq_source_fwhandle(&eirq->resource_source);
+		fwnode = acpi_get_irq_source_fwhandle(&eirq->resource_source,
+						      eirq->interrupts[ctx->index]);
 		acpi_irq_parse_one_match(fwnode, eirq->interrupts[ctx->index],
 					 eirq->triggering, eirq->polarity,
 					 eirq->shareable, ctx);
@@ -291,10 +295,10 @@ int acpi_irq_get(acpi_handle handle, unsigned int index, struct resource *res)
  *          GSI interrupts
  */
 void __init acpi_set_irq_model(enum acpi_irq_model_id model,
-			       struct fwnode_handle *fwnode)
+			       struct fwnode_handle *(*fn)(u32))
 {
 	acpi_irq_model = model;
-	acpi_gsi_domain_id = fwnode;
+	acpi_get_gsi_domain_id = fn;
 }
 
 /**
@@ -312,8 +316,14 @@ struct irq_domain *acpi_irq_create_hierarchy(unsigned int flags,
 					     const struct irq_domain_ops *ops,
 					     void *host_data)
 {
-	struct irq_domain *d = irq_find_matching_fwnode(acpi_gsi_domain_id,
-							DOMAIN_BUS_ANY);
+	struct irq_domain *d;
+
+	/* This only works for the GIC model... */
+	if (acpi_irq_model != ACPI_IRQ_MODEL_GIC)
+		return NULL;
+
+	d = irq_find_matching_fwnode(acpi_get_gsi_domain_id(0),
+				     DOMAIN_BUS_ANY);
 
 	if (!d)
 		return NULL;
diff --git a/drivers/irqchip/irq-gic-v3.c b/drivers/irqchip/irq-gic-v3.c
index 5c1cf90..c664703 100644
--- a/drivers/irqchip/irq-gic-v3.c
+++ b/drivers/irqchip/irq-gic-v3.c
@@ -2360,11 +2360,17 @@ static void __init gic_acpi_setup_kvm_info(void)
 	vgic_set_kvm_info(&gic_v3_kvm_info);
 }
 
+static struct fwnode_handle *gsi_domain_handle;
+
+static struct fwnode_handle *gic_v3_get_gsi_domain_id(u32 gsi)
+{
+	return gsi_domain_handle;
+}
+
 static int __init
 gic_acpi_init(union acpi_subtable_headers *header, const unsigned long end)
 {
 	struct acpi_madt_generic_distributor *dist;
-	struct fwnode_handle *domain_handle;
 	size_t size;
 	int i, err;
 
@@ -2396,18 +2402,18 @@ static void __init gic_acpi_setup_kvm_info(void)
 	if (err)
 		goto out_redist_unmap;
 
-	domain_handle = irq_domain_alloc_fwnode(&dist->base_address);
-	if (!domain_handle) {
+	gsi_domain_handle = irq_domain_alloc_fwnode(&dist->base_address);
+	if (!gsi_domain_handle) {
 		err = -ENOMEM;
 		goto out_redist_unmap;
 	}
 
 	err = gic_init_bases(acpi_data.dist_base, acpi_data.redist_regs,
-			     acpi_data.nr_redist_regions, 0, domain_handle);
+			     acpi_data.nr_redist_regions, 0, gsi_domain_handle);
 	if (err)
 		goto out_fwhandle_free;
 
-	acpi_set_irq_model(ACPI_IRQ_MODEL_GIC, domain_handle);
+	acpi_set_irq_model(ACPI_IRQ_MODEL_GIC, gic_v3_get_gsi_domain_id);
 
 	if (static_branch_likely(&supports_deactivate_key))
 		gic_acpi_setup_kvm_info();
@@ -2415,7 +2421,7 @@ static void __init gic_acpi_setup_kvm_info(void)
 	return 0;
 
 out_fwhandle_free:
-	irq_domain_free_fwnode(domain_handle);
+	irq_domain_free_fwnode(gsi_domain_handle);
 out_redist_unmap:
 	for (i = 0; i < acpi_data.nr_redist_regions; i++)
 		if (acpi_data.redist_regs[i].redist_base)
diff --git a/drivers/irqchip/irq-gic.c b/drivers/irqchip/irq-gic.c
index 820404c..4c7bae0 100644
--- a/drivers/irqchip/irq-gic.c
+++ b/drivers/irqchip/irq-gic.c
@@ -1682,11 +1682,17 @@ static void __init gic_acpi_setup_kvm_info(void)
 	vgic_set_kvm_info(&gic_v2_kvm_info);
 }
 
+static struct fwnode_handle *gsi_domain_handle;
+
+static struct fwnode_handle *gic_v2_get_gsi_domain_id(u32 gsi)
+{
+	return gsi_domain_handle;
+}
+
 static int __init gic_v2_acpi_init(union acpi_subtable_headers *header,
 				   const unsigned long end)
 {
 	struct acpi_madt_generic_distributor *dist;
-	struct fwnode_handle *domain_handle;
 	struct gic_chip_data *gic = &gic_data[0];
 	int count, ret;
 
@@ -1724,22 +1730,22 @@ static int __init gic_v2_acpi_init(union acpi_subtable_headers *header,
 	/*
 	 * Initialize GIC instance zero (no multi-GIC support).
 	 */
-	domain_handle = irq_domain_alloc_fwnode(&dist->base_address);
-	if (!domain_handle) {
+	gsi_domain_handle = irq_domain_alloc_fwnode(&dist->base_address);
+	if (!gsi_domain_handle) {
 		pr_err("Unable to allocate domain handle\n");
 		gic_teardown(gic);
 		return -ENOMEM;
 	}
 
-	ret = __gic_init_bases(gic, domain_handle);
+	ret = __gic_init_bases(gic, gsi_domain_handle);
 	if (ret) {
 		pr_err("Failed to initialise GIC\n");
-		irq_domain_free_fwnode(domain_handle);
+		irq_domain_free_fwnode(gsi_domain_handle);
 		gic_teardown(gic);
 		return ret;
 	}
 
-	acpi_set_irq_model(ACPI_IRQ_MODEL_GIC, domain_handle);
+	acpi_set_irq_model(ACPI_IRQ_MODEL_GIC, gic_v2_get_gsi_domain_id);
 
 	if (IS_ENABLED(CONFIG_ARM_GIC_V2M))
 		gicv2m_init(NULL, gic_data[0].domain);
diff --git a/include/linux/acpi.h b/include/linux/acpi.h
index 4f82a5b..957e23f 100644
--- a/include/linux/acpi.h
+++ b/include/linux/acpi.h
@@ -356,7 +356,7 @@ static inline bool acpi_sci_irq_valid(void)
 int acpi_isa_irq_to_gsi (unsigned isa_irq, u32 *gsi);
 
 void acpi_set_irq_model(enum acpi_irq_model_id model,
-			struct fwnode_handle *fwnode);
+			struct fwnode_handle *(*)(u32));
 
 struct irq_domain *acpi_irq_create_hierarchy(unsigned int flags,
 					     unsigned int size,
-- 
1.8.3.1

[PATCH V14 03/15] ACPI: irq: Allow acpi_gsi_to_irq() to have an arch-specific fallback

[Jianmin Lv]

From: Marc Zyngier <maz@kernel.org>

It appears that the generic version of acpi_gsi_to_irq() doesn't
fallback to establishing a mapping if there is no pre-existing
one while the x86 version does.

While arm64 seems unaffected by it, LoongArch is relying on the x86
behaviour. In an effort to prevent new architectures from reinventing
the proverbial wheel, provide an optional callback that the arch code
can set to restore the x86 behaviour.

Hopefully we can eventually get rid of this in the future once
the expected behaviour has been clarified.

Reported-by: Jianmin Lv <lvjianmin@loongson.cn>
Signed-off-by: Marc Zyngier <maz@kernel.org>
Signed-off-by: Jianmin Lv <lvjianmin@loongson.cn>
---
 drivers/acpi/irq.c   | 18 ++++++++++++++++--
 include/linux/acpi.h |  1 +
 2 files changed, 17 insertions(+), 2 deletions(-)

diff --git a/drivers/acpi/irq.c b/drivers/acpi/irq.c
index f0de768..cd87e0b 100644
--- a/drivers/acpi/irq.c
+++ b/drivers/acpi/irq.c
@@ -13,6 +13,7 @@
 enum acpi_irq_model_id acpi_irq_model;
 
 static struct fwnode_handle *(*acpi_get_gsi_domain_id)(u32 gsi);
+static int (*acpi_gsi_to_irq_fallback)(u32 gsi);
 
 /**
  * acpi_gsi_to_irq() - Retrieve the linux irq number for a given GSI
@@ -32,9 +33,12 @@ int acpi_gsi_to_irq(u32 gsi, unsigned int *irq)
 					DOMAIN_BUS_ANY);
 	*irq = irq_find_mapping(d, gsi);
 	/*
-	 * *irq == 0 means no mapping, that should
-	 * be reported as a failure
+	 * *irq == 0 means no mapping, that should be reported as a
+	 * failure, unless there is an arch-specific fallback handler.
 	 */
+	if (!*irq && acpi_gsi_to_irq_fallback)
+		*irq = acpi_gsi_to_irq_fallback(gsi);
+
 	return (*irq > 0) ? 0 : -EINVAL;
 }
 EXPORT_SYMBOL_GPL(acpi_gsi_to_irq);
@@ -302,6 +306,16 @@ void __init acpi_set_irq_model(enum acpi_irq_model_id model,
 }
 
 /**
+ * acpi_set_gsi_to_irq_fallback - Register a GSI transfer
+ * callback to fallback to arch specified implementation.
+ * @fn: arch-specific fallback handler
+ */
+void __init acpi_set_gsi_to_irq_fallback(int (*fn)(u32))
+{
+	acpi_gsi_to_irq_fallback = fn;
+}
+
+/**
  * acpi_irq_create_hierarchy - Create a hierarchical IRQ domain with the default
  *                             GSI domain as its parent.
  * @flags:      Irq domain flags associated with the domain
diff --git a/include/linux/acpi.h b/include/linux/acpi.h
index 957e23f..71d3719 100644
--- a/include/linux/acpi.h
+++ b/include/linux/acpi.h
@@ -357,6 +357,7 @@ static inline bool acpi_sci_irq_valid(void)
 
 void acpi_set_irq_model(enum acpi_irq_model_id model,
 			struct fwnode_handle *(*)(u32));
+void acpi_set_gsi_to_irq_fallback(int (*)(u32));
 
 struct irq_domain *acpi_irq_create_hierarchy(unsigned int flags,
 					     unsigned int size,
-- 
1.8.3.1

[PATCH V14 04/15] genirq/generic_chip: export irq_unmap_generic_chip

[Jianmin Lv]

Some irq controllers have to re-implement a private version for
irq_generic_chip_ops, because they have a different xlate to translate
hwirq. Export irq_unmap_generic_chip for reusing in user defined
ops.

Signed-off-by: Jianmin Lv <lvjianmin@loongson.cn>
---
 include/linux/irq.h       | 1 +
 kernel/irq/generic-chip.c | 2 +-
 2 files changed, 2 insertions(+), 1 deletion(-)

diff --git a/include/linux/irq.h b/include/linux/irq.h
index 5053082..83a4574 100644
--- a/include/linux/irq.h
+++ b/include/linux/irq.h
@@ -1121,6 +1121,7 @@ struct irq_domain_chip_generic {
 /* Setup functions for irq_chip_generic */
 int irq_map_generic_chip(struct irq_domain *d, unsigned int virq,
 			 irq_hw_number_t hw_irq);
+void irq_unmap_generic_chip(struct irq_domain *d, unsigned int virq);
 struct irq_chip_generic *
 irq_alloc_generic_chip(const char *name, int nr_ct, unsigned int irq_base,
 		       void __iomem *reg_base, irq_flow_handler_t handler);
diff --git a/kernel/irq/generic-chip.c b/kernel/irq/generic-chip.c
index f0862eb..c653cd3 100644
--- a/kernel/irq/generic-chip.c
+++ b/kernel/irq/generic-chip.c
@@ -431,7 +431,7 @@ int irq_map_generic_chip(struct irq_domain *d, unsigned int virq,
 	return 0;
 }
 
-static void irq_unmap_generic_chip(struct irq_domain *d, unsigned int virq)
+void irq_unmap_generic_chip(struct irq_domain *d, unsigned int virq)
 {
 	struct irq_data *data = irq_domain_get_irq_data(d, virq);
 	struct irq_domain_chip_generic *dgc = d->gc;
-- 
1.8.3.1

[PATCH V14 05/15] LoongArch: Use ACPI_GENERIC_GSI for gsi handling

[Jianmin Lv]

For LoongArch, generic gsi code(driver/acpi/irq.c) can be
reused after following patchs:

APCI: irq: Add support for multiple GSI domains
ACPI: irq: Allow acpi_gsi_to_irq() to have an arch-specific fallback

So, config ACPI_GENERIC_GSI for LoongArch with removing the gsi code
in arch directory.

Signed-off-by: Jianmin Lv <lvjianmin@loongson.cn>
---
 arch/loongarch/Kconfig       |  1 +
 arch/loongarch/kernel/acpi.c | 65 --------------------------------------------
 2 files changed, 1 insertion(+), 65 deletions(-)

diff --git a/arch/loongarch/Kconfig b/arch/loongarch/Kconfig
index 1920d52..7f98fc0 100644
--- a/arch/loongarch/Kconfig
+++ b/arch/loongarch/Kconfig
@@ -112,6 +112,7 @@ config LOONGARCH
 	select TRACE_IRQFLAGS_SUPPORT
 	select USE_PERCPU_NUMA_NODE_ID
 	select ZONE_DMA32
+	select ACPI_GENERIC_GSI if ACPI
 
 config 32BIT
 	bool
diff --git a/arch/loongarch/kernel/acpi.c b/arch/loongarch/kernel/acpi.c
index bb729ee..03aa145 100644
--- a/arch/loongarch/kernel/acpi.c
+++ b/arch/loongarch/kernel/acpi.c
@@ -25,7 +25,6 @@
 int acpi_strict = 1; /* We have no workarounds on LoongArch */
 int num_processors;
 int disabled_cpus;
-enum acpi_irq_model_id acpi_irq_model = ACPI_IRQ_MODEL_PLATFORM;
 
 u64 acpi_saved_sp;
 
@@ -33,70 +32,6 @@
 
 #define PREFIX			"ACPI: "
 
-int acpi_gsi_to_irq(u32 gsi, unsigned int *irqp)
-{
-	if (irqp != NULL)
-		*irqp = acpi_register_gsi(NULL, gsi, -1, -1);
-	return (*irqp >= 0) ? 0 : -EINVAL;
-}
-EXPORT_SYMBOL_GPL(acpi_gsi_to_irq);
-
-int acpi_isa_irq_to_gsi(unsigned int isa_irq, u32 *gsi)
-{
-	if (gsi)
-		*gsi = isa_irq;
-	return 0;
-}
-
-/*
- * success: return IRQ number (>=0)
- * failure: return < 0
- */
-int acpi_register_gsi(struct device *dev, u32 gsi, int trigger, int polarity)
-{
-	struct irq_fwspec fwspec;
-
-	switch (gsi) {
-	case GSI_MIN_CPU_IRQ ... GSI_MAX_CPU_IRQ:
-		fwspec.fwnode = liointc_domain->fwnode;
-		fwspec.param[0] = gsi - GSI_MIN_CPU_IRQ;
-		fwspec.param_count = 1;
-
-		return irq_create_fwspec_mapping(&fwspec);
-
-	case GSI_MIN_LPC_IRQ ... GSI_MAX_LPC_IRQ:
-		if (!pch_lpc_domain)
-			return -EINVAL;
-
-		fwspec.fwnode = pch_lpc_domain->fwnode;
-		fwspec.param[0] = gsi - GSI_MIN_LPC_IRQ;
-		fwspec.param[1] = acpi_dev_get_irq_type(trigger, polarity);
-		fwspec.param_count = 2;
-
-		return irq_create_fwspec_mapping(&fwspec);
-
-	case GSI_MIN_PCH_IRQ ... GSI_MAX_PCH_IRQ:
-		if (!pch_pic_domain[0])
-			return -EINVAL;
-
-		fwspec.fwnode = pch_pic_domain[0]->fwnode;
-		fwspec.param[0] = gsi - GSI_MIN_PCH_IRQ;
-		fwspec.param[1] = IRQ_TYPE_LEVEL_HIGH;
-		fwspec.param_count = 2;
-
-		return irq_create_fwspec_mapping(&fwspec);
-	}
-
-	return -EINVAL;
-}
-EXPORT_SYMBOL_GPL(acpi_register_gsi);
-
-void acpi_unregister_gsi(u32 gsi)
-{
-
-}
-EXPORT_SYMBOL_GPL(acpi_unregister_gsi);
-
 void __init __iomem * __acpi_map_table(unsigned long phys, unsigned long size)
 {
 
-- 
1.8.3.1

[PATCH V14 06/15] irqchip: Add Loongson PCH LPC controller support

[Jianmin Lv]

From: Huacai Chen <chenhuacai@loongson.cn>

PCH-LPC stands for "LPC Interrupts" that described in Section 24.3 of
"Loongson 7A1000 Bridge User Manual". For more information please refer
Documentation/loongarch/irq-chip-model.rst.

Co-developed-by: Jianmin Lv <lvjianmin@loongson.cn>
Signed-off-by: Jianmin Lv <lvjianmin@loongson.cn>
Signed-off-by: Huacai Chen <chenhuacai@loongson.cn>
---
 arch/loongarch/include/asm/irq.h       |   4 +-
 arch/loongarch/kernel/irq.c            |   1 -
 drivers/irqchip/Kconfig                |   8 ++
 drivers/irqchip/Makefile               |   1 +
 drivers/irqchip/irq-loongson-pch-lpc.c | 208 +++++++++++++++++++++++++++++++++
 5 files changed, 219 insertions(+), 3 deletions(-)
 create mode 100644 drivers/irqchip/irq-loongson-pch-lpc.c

diff --git a/arch/loongarch/include/asm/irq.h b/arch/loongarch/include/asm/irq.h
index ace3ea6..48c0ce4 100644
--- a/arch/loongarch/include/asm/irq.h
+++ b/arch/loongarch/include/asm/irq.h
@@ -104,7 +104,7 @@ struct irq_domain *eiointc_acpi_init(struct irq_domain *parent,
 
 struct irq_domain *htvec_acpi_init(struct irq_domain *parent,
 					struct acpi_madt_ht_pic *acpi_htvec);
-struct irq_domain *pch_lpc_acpi_init(struct irq_domain *parent,
+int pch_lpc_acpi_init(struct irq_domain *parent,
 					struct acpi_madt_lpc_pic *acpi_pchlpc);
 struct irq_domain *pch_msi_acpi_init(struct irq_domain *parent,
 					struct acpi_madt_msi_pic *acpi_pchmsi);
@@ -121,7 +121,7 @@ struct irq_domain *pch_pic_acpi_init(struct irq_domain *parent,
 
 extern struct irq_domain *cpu_domain;
 extern struct irq_domain *liointc_domain;
-extern struct irq_domain *pch_lpc_domain;
+extern struct fwnode_handle *pch_lpc_handle;
 extern struct irq_domain *pch_msi_domain[MAX_IO_PICS];
 extern struct irq_domain *pch_pic_domain[MAX_IO_PICS];
 
diff --git a/arch/loongarch/kernel/irq.c b/arch/loongarch/kernel/irq.c
index b34b8d7..07d6059 100644
--- a/arch/loongarch/kernel/irq.c
+++ b/arch/loongarch/kernel/irq.c
@@ -27,7 +27,6 @@
 
 struct irq_domain *cpu_domain;
 struct irq_domain *liointc_domain;
-struct irq_domain *pch_lpc_domain;
 struct irq_domain *pch_msi_domain[MAX_IO_PICS];
 struct irq_domain *pch_pic_domain[MAX_IO_PICS];
 
diff --git a/drivers/irqchip/Kconfig b/drivers/irqchip/Kconfig
index 1f23a6b..c1d527f 100644
--- a/drivers/irqchip/Kconfig
+++ b/drivers/irqchip/Kconfig
@@ -591,6 +591,14 @@ config LOONGSON_PCH_MSI
 	help
 	  Support for the Loongson PCH MSI Controller.
 
+config LOONGSON_PCH_LPC
+	bool "Loongson PCH LPC Controller"
+	depends on MACH_LOONGSON64
+	default (MACH_LOONGSON64 && LOONGARCH)
+	select IRQ_DOMAIN_HIERARCHY
+	help
+	  Support for the Loongson PCH LPC Controller.
+
 config MST_IRQ
 	bool "MStar Interrupt Controller"
 	depends on ARCH_MEDIATEK || ARCH_MSTARV7 || COMPILE_TEST
diff --git a/drivers/irqchip/Makefile b/drivers/irqchip/Makefile
index 5b67450..242b8b3 100644
--- a/drivers/irqchip/Makefile
+++ b/drivers/irqchip/Makefile
@@ -108,6 +108,7 @@ obj-$(CONFIG_LOONGSON_HTPIC)		+= irq-loongson-htpic.o
 obj-$(CONFIG_LOONGSON_HTVEC)		+= irq-loongson-htvec.o
 obj-$(CONFIG_LOONGSON_PCH_PIC)		+= irq-loongson-pch-pic.o
 obj-$(CONFIG_LOONGSON_PCH_MSI)		+= irq-loongson-pch-msi.o
+obj-$(CONFIG_LOONGSON_PCH_LPC)		+= irq-loongson-pch-lpc.o
 obj-$(CONFIG_MST_IRQ)			+= irq-mst-intc.o
 obj-$(CONFIG_SL28CPLD_INTC)		+= irq-sl28cpld.o
 obj-$(CONFIG_MACH_REALTEK_RTL)		+= irq-realtek-rtl.o
diff --git a/drivers/irqchip/irq-loongson-pch-lpc.c b/drivers/irqchip/irq-loongson-pch-lpc.c
new file mode 100644
index 0000000..2b83ab9
--- /dev/null
+++ b/drivers/irqchip/irq-loongson-pch-lpc.c
@@ -0,0 +1,208 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Loongson LPC Interrupt Controller support
+ *
+ * Copyright (C) 2020-2022 Loongson Technology Corporation Limited
+ */
+
+#define pr_fmt(fmt) "lpc: " fmt
+
+#include <linux/interrupt.h>
+#include <linux/irq.h>
+#include <linux/irqchip.h>
+#include <linux/irqchip/chained_irq.h>
+#include <linux/irqdomain.h>
+#include <linux/kernel.h>
+
+/* Registers */
+#define LPC_INT_CTL		0x00
+#define LPC_INT_ENA		0x04
+#define LPC_INT_STS		0x08
+#define LPC_INT_CLR		0x0c
+#define LPC_INT_POL		0x10
+#define LPC_COUNT		16
+
+/* LPC_INT_CTL */
+#define LPC_INT_CTL_EN		BIT(31)
+
+struct pch_lpc {
+	void __iomem		*base;
+	struct irq_domain	*lpc_domain;
+	raw_spinlock_t		lpc_lock;
+	u32			saved_reg_ctl;
+	u32			saved_reg_ena;
+	u32			saved_reg_pol;
+};
+
+struct fwnode_handle *pch_lpc_handle;
+
+static void lpc_irq_ack(struct irq_data *d)
+{
+	unsigned long flags;
+	struct pch_lpc *priv = d->domain->host_data;
+
+	raw_spin_lock_irqsave(&priv->lpc_lock, flags);
+	writel(0x1 << d->hwirq, priv->base + LPC_INT_CLR);
+	raw_spin_unlock_irqrestore(&priv->lpc_lock, flags);
+}
+
+static void lpc_irq_mask(struct irq_data *d)
+{
+	unsigned long flags;
+	struct pch_lpc *priv = d->domain->host_data;
+
+	raw_spin_lock_irqsave(&priv->lpc_lock, flags);
+	writel(readl(priv->base + LPC_INT_ENA) & (~(0x1 << (d->hwirq))),
+			priv->base + LPC_INT_ENA);
+	raw_spin_unlock_irqrestore(&priv->lpc_lock, flags);
+}
+
+static void lpc_irq_unmask(struct irq_data *d)
+{
+	unsigned long flags;
+	struct pch_lpc *priv = d->domain->host_data;
+
+	raw_spin_lock_irqsave(&priv->lpc_lock, flags);
+	writel(readl(priv->base + LPC_INT_ENA) | (0x1 << (d->hwirq)),
+			priv->base + LPC_INT_ENA);
+	raw_spin_unlock_irqrestore(&priv->lpc_lock, flags);
+}
+
+static int lpc_irq_set_type(struct irq_data *d, unsigned int type)
+{
+	u32 val;
+	u32 mask = 0x1 << (d->hwirq);
+	struct pch_lpc *priv = d->domain->host_data;
+
+	if (!(type & IRQ_TYPE_LEVEL_MASK))
+		return 0;
+
+	val = readl(priv->base + LPC_INT_POL);
+
+	if (type == IRQ_TYPE_LEVEL_HIGH)
+		val |= mask;
+	else
+		val &= ~mask;
+
+	writel(val, priv->base + LPC_INT_POL);
+
+	return 0;
+}
+
+static const struct irq_chip pch_lpc_irq_chip = {
+	.name			= "PCH LPC",
+	.irq_mask		= lpc_irq_mask,
+	.irq_unmask		= lpc_irq_unmask,
+	.irq_ack		= lpc_irq_ack,
+	.irq_set_type		= lpc_irq_set_type,
+	.flags			= IRQCHIP_SKIP_SET_WAKE,
+};
+
+static void lpc_irq_dispatch(struct irq_desc *desc)
+{
+	u32 pending, bit;
+	struct irq_chip *chip = irq_desc_get_chip(desc);
+	struct pch_lpc *priv = irq_desc_get_handler_data(desc);
+
+	chained_irq_enter(chip, desc);
+
+	pending = readl(priv->base + LPC_INT_ENA);
+	pending &= readl(priv->base + LPC_INT_STS);
+	if (!pending)
+		spurious_interrupt();
+
+	while (pending) {
+		bit = __ffs(pending);
+
+		generic_handle_domain_irq(priv->lpc_domain, bit);
+		pending &= ~BIT(bit);
+	}
+	chained_irq_exit(chip, desc);
+}
+
+static int pch_lpc_map(struct irq_domain *d, unsigned int irq,
+			irq_hw_number_t hw)
+{
+	irq_set_chip_and_handler(irq, &pch_lpc_irq_chip, handle_level_irq);
+	return 0;
+}
+
+static const struct irq_domain_ops pch_lpc_domain_ops = {
+	.map 		= pch_lpc_map,
+	.translate	= irq_domain_translate_twocell,
+};
+
+static void pch_lpc_reset(struct pch_lpc *priv)
+{
+	/* Enable the LPC interrupt, bit31: en  bit30: edge */
+	writel(LPC_INT_CTL_EN, priv->base + LPC_INT_CTL);
+	writel(0, priv->base + LPC_INT_ENA);
+	/* Clear all 18-bit interrpt bit */
+	writel(GENMASK(17, 0), priv->base + LPC_INT_CLR);
+}
+
+static int pch_lpc_disabled(struct pch_lpc *priv)
+{
+	return (readl(priv->base + LPC_INT_ENA) == 0xffffffff) &&
+			(readl(priv->base + LPC_INT_STS) == 0xffffffff);
+}
+
+int __init pch_lpc_acpi_init(struct irq_domain *parent,
+					struct acpi_madt_lpc_pic *acpi_pchlpc)
+{
+	int parent_irq;
+	struct pch_lpc *priv;
+	struct irq_fwspec fwspec;
+	struct fwnode_handle *irq_handle;
+
+	if (!acpi_pchlpc)
+		return -EINVAL;
+
+	priv = kzalloc(sizeof(*priv), GFP_KERNEL);
+	if (!priv)
+		return -ENOMEM;
+
+	raw_spin_lock_init(&priv->lpc_lock);
+
+	priv->base = ioremap(acpi_pchlpc->address, acpi_pchlpc->size);
+	if (!priv->base)
+		goto free_priv;
+
+	if (pch_lpc_disabled(priv)) {
+		pr_err("Failed to get LPC status\n");
+		goto iounmap_base;
+	}
+
+	irq_handle = irq_domain_alloc_named_fwnode("lpcintc");
+	if (!irq_handle) {
+		pr_err("Unable to allocate domain handle\n");
+		goto iounmap_base;
+	}
+
+	priv->lpc_domain = irq_domain_create_linear(irq_handle, LPC_COUNT,
+					&pch_lpc_domain_ops, priv);
+	if (!priv->lpc_domain) {
+		pr_err("Failed to create IRQ domain\n");
+		goto free_irq_handle;
+	}
+	pch_lpc_reset(priv);
+
+	fwspec.fwnode = parent->fwnode;
+	fwspec.param[0] = acpi_pchlpc->cascade;
+	fwspec.param[1] = IRQ_TYPE_LEVEL_HIGH;
+	fwspec.param_count = 2;
+	parent_irq = irq_create_fwspec_mapping(&fwspec);
+	irq_set_chained_handler_and_data(parent_irq, lpc_irq_dispatch, priv);
+
+	pch_lpc_handle = irq_handle;
+	return 0;
+
+free_irq_handle:
+	irq_domain_free_fwnode(irq_handle);
+iounmap_base:
+	iounmap(priv->base);
+free_priv:
+	kfree(priv);
+
+	return -ENOMEM;
+}
-- 
1.8.3.1

[PATCH V14 07/15] irqchip/loongson-pch-pic: Add ACPI init support

[Jianmin Lv]

From: Huacai Chen <chenhuacai@loongson.cn>

PCH-PIC/PCH-MSI stands for "Interrupt Controller" that described in
Section 5 of "Loongson 7A1000 Bridge User Manual". For more information
please refer Documentation/loongarch/irq-chip-model.rst.

Co-developed-by: Jianmin Lv <lvjianmin@loongson.cn>
Signed-off-by: Jianmin Lv <lvjianmin@loongson.cn>
Signed-off-by: Huacai Chen <chenhuacai@loongson.cn>
---
 arch/loongarch/include/asm/irq.h            |   5 +-
 arch/loongarch/kernel/irq.c                 |   1 -
 arch/mips/include/asm/mach-loongson64/irq.h |   2 +-
 drivers/irqchip/irq-loongson-pch-pic.c      | 178 +++++++++++++++++++++++-----
 4 files changed, 151 insertions(+), 35 deletions(-)

diff --git a/arch/loongarch/include/asm/irq.h b/arch/loongarch/include/asm/irq.h
index 48c0ce4..74fef60 100644
--- a/arch/loongarch/include/asm/irq.h
+++ b/arch/loongarch/include/asm/irq.h
@@ -108,8 +108,9 @@ int pch_lpc_acpi_init(struct irq_domain *parent,
 					struct acpi_madt_lpc_pic *acpi_pchlpc);
 struct irq_domain *pch_msi_acpi_init(struct irq_domain *parent,
 					struct acpi_madt_msi_pic *acpi_pchmsi);
-struct irq_domain *pch_pic_acpi_init(struct irq_domain *parent,
+int pch_pic_acpi_init(struct irq_domain *parent,
 					struct acpi_madt_bio_pic *acpi_pchpic);
+int find_pch_pic(u32 gsi);
 
 extern struct acpi_madt_lio_pic *acpi_liointc;
 extern struct acpi_madt_eio_pic *acpi_eiointc[MAX_IO_PICS];
@@ -123,7 +124,7 @@ struct irq_domain *pch_pic_acpi_init(struct irq_domain *parent,
 extern struct irq_domain *liointc_domain;
 extern struct fwnode_handle *pch_lpc_handle;
 extern struct irq_domain *pch_msi_domain[MAX_IO_PICS];
-extern struct irq_domain *pch_pic_domain[MAX_IO_PICS];
+extern struct fwnode_handle *pch_pic_handle[MAX_IO_PICS];
 
 extern irqreturn_t loongson3_ipi_interrupt(int irq, void *dev);
 
diff --git a/arch/loongarch/kernel/irq.c b/arch/loongarch/kernel/irq.c
index 07d6059..866b2ee 100644
--- a/arch/loongarch/kernel/irq.c
+++ b/arch/loongarch/kernel/irq.c
@@ -28,7 +28,6 @@
 struct irq_domain *cpu_domain;
 struct irq_domain *liointc_domain;
 struct irq_domain *pch_msi_domain[MAX_IO_PICS];
-struct irq_domain *pch_pic_domain[MAX_IO_PICS];
 
 /*
  * 'what should we do if we get a hw irq event on an illegal vector'.
diff --git a/arch/mips/include/asm/mach-loongson64/irq.h b/arch/mips/include/asm/mach-loongson64/irq.h
index 98ea977..55e0dee 100644
--- a/arch/mips/include/asm/mach-loongson64/irq.h
+++ b/arch/mips/include/asm/mach-loongson64/irq.h
@@ -7,7 +7,7 @@
 #define NR_MIPS_CPU_IRQS	8
 #define NR_MAX_CHAINED_IRQS	40 /* Chained IRQs means those not directly used by devices */
 #define NR_IRQS			(NR_IRQS_LEGACY + NR_MIPS_CPU_IRQS + NR_MAX_CHAINED_IRQS + 256)
-
+#define MAX_IO_PICS		1
 #define MIPS_CPU_IRQ_BASE 	NR_IRQS_LEGACY
 
 #include <asm/mach-generic/irq.h>
diff --git a/drivers/irqchip/irq-loongson-pch-pic.c b/drivers/irqchip/irq-loongson-pch-pic.c
index a4eb8a2..b6a73c8 100644
--- a/drivers/irqchip/irq-loongson-pch-pic.c
+++ b/drivers/irqchip/irq-loongson-pch-pic.c
@@ -33,13 +33,40 @@
 #define PIC_REG_IDX(irq_id)	((irq_id) / PIC_COUNT_PER_REG)
 #define PIC_REG_BIT(irq_id)	((irq_id) % PIC_COUNT_PER_REG)
 
+static int nr_pics;
+
 struct pch_pic {
 	void __iomem		*base;
 	struct irq_domain	*pic_domain;
 	u32			ht_vec_base;
 	raw_spinlock_t		pic_lock;
+	u32			vec_count;
+	u32			gsi_base;
 };
 
+static struct pch_pic *pch_pic_priv[MAX_IO_PICS];
+
+struct fwnode_handle *pch_pic_handle[MAX_IO_PICS];
+
+int find_pch_pic(u32 gsi)
+{
+	int i;
+
+	/* Find the PCH_PIC that manages this GSI. */
+	for (i = 0; i < MAX_IO_PICS; i++) {
+		struct pch_pic *priv = pch_pic_priv[i];
+
+		if (!priv)
+			return -1;
+
+		if (gsi >= priv->gsi_base && gsi < (priv->gsi_base + priv->vec_count))
+			return i;
+	}
+
+	pr_err("ERROR: Unable to locate PCH_PIC for GSI %d\n", gsi);
+	return -1;
+}
+
 static void pch_pic_bitset(struct pch_pic *priv, int offset, int bit)
 {
 	u32 reg;
@@ -139,6 +166,28 @@ static void pch_pic_ack_irq(struct irq_data *d)
 	.irq_set_type		= pch_pic_set_type,
 };
 
+static int pch_pic_domain_translate(struct irq_domain *d,
+					struct irq_fwspec *fwspec,
+					unsigned long *hwirq,
+					unsigned int *type)
+{
+	struct pch_pic *priv = d->host_data;
+	struct device_node *of_node = to_of_node(fwspec->fwnode);
+
+	if (fwspec->param_count < 1)
+		return -EINVAL;
+
+	if (of_node) {
+		*hwirq = fwspec->param[0] + priv->ht_vec_base;
+		*type = fwspec->param[1] & IRQ_TYPE_SENSE_MASK;
+	} else {
+		*hwirq = fwspec->param[0] - priv->gsi_base;
+		*type = IRQ_TYPE_NONE;
+	}
+
+	return 0;
+}
+
 static int pch_pic_alloc(struct irq_domain *domain, unsigned int virq,
 			      unsigned int nr_irqs, void *arg)
 {
@@ -149,13 +198,13 @@ static int pch_pic_alloc(struct irq_domain *domain, unsigned int virq,
 	struct irq_fwspec parent_fwspec;
 	struct pch_pic *priv = domain->host_data;
 
-	err = irq_domain_translate_twocell(domain, fwspec, &hwirq, &type);
+	err = pch_pic_domain_translate(domain, fwspec, &hwirq, &type);
 	if (err)
 		return err;
 
 	parent_fwspec.fwnode = domain->parent->fwnode;
 	parent_fwspec.param_count = 1;
-	parent_fwspec.param[0] = hwirq + priv->ht_vec_base;
+	parent_fwspec.param[0] = hwirq;
 
 	err = irq_domain_alloc_irqs_parent(domain, virq, 1, &parent_fwspec);
 	if (err)
@@ -170,7 +219,7 @@ static int pch_pic_alloc(struct irq_domain *domain, unsigned int virq,
 }
 
 static const struct irq_domain_ops pch_pic_domain_ops = {
-	.translate	= irq_domain_translate_twocell,
+	.translate	= pch_pic_domain_translate,
 	.alloc		= pch_pic_alloc,
 	.free		= irq_domain_free_irqs_parent,
 };
@@ -180,7 +229,7 @@ static void pch_pic_reset(struct pch_pic *priv)
 	int i;
 
 	for (i = 0; i < PIC_COUNT; i++) {
-		/* Write vectored ID */
+		/* Write vector ID */
 		writeb(priv->ht_vec_base + i, priv->base + PCH_INT_HTVEC(i));
 		/* Hardcode route to HT0 Lo */
 		writeb(1, priv->base + PCH_INT_ROUTE(i));
@@ -198,50 +247,37 @@ static void pch_pic_reset(struct pch_pic *priv)
 	}
 }
 
-static int pch_pic_of_init(struct device_node *node,
-				struct device_node *parent)
+static int pch_pic_init(phys_addr_t addr, unsigned long size, int vec_base,
+			struct irq_domain *parent_domain, struct fwnode_handle *domain_handle,
+			u32 gsi_base)
 {
 	struct pch_pic *priv;
-	struct irq_domain *parent_domain;
-	int err;
 
 	priv = kzalloc(sizeof(*priv), GFP_KERNEL);
 	if (!priv)
 		return -ENOMEM;
 
 	raw_spin_lock_init(&priv->pic_lock);
-	priv->base = of_iomap(node, 0);
-	if (!priv->base) {
-		err = -ENOMEM;
+	priv->base = ioremap(addr, size);
+	if (!priv->base)
 		goto free_priv;
-	}
-
-	parent_domain = irq_find_host(parent);
-	if (!parent_domain) {
-		pr_err("Failed to find the parent domain\n");
-		err = -ENXIO;
-		goto iounmap_base;
-	}
 
-	if (of_property_read_u32(node, "loongson,pic-base-vec",
-				&priv->ht_vec_base)) {
-		pr_err("Failed to determine pic-base-vec\n");
-		err = -EINVAL;
-		goto iounmap_base;
-	}
+	priv->ht_vec_base = vec_base;
+	priv->vec_count = ((readq(priv->base) >> 48) & 0xff) + 1;
+	priv->gsi_base = gsi_base;
 
 	priv->pic_domain = irq_domain_create_hierarchy(parent_domain, 0,
-						       PIC_COUNT,
-						       of_node_to_fwnode(node),
-						       &pch_pic_domain_ops,
-						       priv);
+						priv->vec_count, domain_handle,
+						&pch_pic_domain_ops, priv);
+
 	if (!priv->pic_domain) {
 		pr_err("Failed to create IRQ domain\n");
-		err = -ENOMEM;
 		goto iounmap_base;
 	}
 
 	pch_pic_reset(priv);
+	pch_pic_handle[nr_pics] = domain_handle;
+	pch_pic_priv[nr_pics++] = priv;
 
 	return 0;
 
@@ -250,7 +286,87 @@ static int pch_pic_of_init(struct device_node *node,
 free_priv:
 	kfree(priv);
 
-	return err;
+	return -EINVAL;
+}
+
+#ifdef CONFIG_OF
+
+static int pch_pic_of_init(struct device_node *node,
+				struct device_node *parent)
+{
+	int err, vec_base;
+	struct resource res;
+	struct irq_domain *parent_domain;
+
+	if (of_address_to_resource(node, 0, &res))
+		return -EINVAL;
+
+	parent_domain = irq_find_host(parent);
+	if (!parent_domain) {
+		pr_err("Failed to find the parent domain\n");
+		return -ENXIO;
+	}
+
+	if (of_property_read_u32(node, "loongson,pic-base-vec", &vec_base)) {
+		pr_err("Failed to determine pic-base-vec\n");
+		return -EINVAL;
+	}
+
+	err = pch_pic_init(res.start, resource_size(&res), vec_base,
+				parent_domain, of_node_to_fwnode(node), 0);
+	if (err < 0)
+		return err;
+
+	return 0;
 }
 
 IRQCHIP_DECLARE(pch_pic, "loongson,pch-pic-1.0", pch_pic_of_init);
+
+#endif
+
+#ifdef CONFIG_ACPI
+static int __init
+lpcintc_parse_madt(union acpi_subtable_headers *header,
+		       const unsigned long end)
+{
+	struct acpi_madt_lpc_pic *lpcintc_entry = (struct acpi_madt_lpc_pic *)header;
+
+	return pch_lpc_acpi_init(pch_pic_priv[0]->pic_domain, lpcintc_entry);
+}
+
+static int __init acpi_cascade_irqdomain_init(void)
+{
+	acpi_table_parse_madt(ACPI_MADT_TYPE_LPC_PIC,
+			      lpcintc_parse_madt, 0);
+	return 0;
+}
+
+int __init pch_pic_acpi_init(struct irq_domain *parent,
+					struct acpi_madt_bio_pic *acpi_pchpic)
+{
+	int ret, vec_base;
+	struct fwnode_handle *domain_handle;
+
+	if (!acpi_pchpic)
+		return -EINVAL;
+
+	vec_base = acpi_pchpic->gsi_base - GSI_MIN_PCH_IRQ;
+
+	domain_handle = irq_domain_alloc_fwnode((phys_addr_t *)acpi_pchpic);
+	if (!domain_handle) {
+		pr_err("Unable to allocate domain handle\n");
+		return -ENOMEM;
+	}
+
+	ret = pch_pic_init(acpi_pchpic->address, acpi_pchpic->size,
+				vec_base, parent, domain_handle, acpi_pchpic->gsi_base);
+
+	if (!ret) {
+		if (acpi_pchpic->id == 0)
+			acpi_cascade_irqdomain_init();
+	} else
+		irq_domain_free_fwnode(domain_handle);
+
+	return ret;
+}
+#endif
-- 
1.8.3.1

[PATCH V14 08/15] irqchip/loongson-pch-msi: Add ACPI init support

[Jianmin Lv]

From: Huacai Chen <chenhuacai@loongson.cn>

PCH-PIC/PCH-MSI stands for "Interrupt Controller" that described in
Section 5 of "Loongson 7A1000 Bridge User Manual". For more information
please refer Documentation/loongarch/irq-chip-model.rst.

Co-developed-by: Jianmin Lv <lvjianmin@loongson.cn>
Signed-off-by: Jianmin Lv <lvjianmin@loongson.cn>
Signed-off-by: Huacai Chen <chenhuacai@loongson.cn>
---
 arch/loongarch/include/asm/irq.h       |   4 +-
 arch/loongarch/kernel/irq.c            |   1 -
 drivers/irqchip/irq-loongson-pch-msi.c | 131 ++++++++++++++++++++++-----------
 3 files changed, 91 insertions(+), 45 deletions(-)

diff --git a/arch/loongarch/include/asm/irq.h b/arch/loongarch/include/asm/irq.h
index 74fef60..6022406 100644
--- a/arch/loongarch/include/asm/irq.h
+++ b/arch/loongarch/include/asm/irq.h
@@ -106,11 +106,12 @@ struct irq_domain *htvec_acpi_init(struct irq_domain *parent,
 					struct acpi_madt_ht_pic *acpi_htvec);
 int pch_lpc_acpi_init(struct irq_domain *parent,
 					struct acpi_madt_lpc_pic *acpi_pchlpc);
-struct irq_domain *pch_msi_acpi_init(struct irq_domain *parent,
+int pch_msi_acpi_init(struct irq_domain *parent,
 					struct acpi_madt_msi_pic *acpi_pchmsi);
 int pch_pic_acpi_init(struct irq_domain *parent,
 					struct acpi_madt_bio_pic *acpi_pchpic);
 int find_pch_pic(u32 gsi);
+struct fwnode_handle *get_pch_msi_handle(int pci_segment);
 
 extern struct acpi_madt_lio_pic *acpi_liointc;
 extern struct acpi_madt_eio_pic *acpi_eiointc[MAX_IO_PICS];
@@ -123,7 +124,6 @@ int pch_pic_acpi_init(struct irq_domain *parent,
 extern struct irq_domain *cpu_domain;
 extern struct irq_domain *liointc_domain;
 extern struct fwnode_handle *pch_lpc_handle;
-extern struct irq_domain *pch_msi_domain[MAX_IO_PICS];
 extern struct fwnode_handle *pch_pic_handle[MAX_IO_PICS];
 
 extern irqreturn_t loongson3_ipi_interrupt(int irq, void *dev);
diff --git a/arch/loongarch/kernel/irq.c b/arch/loongarch/kernel/irq.c
index 866b2ee..ce21281 100644
--- a/arch/loongarch/kernel/irq.c
+++ b/arch/loongarch/kernel/irq.c
@@ -27,7 +27,6 @@
 
 struct irq_domain *cpu_domain;
 struct irq_domain *liointc_domain;
-struct irq_domain *pch_msi_domain[MAX_IO_PICS];
 
 /*
  * 'what should we do if we get a hw irq event on an illegal vector'.
diff --git a/drivers/irqchip/irq-loongson-pch-msi.c b/drivers/irqchip/irq-loongson-pch-msi.c
index e3801c4..b3f1f8e 100644
--- a/drivers/irqchip/irq-loongson-pch-msi.c
+++ b/drivers/irqchip/irq-loongson-pch-msi.c
@@ -15,6 +15,8 @@
 #include <linux/pci.h>
 #include <linux/slab.h>
 
+static int nr_pics;
+
 struct pch_msi_data {
 	struct mutex	msi_map_lock;
 	phys_addr_t	doorbell;
@@ -23,6 +25,8 @@ struct pch_msi_data {
 	unsigned long	*msi_map;
 };
 
+static struct fwnode_handle *pch_msi_handle[MAX_IO_PICS];
+
 static void pch_msi_mask_msi_irq(struct irq_data *d)
 {
 	pci_msi_mask_irq(d);
@@ -154,12 +158,12 @@ static void pch_msi_middle_domain_free(struct irq_domain *domain,
 };
 
 static int pch_msi_init_domains(struct pch_msi_data *priv,
-				struct device_node *node,
-				struct irq_domain *parent)
+				struct irq_domain *parent,
+				struct fwnode_handle *domain_handle)
 {
 	struct irq_domain *middle_domain, *msi_domain;
 
-	middle_domain = irq_domain_create_linear(of_node_to_fwnode(node),
+	middle_domain = irq_domain_create_linear(domain_handle,
 						priv->num_irqs,
 						&pch_msi_middle_domain_ops,
 						priv);
@@ -171,7 +175,7 @@ static int pch_msi_init_domains(struct pch_msi_data *priv,
 	middle_domain->parent = parent;
 	irq_domain_update_bus_token(middle_domain, DOMAIN_BUS_NEXUS);
 
-	msi_domain = pci_msi_create_irq_domain(of_node_to_fwnode(node),
+	msi_domain = pci_msi_create_irq_domain(domain_handle,
 					       &pch_msi_domain_info,
 					       middle_domain);
 	if (!msi_domain) {
@@ -183,19 +187,11 @@ static int pch_msi_init_domains(struct pch_msi_data *priv,
 	return 0;
 }
 
-static int pch_msi_init(struct device_node *node,
-			    struct device_node *parent)
+static int pch_msi_init(phys_addr_t msg_address, int irq_base, int irq_count,
+			struct irq_domain *parent_domain, struct fwnode_handle *domain_handle)
 {
-	struct pch_msi_data *priv;
-	struct irq_domain *parent_domain;
-	struct resource res;
 	int ret;
-
-	parent_domain = irq_find_host(parent);
-	if (!parent_domain) {
-		pr_err("Failed to find the parent domain\n");
-		return -ENXIO;
-	}
+	struct pch_msi_data *priv;
 
 	priv = kzalloc(sizeof(*priv), GFP_KERNEL);
 	if (!priv)
@@ -203,48 +199,99 @@ static int pch_msi_init(struct device_node *node,
 
 	mutex_init(&priv->msi_map_lock);
 
-	ret = of_address_to_resource(node, 0, &res);
-	if (ret) {
-		pr_err("Failed to allocate resource\n");
-		goto err_priv;
-	}
-
-	priv->doorbell = res.start;
-
-	if (of_property_read_u32(node, "loongson,msi-base-vec",
-				&priv->irq_first)) {
-		pr_err("Unable to parse MSI vec base\n");
-		ret = -EINVAL;
-		goto err_priv;
-	}
-
-	if (of_property_read_u32(node, "loongson,msi-num-vecs",
-				&priv->num_irqs)) {
-		pr_err("Unable to parse MSI vec number\n");
-		ret = -EINVAL;
-		goto err_priv;
-	}
+	priv->doorbell = msg_address;
+	priv->irq_first = irq_base;
+	priv->num_irqs = irq_count;
 
 	priv->msi_map = bitmap_zalloc(priv->num_irqs, GFP_KERNEL);
-	if (!priv->msi_map) {
-		ret = -ENOMEM;
+	if (!priv->msi_map)
 		goto err_priv;
-	}
 
 	pr_debug("Registering %d MSIs, starting at %d\n",
 		 priv->num_irqs, priv->irq_first);
 
-	ret = pch_msi_init_domains(priv, node, parent_domain);
+	ret = pch_msi_init_domains(priv, parent_domain, domain_handle);
 	if (ret)
 		goto err_map;
 
+	pch_msi_handle[nr_pics++] = domain_handle;
 	return 0;
 
 err_map:
 	bitmap_free(priv->msi_map);
 err_priv:
 	kfree(priv);
-	return ret;
+
+	return -EINVAL;
+}
+
+#ifdef CONFIG_OF
+static int pch_msi_of_init(struct device_node *node, struct device_node *parent)
+{
+	int err;
+	int irq_base, irq_count;
+	struct resource res;
+	struct irq_domain *parent_domain;
+
+	parent_domain = irq_find_host(parent);
+	if (!parent_domain) {
+		pr_err("Failed to find the parent domain\n");
+		return -ENXIO;
+	}
+
+	if (of_address_to_resource(node, 0, &res)) {
+		pr_err("Failed to allocate resource\n");
+		return -EINVAL;
+	}
+
+	if (of_property_read_u32(node, "loongson,msi-base-vec", &irq_base)) {
+		pr_err("Unable to parse MSI vec base\n");
+		return -EINVAL;
+	}
+
+	if (of_property_read_u32(node, "loongson,msi-num-vecs", &irq_count)) {
+		pr_err("Unable to parse MSI vec number\n");
+		return -EINVAL;
+	}
+
+	err = pch_msi_init(res.start, irq_base, irq_count, parent_domain, of_node_to_fwnode(node));
+	if (err < 0)
+		return err;
+
+	return 0;
+}
+
+IRQCHIP_DECLARE(pch_msi, "loongson,pch-msi-1.0", pch_msi_of_init);
+#endif
+
+#ifdef CONFIG_ACPI
+struct fwnode_handle *get_pch_msi_handle(int pci_segment)
+{
+	int i;
+
+	for (i = 0; i < MAX_IO_PICS; i++) {
+		if (msi_group[i].pci_segment == pci_segment)
+			return pch_msi_handle[i];
+	}
+	return NULL;
 }
 
-IRQCHIP_DECLARE(pch_msi, "loongson,pch-msi-1.0", pch_msi_init);
+int __init pch_msi_acpi_init(struct irq_domain *parent,
+					struct acpi_madt_msi_pic *acpi_pchmsi)
+{
+	int ret;
+	struct fwnode_handle *domain_handle;
+
+	if (!acpi_pchmsi)
+		return -EINVAL;
+
+	domain_handle = irq_domain_alloc_fwnode((phys_addr_t *)acpi_pchmsi);
+
+	ret = pch_msi_init(acpi_pchmsi->msg_address, acpi_pchmsi->start,
+				acpi_pchmsi->count, parent, domain_handle);
+	if (ret < 0)
+		irq_domain_free_fwnode(domain_handle);
+
+	return ret;
+}
+#endif
-- 
1.8.3.1

[PATCH V14 09/15] irqchip/loongson-htvec: Add ACPI init support

[Jianmin Lv]

From: Huacai Chen <chenhuacai@loongson.cn>

HTVECINTC stands for "HyperTransport Interrupts" that described in
Section 14.3 of "Loongson 3A5000 Processor Reference Manual". For more
information please refer Documentation/loongarch/irq-chip-model.rst.

Co-developed-by: Jianmin Lv <lvjianmin@loongson.cn>
Signed-off-by: Jianmin Lv <lvjianmin@loongson.cn>
Signed-off-by: Huacai Chen <chenhuacai@loongson.cn>
---
 arch/loongarch/include/asm/irq.h     |   2 +-
 drivers/irqchip/irq-loongson-htvec.c | 145 +++++++++++++++++++++++++++--------
 2 files changed, 112 insertions(+), 35 deletions(-)

diff --git a/arch/loongarch/include/asm/irq.h b/arch/loongarch/include/asm/irq.h
index 6022406..8775dc6 100644
--- a/arch/loongarch/include/asm/irq.h
+++ b/arch/loongarch/include/asm/irq.h
@@ -102,7 +102,7 @@ struct irq_domain *liointc_acpi_init(struct irq_domain *parent,
 struct irq_domain *eiointc_acpi_init(struct irq_domain *parent,
 					struct acpi_madt_eio_pic *acpi_eiointc);
 
-struct irq_domain *htvec_acpi_init(struct irq_domain *parent,
+int htvec_acpi_init(struct irq_domain *parent,
 					struct acpi_madt_ht_pic *acpi_htvec);
 int pch_lpc_acpi_init(struct irq_domain *parent,
 					struct acpi_madt_lpc_pic *acpi_pchlpc);
diff --git a/drivers/irqchip/irq-loongson-htvec.c b/drivers/irqchip/irq-loongson-htvec.c
index 60a335d..65f4938 100644
--- a/drivers/irqchip/irq-loongson-htvec.c
+++ b/drivers/irqchip/irq-loongson-htvec.c
@@ -20,7 +20,6 @@
 /* Registers */
 #define HTVEC_EN_OFF		0x20
 #define HTVEC_MAX_PARENT_IRQ	8
-
 #define VEC_COUNT_PER_REG	32
 #define VEC_REG_IDX(irq_id)	((irq_id) / VEC_COUNT_PER_REG)
 #define VEC_REG_BIT(irq_id)	((irq_id) % VEC_COUNT_PER_REG)
@@ -32,6 +31,8 @@ struct htvec {
 	raw_spinlock_t		htvec_lock;
 };
 
+static struct htvec *htvec_priv;
+
 static void htvec_irq_dispatch(struct irq_desc *desc)
 {
 	int i;
@@ -155,64 +156,140 @@ static void htvec_reset(struct htvec *priv)
 	}
 }
 
-static int htvec_of_init(struct device_node *node,
-				struct device_node *parent)
+static int htvec_init(phys_addr_t addr, unsigned long size,
+		int num_parents, int parent_irq[], struct fwnode_handle *domain_handle)
 {
+	int i;
 	struct htvec *priv;
-	int err, parent_irq[8], i;
 
 	priv = kzalloc(sizeof(*priv), GFP_KERNEL);
 	if (!priv)
 		return -ENOMEM;
 
+	priv->num_parents = num_parents;
+	priv->base = ioremap(addr, size);
 	raw_spin_lock_init(&priv->htvec_lock);
-	priv->base = of_iomap(node, 0);
-	if (!priv->base) {
-		err = -ENOMEM;
-		goto free_priv;
-	}
-
-	/* Interrupt may come from any of the 8 interrupt lines */
-	for (i = 0; i < HTVEC_MAX_PARENT_IRQ; i++) {
-		parent_irq[i] = irq_of_parse_and_map(node, i);
-		if (parent_irq[i] <= 0)
-			break;
-
-		priv->num_parents++;
-	}
-
-	if (!priv->num_parents) {
-		pr_err("Failed to get parent irqs\n");
-		err = -ENODEV;
-		goto iounmap_base;
-	}
 
-	priv->htvec_domain = irq_domain_create_linear(of_node_to_fwnode(node),
+	/* Setup IRQ domain */
+	priv->htvec_domain = irq_domain_create_linear(domain_handle,
 					(VEC_COUNT_PER_REG * priv->num_parents),
 					&htvec_domain_ops, priv);
 	if (!priv->htvec_domain) {
-		pr_err("Failed to create IRQ domain\n");
-		err = -ENOMEM;
-		goto irq_dispose;
+		pr_err("loongson-htvec: cannot add IRQ domain\n");
+		goto iounmap_base;
 	}
 
 	htvec_reset(priv);
 
-	for (i = 0; i < priv->num_parents; i++)
+	for (i = 0; i < priv->num_parents; i++) {
 		irq_set_chained_handler_and_data(parent_irq[i],
 						 htvec_irq_dispatch, priv);
+	}
+
+	htvec_priv = priv;
 
 	return 0;
 
-irq_dispose:
-	for (; i > 0; i--)
-		irq_dispose_mapping(parent_irq[i - 1]);
 iounmap_base:
 	iounmap(priv->base);
-free_priv:
 	kfree(priv);
 
-	return err;
+	return -EINVAL;
+}
+
+#ifdef CONFIG_OF
+
+static int htvec_of_init(struct device_node *node,
+				struct device_node *parent)
+{
+	int i, err;
+	int parent_irq[8];
+	int num_parents = 0;
+	struct resource res;
+
+	if (of_address_to_resource(node, 0, &res))
+		return -EINVAL;
+
+	/* Interrupt may come from any of the 8 interrupt lines */
+	for (i = 0; i < HTVEC_MAX_PARENT_IRQ; i++) {
+		parent_irq[i] = irq_of_parse_and_map(node, i);
+		if (parent_irq[i] <= 0)
+			break;
+
+		num_parents++;
+	}
+
+	err = htvec_init(res.start, resource_size(&res),
+			num_parents, parent_irq, of_node_to_fwnode(node));
+	if (err < 0)
+		return err;
+
+	return 0;
 }
 
 IRQCHIP_DECLARE(htvec, "loongson,htvec-1.0", htvec_of_init);
+
+#endif
+
+#ifdef CONFIG_ACPI
+static int __init
+pch_pic_parse_madt(union acpi_subtable_headers *header,
+		       const unsigned long end)
+{
+	struct acpi_madt_bio_pic *pchpic_entry = (struct acpi_madt_bio_pic *)header;
+
+	return pch_pic_acpi_init(htvec_priv->htvec_domain, pchpic_entry);
+}
+
+static int __init
+pch_msi_parse_madt(union acpi_subtable_headers *header,
+		       const unsigned long end)
+{
+	struct acpi_madt_msi_pic *pchmsi_entry = (struct acpi_madt_msi_pic *)header;
+
+	return pch_msi_acpi_init(htvec_priv->htvec_domain, pchmsi_entry);
+}
+
+static int __init acpi_cascade_irqdomain_init(void)
+{
+	acpi_table_parse_madt(ACPI_MADT_TYPE_BIO_PIC,
+			      pch_pic_parse_madt, 0);
+	acpi_table_parse_madt(ACPI_MADT_TYPE_MSI_PIC,
+			      pch_msi_parse_madt, 0);
+	return 0;
+}
+
+int __init htvec_acpi_init(struct irq_domain *parent,
+				   struct acpi_madt_ht_pic *acpi_htvec)
+{
+	int i, ret;
+	int num_parents, parent_irq[8];
+	struct fwnode_handle *domain_handle;
+
+	if (!acpi_htvec)
+		return -EINVAL;
+
+	num_parents = HTVEC_MAX_PARENT_IRQ;
+
+	domain_handle = irq_domain_alloc_fwnode((phys_addr_t *)acpi_htvec);
+	if (!domain_handle) {
+		pr_err("Unable to allocate domain handle\n");
+		return -ENOMEM;
+	}
+
+	/* Interrupt may come from any of the 8 interrupt lines */
+	for (i = 0; i < HTVEC_MAX_PARENT_IRQ; i++)
+		parent_irq[i] = irq_create_mapping(parent, acpi_htvec->cascade[i]);
+
+	ret = htvec_init(acpi_htvec->address, acpi_htvec->size,
+			num_parents, parent_irq, domain_handle);
+
+	if (!ret)
+		acpi_cascade_irqdomain_init();
+	else
+		irq_domain_free_fwnode(domain_handle);
+
+	return ret;
+}
+
+#endif
-- 
1.8.3.1

[PATCH V14 10/15] irqchip/loongson-liointc: Add ACPI init support

[Jianmin Lv]

From: Huacai Chen <chenhuacai@loongson.cn>

LIOINTC stands for "Legacy I/O Interrupts" that described in Section
11.1 of "Loongson 3A5000 Processor Reference Manual". For more
information please refer Documentation/loongarch/irq-chip-model.rst.

Co-developed-by: Jianmin Lv <lvjianmin@loongson.cn>
Signed-off-by: Jianmin Lv <lvjianmin@loongson.cn>
Signed-off-by: Huacai Chen <chenhuacai@loongson.cn>
---
 arch/loongarch/include/asm/irq.h       |   4 +-
 arch/loongarch/kernel/irq.c            |   1 -
 drivers/irqchip/irq-loongson-liointc.c | 227 ++++++++++++++++++++++-----------
 3 files changed, 154 insertions(+), 78 deletions(-)

diff --git a/arch/loongarch/include/asm/irq.h b/arch/loongarch/include/asm/irq.h
index 8775dc6..b4c7956 100644
--- a/arch/loongarch/include/asm/irq.h
+++ b/arch/loongarch/include/asm/irq.h
@@ -97,7 +97,7 @@ static inline void eiointc_enable(void)
 
 struct irq_domain *loongarch_cpu_irq_init(void);
 
-struct irq_domain *liointc_acpi_init(struct irq_domain *parent,
+int liointc_acpi_init(struct irq_domain *parent,
 					struct acpi_madt_lio_pic *acpi_liointc);
 struct irq_domain *eiointc_acpi_init(struct irq_domain *parent,
 					struct acpi_madt_eio_pic *acpi_eiointc);
@@ -122,7 +122,7 @@ int pch_pic_acpi_init(struct irq_domain *parent,
 extern struct acpi_madt_bio_pic *acpi_pchpic[MAX_IO_PICS];
 
 extern struct irq_domain *cpu_domain;
-extern struct irq_domain *liointc_domain;
+extern struct fwnode_handle *liointc_handle;
 extern struct fwnode_handle *pch_lpc_handle;
 extern struct fwnode_handle *pch_pic_handle[MAX_IO_PICS];
 
diff --git a/arch/loongarch/kernel/irq.c b/arch/loongarch/kernel/irq.c
index ce21281..b04201c 100644
--- a/arch/loongarch/kernel/irq.c
+++ b/arch/loongarch/kernel/irq.c
@@ -26,7 +26,6 @@
 EXPORT_PER_CPU_SYMBOL(irq_stat);
 
 struct irq_domain *cpu_domain;
-struct irq_domain *liointc_domain;
 
 /*
  * 'what should we do if we get a hw irq event on an illegal vector'.
diff --git a/drivers/irqchip/irq-loongson-liointc.c b/drivers/irqchip/irq-loongson-liointc.c
index 8d05d8b..526ade4 100644
--- a/drivers/irqchip/irq-loongson-liointc.c
+++ b/drivers/irqchip/irq-loongson-liointc.c
@@ -23,7 +23,7 @@
 #endif
 
 #define LIOINTC_CHIP_IRQ	32
-#define LIOINTC_NUM_PARENT 4
+#define LIOINTC_NUM_PARENT	4
 #define LIOINTC_NUM_CORES	4
 
 #define LIOINTC_INTC_CHIP_START	0x20
@@ -58,6 +58,8 @@ struct liointc_priv {
 	bool				has_lpc_irq_errata;
 };
 
+struct fwnode_handle *liointc_handle;
+
 static void liointc_chained_handle_irq(struct irq_desc *desc)
 {
 	struct liointc_handler_data *handler = irq_desc_get_handler_data(desc);
@@ -153,97 +155,82 @@ static void liointc_resume(struct irq_chip_generic *gc)
 	irq_gc_unlock_irqrestore(gc, flags);
 }
 
-static const char * const parent_names[] = {"int0", "int1", "int2", "int3"};
-static const char * const core_reg_names[] = {"isr0", "isr1", "isr2", "isr3"};
+static int parent_irq[LIOINTC_NUM_PARENT];
+static u32 parent_int_map[LIOINTC_NUM_PARENT];
+static const char *const parent_names[] = {"int0", "int1", "int2", "int3"};
+static const char *const core_reg_names[] = {"isr0", "isr1", "isr2", "isr3"};
 
-static void __iomem *liointc_get_reg_byname(struct device_node *node,
-						const char *name)
+#ifdef CONFIG_ACPI
+static int liointc_domain_xlate(struct irq_domain *d, struct device_node *ctrlr,
+			     const u32 *intspec, unsigned int intsize,
+			     unsigned long *out_hwirq, unsigned int *out_type)
 {
-	int index = of_property_match_string(node, "reg-names", name);
-
-	if (index < 0)
-		return NULL;
-
-	return of_iomap(node, index);
+	if (WARN_ON(intsize < 1))
+		return -EINVAL;
+	*out_hwirq = intspec[0] - GSI_MIN_CPU_IRQ;
+	*out_type = IRQ_TYPE_NONE;
+	return 0;
 }
 
-static int __init liointc_of_init(struct device_node *node,
-				  struct device_node *parent)
+const struct irq_domain_ops acpi_irq_gc_ops = {
+	.map	= irq_map_generic_chip,
+	.unmap  = irq_unmap_generic_chip,
+	.xlate	= liointc_domain_xlate,
+};
+#endif
+
+static int liointc_init(phys_addr_t addr, unsigned long size, int revision,
+		struct fwnode_handle *domain_handle, struct device_node *node)
 {
+	int i, err;
+	void __iomem *base;
+	struct irq_chip_type *ct;
 	struct irq_chip_generic *gc;
 	struct irq_domain *domain;
-	struct irq_chip_type *ct;
 	struct liointc_priv *priv;
-	void __iomem *base;
-	u32 of_parent_int_map[LIOINTC_NUM_PARENT];
-	int parent_irq[LIOINTC_NUM_PARENT];
-	bool have_parent = FALSE;
-	int sz, i, err = 0;
 
 	priv = kzalloc(sizeof(*priv), GFP_KERNEL);
 	if (!priv)
 		return -ENOMEM;
 
-	if (of_device_is_compatible(node, "loongson,liointc-2.0")) {
-		base = liointc_get_reg_byname(node, "main");
-		if (!base) {
-			err = -ENODEV;
-			goto out_free_priv;
-		}
+	base = ioremap(addr, size);
+	if (!base)
+		goto out_free_priv;
 
-		for (i = 0; i < LIOINTC_NUM_CORES; i++)
-			priv->core_isr[i] = liointc_get_reg_byname(node, core_reg_names[i]);
-		if (!priv->core_isr[0]) {
-			err = -ENODEV;
-			goto out_iounmap_base;
-		}
-	} else {
-		base = of_iomap(node, 0);
-		if (!base) {
-			err = -ENODEV;
-			goto out_free_priv;
-		}
+	for (i = 0; i < LIOINTC_NUM_CORES; i++)
+		priv->core_isr[i] = base + LIOINTC_REG_INTC_STATUS;
 
-		for (i = 0; i < LIOINTC_NUM_CORES; i++)
-			priv->core_isr[i] = base + LIOINTC_REG_INTC_STATUS;
-	}
+	for (i = 0; i < LIOINTC_NUM_PARENT; i++)
+		priv->handler[i].parent_int_map = parent_int_map[i];
 
-	for (i = 0; i < LIOINTC_NUM_PARENT; i++) {
-		parent_irq[i] = of_irq_get_byname(node, parent_names[i]);
-		if (parent_irq[i] > 0)
-			have_parent = TRUE;
-	}
-	if (!have_parent) {
-		err = -ENODEV;
-		goto out_iounmap_isr;
-	}
+	if (revision > 1) {
+		for (i = 0; i < LIOINTC_NUM_CORES; i++) {
+			int index = of_property_match_string(node,
+					"reg-names", core_reg_names[i]);
 
-	sz = of_property_read_variable_u32_array(node,
-						"loongson,parent_int_map",
-						&of_parent_int_map[0],
-						LIOINTC_NUM_PARENT,
-						LIOINTC_NUM_PARENT);
-	if (sz < 4) {
-		pr_err("loongson-liointc: No parent_int_map\n");
-		err = -ENODEV;
-		goto out_iounmap_isr;
-	}
+			if (index < 0)
+				return -EINVAL;
 
-	for (i = 0; i < LIOINTC_NUM_PARENT; i++)
-		priv->handler[i].parent_int_map = of_parent_int_map[i];
+			priv->core_isr[i] = of_iomap(node, index);
+		}
+	}
 
 	/* Setup IRQ domain */
-	domain = irq_domain_add_linear(node, 32,
+#ifdef CONFIG_ACPI
+	domain = irq_domain_create_linear(domain_handle, LIOINTC_CHIP_IRQ,
+					&acpi_irq_gc_ops, priv);
+#else
+	domain = irq_domain_create_linear(domain_handle, LIOINTC_CHIP_IRQ,
 					&irq_generic_chip_ops, priv);
+#endif
 	if (!domain) {
 		pr_err("loongson-liointc: cannot add IRQ domain\n");
-		err = -EINVAL;
-		goto out_iounmap_isr;
+		goto out_iounmap;
 	}
 
-	err = irq_alloc_domain_generic_chips(domain, 32, 1,
-					node->full_name, handle_level_irq,
-					IRQ_NOPROBE, 0, 0);
+	err = irq_alloc_domain_generic_chips(domain, LIOINTC_CHIP_IRQ, 1,
+					(node ? node->full_name : "LIOINTC"),
+					handle_level_irq, 0, IRQ_NOPROBE, 0);
 	if (err) {
 		pr_err("loongson-liointc: unable to register IRQ domain\n");
 		goto out_free_domain;
@@ -299,24 +286,114 @@ static int __init liointc_of_init(struct device_node *node,
 				liointc_chained_handle_irq, &priv->handler[i]);
 	}
 
+	liointc_handle = domain_handle;
 	return 0;
 
 out_free_domain:
 	irq_domain_remove(domain);
-out_iounmap_isr:
-	for (i = 0; i < LIOINTC_NUM_CORES; i++) {
-		if (!priv->core_isr[i])
-			continue;
-		iounmap(priv->core_isr[i]);
-	}
-out_iounmap_base:
+out_iounmap:
 	iounmap(base);
 out_free_priv:
 	kfree(priv);
 
-	return err;
+	return -EINVAL;
+}
+
+#ifdef CONFIG_OF
+
+static int __init liointc_of_init(struct device_node *node,
+				  struct device_node *parent)
+{
+	bool have_parent = FALSE;
+	int sz, i, index, revision, err = 0;
+	struct resource res;
+
+	if (!of_device_is_compatible(node, "loongson,liointc-2.0")) {
+		index = 0;
+		revision = 1;
+	} else {
+		index = of_property_match_string(node, "reg-names", "main");
+		revision = 2;
+	}
+
+	if (of_address_to_resource(node, index, &res))
+		return -EINVAL;
+
+	for (i = 0; i < LIOINTC_NUM_PARENT; i++) {
+		parent_irq[i] = of_irq_get_byname(node, parent_names[i]);
+		if (parent_irq[i] > 0)
+			have_parent = TRUE;
+	}
+	if (!have_parent)
+		return -ENODEV;
+
+	sz = of_property_read_variable_u32_array(node,
+						"loongson,parent_int_map",
+						&parent_int_map[0],
+						LIOINTC_NUM_PARENT,
+						LIOINTC_NUM_PARENT);
+	if (sz < 4) {
+		pr_err("loongson-liointc: No parent_int_map\n");
+		return -ENODEV;
+	}
+
+	err = liointc_init(res.start, resource_size(&res),
+			revision, of_node_to_fwnode(node), node);
+	if (err < 0)
+		return err;
+
+	return 0;
 }
 
 IRQCHIP_DECLARE(loongson_liointc_1_0, "loongson,liointc-1.0", liointc_of_init);
 IRQCHIP_DECLARE(loongson_liointc_1_0a, "loongson,liointc-1.0a", liointc_of_init);
 IRQCHIP_DECLARE(loongson_liointc_2_0, "loongson,liointc-2.0", liointc_of_init);
+
+#endif
+
+#ifdef CONFIG_ACPI
+static int __init htintc_parse_madt(union acpi_subtable_headers *header,
+					const unsigned long end)
+{
+	struct acpi_madt_ht_pic *htintc_entry = (struct acpi_madt_ht_pic *)header;
+	struct irq_domain *parent = irq_find_matching_fwnode(liointc_handle, DOMAIN_BUS_ANY);
+
+	return htvec_acpi_init(parent, htintc_entry);
+}
+
+static int __init acpi_cascade_irqdomain_init(void)
+{
+	acpi_table_parse_madt(ACPI_MADT_TYPE_HT_PIC,
+			      htintc_parse_madt, 0);
+	return 0;
+}
+
+int __init liointc_acpi_init(struct irq_domain *parent, struct acpi_madt_lio_pic *acpi_liointc)
+{
+	int ret;
+	struct fwnode_handle *domain_handle;
+
+	if (!acpi_liointc)
+		return -EINVAL;
+
+	parent_int_map[0] = acpi_liointc->cascade_map[0];
+	parent_int_map[1] = acpi_liointc->cascade_map[1];
+
+	parent_irq[0] = irq_create_mapping(parent, acpi_liointc->cascade[0]);
+	parent_irq[1] = irq_create_mapping(parent, acpi_liointc->cascade[1]);
+
+	domain_handle = irq_domain_alloc_fwnode((phys_addr_t *)acpi_liointc);
+	if (!domain_handle) {
+		pr_err("Unable to allocate domain handle\n");
+		return -ENOMEM;
+	}
+	ret = liointc_init(acpi_liointc->address, acpi_liointc->size,
+			   1, domain_handle, NULL);
+	if (ret == 0)
+		acpi_cascade_irqdomain_init();
+	else
+		irq_domain_free_fwnode(domain_handle);
+
+	return ret;
+}
+#endif
-- 
1.8.3.1

[PATCH V14 11/15] LoongArch: prepare to support multiple pch-pic and pch-msi irqdomain

[Jianmin Lv]

For systems with two chipsets, there are two related pch-pic and
pch-msi irqdomains, each of which has the same node id as its
parent irqdomain. So we use a structure to mantain the relation
of node and it's parent irqdomain as pch irqdomin, the 'pci_segment'
field is only used to match the pci segment of a pci device when
setting msi irqdomain for the device.

struct acpi_vector_group {
        int node;
        int pci_segment;
        struct irq_domain *parent;
};

The field 'pci_segment' and 'node' are initialized from MCFG, and
the parent irqdomain driver will set field 'parent' by matching same
'node'.

Signed-off-by: Jianmin Lv <lvjianmin@loongson.cn>
---
 arch/loongarch/include/asm/irq.h |  8 ++++++++
 arch/loongarch/kernel/irq.c      | 38 ++++++++++++++++++++++++++++++++++++++
 2 files changed, 46 insertions(+)

diff --git a/arch/loongarch/include/asm/irq.h b/arch/loongarch/include/asm/irq.h
index b4c7956..a07315a 100644
--- a/arch/loongarch/include/asm/irq.h
+++ b/arch/loongarch/include/asm/irq.h
@@ -48,6 +48,14 @@ static inline bool on_irq_stack(int cpu, unsigned long sp)
 #define MAX_IO_PICS 2
 #define NR_IRQS	(64 + (256 * MAX_IO_PICS))
 
+struct acpi_vector_group {
+	int node;
+	int pci_segment;
+	struct irq_domain *parent;
+};
+extern struct acpi_vector_group pch_group[MAX_IO_PICS];
+extern struct acpi_vector_group msi_group[MAX_IO_PICS];
+
 #define CORES_PER_EIO_NODE	4
 
 #define LOONGSON_CPU_UART0_VEC		10 /* CPU UART0 */
diff --git a/arch/loongarch/kernel/irq.c b/arch/loongarch/kernel/irq.c
index b04201c..06f2a15 100644
--- a/arch/loongarch/kernel/irq.c
+++ b/arch/loongarch/kernel/irq.c
@@ -26,6 +26,8 @@
 EXPORT_PER_CPU_SYMBOL(irq_stat);
 
 struct irq_domain *cpu_domain;
+struct acpi_vector_group pch_group[MAX_IO_PICS];
+struct acpi_vector_group msi_group[MAX_IO_PICS];
 
 /*
  * 'what should we do if we get a hw irq event on an illegal vector'.
@@ -52,6 +54,41 @@ int arch_show_interrupts(struct seq_file *p, int prec)
 	return 0;
 }
 
+static int __init early_pci_mcfg_parse(struct acpi_table_header *header)
+{
+	struct acpi_table_mcfg *mcfg;
+	struct acpi_mcfg_allocation *mptr;
+	int i, n;
+
+	if (header->length < sizeof(struct acpi_table_mcfg))
+		return -EINVAL;
+
+	n = (header->length - sizeof(struct acpi_table_mcfg)) /
+					sizeof(struct acpi_mcfg_allocation);
+	mcfg = (struct acpi_table_mcfg *)header;
+	mptr = (struct acpi_mcfg_allocation *) &mcfg[1];
+
+	for (i = 0; i < n; i++, mptr++) {
+		msi_group[i].pci_segment = mptr->pci_segment;
+		pch_group[i].node = msi_group[i].node = (mptr->address >> 44) & 0xf;
+	}
+
+	return 0;
+}
+
+static void __init init_vec_parent_group(void)
+{
+	int i;
+
+	for (i = 0; i < MAX_IO_PICS; i++) {
+		msi_group[i].pci_segment = -1;
+		msi_group[i].node = -1;
+		pch_group[i].node = -1;
+	}
+
+	acpi_table_parse(ACPI_SIG_MCFG, early_pci_mcfg_parse);
+}
+
 void __init init_IRQ(void)
 {
 	int i;
@@ -65,6 +102,7 @@ void __init init_IRQ(void)
 	clear_csr_ecfg(ECFG0_IM);
 	clear_csr_estat(ESTATF_IP);
 
+	init_vec_parent_group();
 	irqchip_init();
 #ifdef CONFIG_SMP
 	ipi_irq = EXCCODE_IPI - EXCCODE_INT_START;
-- 
1.8.3.1

[PATCH V14 12/15] irqchip: Add Loongson Extended I/O interrupt controller support

[Jianmin Lv]

From: Huacai Chen <chenhuacai@loongson.cn>

EIOINTC stands for "Extended I/O Interrupts" that described in Section
11.2 of "Loongson 3A5000 Processor Reference Manual". For more
information please refer Documentation/loongarch/irq-chip-model.rst.

Loongson-3A5000 has 4 cores per NUMA node, and each NUMA node has an
EIOINTC; while Loongson-3C5000 has 16 cores per NUMA node, and each NUMA
node has 4 EIOINTCs. In other words, 16 cores of one NUMA node in
Loongson-3C5000 are organized in 4 groups, each group connects to an
EIOINTC. We call the "group" here as an EIOINTC node, so each EIOINTC
node always includes 4 cores (both in Loongson-3A5000 and Loongson-
3C5000).

Co-developed-by: Jianmin Lv <lvjianmin@loongson.cn>
Signed-off-by: Jianmin Lv <lvjianmin@loongson.cn>
Signed-off-by: Huacai Chen <chenhuacai@loongson.cn>
---
 arch/loongarch/include/asm/irq.h       |  11 +-
 drivers/irqchip/Kconfig                |  10 +
 drivers/irqchip/Makefile               |   1 +
 drivers/irqchip/irq-loongson-eiointc.c | 413 +++++++++++++++++++++++++++++++++
 include/linux/cpuhotplug.h             |   1 +
 5 files changed, 426 insertions(+), 10 deletions(-)
 create mode 100644 drivers/irqchip/irq-loongson-eiointc.c

diff --git a/arch/loongarch/include/asm/irq.h b/arch/loongarch/include/asm/irq.h
index a07315a..a826ac4 100644
--- a/arch/loongarch/include/asm/irq.h
+++ b/arch/loongarch/include/asm/irq.h
@@ -87,15 +87,6 @@ struct acpi_vector_group {
 extern int find_pch_pic(u32 gsi);
 extern int eiointc_get_node(int id);
 
-static inline void eiointc_enable(void)
-{
-	uint64_t misc;
-
-	misc = iocsr_read64(LOONGARCH_IOCSR_MISC_FUNC);
-	misc |= IOCSR_MISC_FUNC_EXT_IOI_EN;
-	iocsr_write64(misc, LOONGARCH_IOCSR_MISC_FUNC);
-}
-
 struct acpi_madt_lio_pic;
 struct acpi_madt_eio_pic;
 struct acpi_madt_ht_pic;
@@ -107,7 +98,7 @@ static inline void eiointc_enable(void)
 
 int liointc_acpi_init(struct irq_domain *parent,
 					struct acpi_madt_lio_pic *acpi_liointc);
-struct irq_domain *eiointc_acpi_init(struct irq_domain *parent,
+int eiointc_acpi_init(struct irq_domain *parent,
 					struct acpi_madt_eio_pic *acpi_eiointc);
 
 int htvec_acpi_init(struct irq_domain *parent,
diff --git a/drivers/irqchip/Kconfig b/drivers/irqchip/Kconfig
index c1d527f..e918579 100644
--- a/drivers/irqchip/Kconfig
+++ b/drivers/irqchip/Kconfig
@@ -555,6 +555,16 @@ config LOONGSON_LIOINTC
 	help
 	  Support for the Loongson Local I/O Interrupt Controller.
 
+config LOONGSON_EIOINTC
+	bool "Loongson Extend I/O Interrupt Controller"
+	depends on LOONGARCH
+	depends on MACH_LOONGSON64
+	default MACH_LOONGSON64
+	select IRQ_DOMAIN_HIERARCHY
+	select GENERIC_IRQ_CHIP
+	help
+	  Support for the Loongson3 Extend I/O Interrupt Vector Controller.
+
 config LOONGSON_HTPIC
 	bool "Loongson3 HyperTransport PIC Controller"
 	depends on MACH_LOONGSON64 && MIPS
diff --git a/drivers/irqchip/Makefile b/drivers/irqchip/Makefile
index 242b8b3..0cfd4f0 100644
--- a/drivers/irqchip/Makefile
+++ b/drivers/irqchip/Makefile
@@ -104,6 +104,7 @@ obj-$(CONFIG_TI_SCI_INTR_IRQCHIP)	+= irq-ti-sci-intr.o
 obj-$(CONFIG_TI_SCI_INTA_IRQCHIP)	+= irq-ti-sci-inta.o
 obj-$(CONFIG_TI_PRUSS_INTC)		+= irq-pruss-intc.o
 obj-$(CONFIG_LOONGSON_LIOINTC)		+= irq-loongson-liointc.o
+obj-$(CONFIG_LOONGSON_EIOINTC)		+= irq-loongson-eiointc.o
 obj-$(CONFIG_LOONGSON_HTPIC)		+= irq-loongson-htpic.o
 obj-$(CONFIG_LOONGSON_HTVEC)		+= irq-loongson-htvec.o
 obj-$(CONFIG_LOONGSON_PCH_PIC)		+= irq-loongson-pch-pic.o
diff --git a/drivers/irqchip/irq-loongson-eiointc.c b/drivers/irqchip/irq-loongson-eiointc.c
new file mode 100644
index 0000000..9ddb9ac
--- /dev/null
+++ b/drivers/irqchip/irq-loongson-eiointc.c
@@ -0,0 +1,413 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Loongson Extend I/O Interrupt Controller support
+ *
+ * Copyright (C) 2020-2022 Loongson Technology Corporation Limited
+ */
+
+#define pr_fmt(fmt) "eiointc: " fmt
+
+#include <linux/interrupt.h>
+#include <linux/irq.h>
+#include <linux/irqchip.h>
+#include <linux/irqdomain.h>
+#include <linux/irqchip/chained_irq.h>
+#include <linux/kernel.h>
+#include <linux/platform_device.h>
+#include <linux/of_address.h>
+#include <linux/of_irq.h>
+#include <linux/of_platform.h>
+
+#define EIOINTC_REG_NODEMAP	0x14a0
+#define EIOINTC_REG_IPMAP	0x14c0
+#define EIOINTC_REG_ENABLE	0x1600
+#define EIOINTC_REG_BOUNCE	0x1680
+#define EIOINTC_REG_ISR		0x1800
+#define EIOINTC_REG_ROUTE	0x1c00
+
+#define VEC_REG_COUNT		4
+#define VEC_COUNT_PER_REG	64
+#define VEC_COUNT		(VEC_REG_COUNT * VEC_COUNT_PER_REG)
+#define VEC_REG_IDX(irq_id)	((irq_id) / VEC_COUNT_PER_REG)
+#define VEC_REG_BIT(irq_id)     ((irq_id) % VEC_COUNT_PER_REG)
+#define EIOINTC_ALL_ENABLE	0xffffffff
+
+#define MAX_EIO_NODES		(NR_CPUS / CORES_PER_EIO_NODE)
+
+static int nr_pics;
+
+struct eiointc_priv {
+	u32			node;
+	nodemask_t		node_map;
+	cpumask_t		cpuspan_map;
+	struct fwnode_handle	*domain_handle;
+	struct irq_domain	*eiointc_domain;
+};
+
+static struct eiointc_priv *eiointc_priv[MAX_IO_PICS];
+
+static void eiointc_enable(void)
+{
+	uint64_t misc;
+
+	misc = iocsr_read64(LOONGARCH_IOCSR_MISC_FUNC);
+	misc |= IOCSR_MISC_FUNC_EXT_IOI_EN;
+	iocsr_write64(misc, LOONGARCH_IOCSR_MISC_FUNC);
+}
+
+static int cpu_to_eio_node(int cpu)
+{
+	return cpu_logical_map(cpu) / CORES_PER_EIO_NODE;
+}
+
+static void eiointc_set_irq_route(int pos, unsigned int cpu, unsigned int mnode, nodemask_t *node_map)
+{
+	int i, node, cpu_node, route_node;
+	unsigned char coremap[MAX_EIO_NODES];
+	uint32_t pos_off, data, data_byte, data_mask;
+
+	pos_off = pos & ~3;
+	data_byte = pos & 3;
+	data_mask = ~BIT_MASK(data_byte) & 0xf;
+
+	memset(coremap, 0, sizeof(unsigned char) * MAX_EIO_NODES);
+
+	/* Calculate node and coremap of target irq */
+	cpu_node = cpu_logical_map(cpu) / CORES_PER_EIO_NODE;
+	coremap[cpu_node] |= BIT(cpu_logical_map(cpu) % CORES_PER_EIO_NODE);
+
+	for_each_online_cpu(i) {
+		node = cpu_to_eio_node(i);
+		if (!node_isset(node, *node_map))
+			continue;
+
+		/* EIO node 0 is in charge of inter-node interrupt dispatch */
+		route_node = (node == mnode) ? cpu_node : node;
+		data = ((coremap[node] | (route_node << 4)) << (data_byte * 8));
+		csr_any_send(EIOINTC_REG_ROUTE + pos_off, data, data_mask, node * CORES_PER_EIO_NODE);
+	}
+}
+
+static DEFINE_RAW_SPINLOCK(affinity_lock);
+
+static int eiointc_set_irq_affinity(struct irq_data *d, const struct cpumask *affinity, bool force)
+{
+	unsigned int cpu;
+	unsigned long flags;
+	uint32_t vector, regaddr;
+	struct cpumask intersect_affinity;
+	struct eiointc_priv *priv = d->domain->host_data;
+
+	if (!IS_ENABLED(CONFIG_SMP))
+		return -EPERM;
+
+	raw_spin_lock_irqsave(&affinity_lock, flags);
+
+	cpumask_and(&intersect_affinity, affinity, cpu_online_mask);
+	cpumask_and(&intersect_affinity, &intersect_affinity, &priv->cpuspan_map);
+
+	if (cpumask_empty(&intersect_affinity)) {
+		raw_spin_unlock_irqrestore(&affinity_lock, flags);
+		return -EINVAL;
+	}
+	cpu = cpumask_first(&intersect_affinity);
+
+	if (!d->parent_data)
+		vector = d->hwirq;
+	else
+		vector = d->parent_data->hwirq;
+
+	regaddr = EIOINTC_REG_ENABLE + ((vector >> 5) << 2);
+
+	/* Mask target vector */
+	csr_any_send(regaddr, EIOINTC_ALL_ENABLE & (~BIT(vector & 0x1F)), 0x0, 0);
+	/* Set route for target vector */
+	eiointc_set_irq_route(vector, cpu, priv->node, &priv->node_map);
+	/* Unmask target vector */
+	csr_any_send(regaddr, EIOINTC_ALL_ENABLE, 0x0, 0);
+
+	irq_data_update_effective_affinity(d, cpumask_of(cpu));
+
+	raw_spin_unlock_irqrestore(&affinity_lock, flags);
+
+	return IRQ_SET_MASK_OK;
+}
+
+static int eiointc_index(int node)
+{
+	int i;
+
+	for (i = 0; i < nr_pics; i++) {
+		if (node_isset(node, eiointc_priv[i]->node_map))
+			return i;
+	}
+
+	return -1;
+}
+
+static int eiointc_router_init(unsigned int cpu)
+{
+	int i, bit;
+	uint32_t data;
+	uint32_t node = cpu_to_eio_node(cpu);
+	uint32_t index = eiointc_index(node);
+
+	if (index < 0) {
+		pr_err("Error: invalid nodemap!\n");
+		return -1;
+	}
+
+	if ((cpu_logical_map(cpu) % CORES_PER_EIO_NODE) == 0) {
+		eiointc_enable();
+
+		for (i = 0; i < VEC_COUNT / 32; i++) {
+			data = (((1 << (i * 2 + 1)) << 16) | (1 << (i * 2)));
+			iocsr_write32(data, EIOINTC_REG_NODEMAP + i * 4);
+		}
+
+		for (i = 0; i < VEC_COUNT / 32 / 4; i++) {
+			bit = BIT(1 + index); /* Route to IP[1 + index] */
+			data = bit | (bit << 8) | (bit << 16) | (bit << 24);
+			iocsr_write32(data, EIOINTC_REG_IPMAP + i * 4);
+		}
+
+		for (i = 0; i < VEC_COUNT / 4; i++) {
+			/* Route to Node-0 Core-0 */
+			if (index == 0)
+				bit = BIT(cpu_logical_map(0));
+			else
+				bit = (eiointc_priv[index]->node << 4) | 1;
+
+			data = bit | (bit << 8) | (bit << 16) | (bit << 24);
+			iocsr_write32(data, EIOINTC_REG_ROUTE + i * 4);
+		}
+
+		for (i = 0; i < VEC_COUNT / 32; i++) {
+			data = 0xffffffff;
+			iocsr_write32(data, EIOINTC_REG_ENABLE + i * 4);
+			iocsr_write32(data, EIOINTC_REG_BOUNCE + i * 4);
+		}
+	}
+
+	return 0;
+}
+
+static void eiointc_irq_dispatch(struct irq_desc *desc)
+{
+	int i;
+	u64 pending;
+	bool handled = false;
+	struct irq_chip *chip = irq_desc_get_chip(desc);
+	struct eiointc_priv *priv = irq_desc_get_handler_data(desc);
+
+	chained_irq_enter(chip, desc);
+
+	for (i = 0; i < VEC_REG_COUNT; i++) {
+		pending = iocsr_read64(EIOINTC_REG_ISR + (i << 3));
+		iocsr_write64(pending, EIOINTC_REG_ISR + (i << 3));
+		while (pending) {
+			int bit = __ffs(pending);
+			int irq = bit + VEC_COUNT_PER_REG * i;
+
+			generic_handle_domain_irq(priv->eiointc_domain, irq);
+			pending &= ~BIT(bit);
+			handled = true;
+		}
+	}
+
+	if (!handled)
+		spurious_interrupt();
+
+	chained_irq_exit(chip, desc);
+}
+
+static void eiointc_ack_irq(struct irq_data *d)
+{
+	if (d->parent_data)
+		irq_chip_ack_parent(d);
+}
+
+static void eiointc_mask_irq(struct irq_data *d)
+{
+	if (d->parent_data)
+		irq_chip_mask_parent(d);
+}
+
+static void eiointc_unmask_irq(struct irq_data *d)
+{
+	if (d->parent_data)
+		irq_chip_unmask_parent(d);
+}
+
+static struct irq_chip eiointc_irq_chip = {
+	.name			= "EIOINTC",
+	.irq_ack		= eiointc_ack_irq,
+	.irq_mask		= eiointc_mask_irq,
+	.irq_unmask		= eiointc_unmask_irq,
+	.irq_set_affinity	= eiointc_set_irq_affinity,
+};
+
+static int eiointc_domain_alloc(struct irq_domain *domain, unsigned int virq,
+				unsigned int nr_irqs, void *arg)
+{
+	int ret;
+	unsigned int i, type;
+	unsigned long hwirq = 0;
+	struct eiointc *priv = domain->host_data;
+
+	ret = irq_domain_translate_onecell(domain, arg, &hwirq, &type);
+	if (ret)
+		return ret;
+
+	for (i = 0; i < nr_irqs; i++) {
+		irq_domain_set_info(domain, virq + i, hwirq + i, &eiointc_irq_chip,
+					priv, handle_edge_irq, NULL, NULL);
+	}
+
+	return 0;
+}
+
+static void eiointc_domain_free(struct irq_domain *domain, unsigned int virq,
+				unsigned int nr_irqs)
+{
+	int i;
+
+	for (i = 0; i < nr_irqs; i++) {
+		struct irq_data *d = irq_domain_get_irq_data(domain, virq + i);
+
+		irq_set_handler(virq + i, NULL);
+		irq_domain_reset_irq_data(d);
+	}
+}
+
+static const struct irq_domain_ops eiointc_domain_ops = {
+	.translate	= irq_domain_translate_onecell,
+	.alloc		= eiointc_domain_alloc,
+	.free		= eiointc_domain_free,
+};
+
+static void acpi_set_vec_parent(int node, struct irq_domain *parent, struct acpi_vector_group *vec_group)
+{
+	int i;
+
+	if (cpu_has_flatmode)
+		node = cpu_to_node(node * CORES_PER_EIO_NODE);
+
+	for (i = 0; i < MAX_IO_PICS; i++) {
+		if (node == vec_group[i].node) {
+			vec_group[i].parent = parent;
+			return;
+		}
+	}
+}
+
+struct irq_domain *acpi_get_vec_parent(int node, struct acpi_vector_group *vec_group)
+{
+	int i;
+
+	for (i = 0; i < MAX_IO_PICS; i++) {
+		if (node == vec_group[i].node)
+			return vec_group[i].parent;
+	}
+	return NULL;
+}
+
+static int __init
+pch_pic_parse_madt(union acpi_subtable_headers *header,
+		       const unsigned long end)
+{
+	struct acpi_madt_bio_pic *pchpic_entry = (struct acpi_madt_bio_pic *)header;
+	unsigned int node = (pchpic_entry->address >> 44) & 0xf;
+	struct irq_domain *parent = acpi_get_vec_parent(node, pch_group);
+
+	if (parent)
+		return pch_pic_acpi_init(parent, pchpic_entry);
+
+	return -EINVAL;
+}
+
+static int __init
+pch_msi_parse_madt(union acpi_subtable_headers *header,
+		       const unsigned long end)
+{
+	struct acpi_madt_msi_pic *pchmsi_entry = (struct acpi_madt_msi_pic *)header;
+	struct irq_domain *parent = acpi_get_vec_parent(eiointc_priv[nr_pics - 1]->node, msi_group);
+
+	if (parent)
+		return pch_msi_acpi_init(parent, pchmsi_entry);
+
+	return -EINVAL;
+}
+
+static int __init acpi_cascade_irqdomain_init(void)
+{
+	acpi_table_parse_madt(ACPI_MADT_TYPE_BIO_PIC,
+			      pch_pic_parse_madt, 0);
+	acpi_table_parse_madt(ACPI_MADT_TYPE_MSI_PIC,
+			      pch_msi_parse_madt, 1);
+	return 0;
+}
+
+int __init eiointc_acpi_init(struct irq_domain *parent,
+				     struct acpi_madt_eio_pic *acpi_eiointc)
+{
+	int i, parent_irq;
+	unsigned long node_map;
+	struct eiointc_priv *priv;
+
+	if (!acpi_eiointc)
+		return -EINVAL;
+
+	priv = kzalloc(sizeof(*priv), GFP_KERNEL);
+	if (!priv)
+		return -ENOMEM;
+
+	priv->domain_handle = irq_domain_alloc_fwnode((phys_addr_t *)acpi_eiointc);
+	if (!priv->domain_handle) {
+		pr_err("Unable to allocate domain handle\n");
+		goto out_free_priv;
+	}
+
+	priv->node = acpi_eiointc->node;
+	node_map = acpi_eiointc->node_map ? : -1ULL;
+
+	for_each_possible_cpu(i) {
+		if (node_map & (1ULL << cpu_to_eio_node(i))) {
+			node_set(cpu_to_eio_node(i), priv->node_map);
+			cpumask_or(&priv->cpuspan_map, &priv->cpuspan_map, cpumask_of(i));
+		}
+	}
+
+	/* Setup IRQ domain */
+	priv->eiointc_domain = irq_domain_create_linear(priv->domain_handle, VEC_COUNT,
+					&eiointc_domain_ops, priv);
+	if (!priv->eiointc_domain) {
+		pr_err("loongson-eiointc: cannot add IRQ domain\n");
+		goto out_free_handle;
+	}
+
+	eiointc_priv[nr_pics++] = priv;
+
+	eiointc_router_init(0);
+
+	parent_irq = irq_create_mapping(parent, acpi_eiointc->cascade);
+	irq_set_chained_handler_and_data(parent_irq, eiointc_irq_dispatch, priv);
+
+	cpuhp_setup_state_nocalls(CPUHP_AP_IRQ_LOONGARCH_STARTING,
+				  "irqchip/loongarch/intc:starting",
+				  eiointc_router_init, NULL);
+
+	acpi_set_vec_parent(acpi_eiointc->node, priv->eiointc_domain, pch_group);
+	acpi_set_vec_parent(acpi_eiointc->node, priv->eiointc_domain, msi_group);
+	acpi_cascade_irqdomain_init();
+
+	return 0;
+
+out_free_handle:
+	irq_domain_free_fwnode(priv->domain_handle);
+	priv->domain_handle = NULL;
+out_free_priv:
+	kfree(priv);
+
+	return -ENOMEM;
+}
diff --git a/include/linux/cpuhotplug.h b/include/linux/cpuhotplug.h
index 19f0dbf..de662f3 100644
--- a/include/linux/cpuhotplug.h
+++ b/include/linux/cpuhotplug.h
@@ -151,6 +151,7 @@ enum cpuhp_state {
 	CPUHP_AP_IRQ_BCM2836_STARTING,
 	CPUHP_AP_IRQ_MIPS_GIC_STARTING,
 	CPUHP_AP_IRQ_RISCV_STARTING,
+	CPUHP_AP_IRQ_LOONGARCH_STARTING,
 	CPUHP_AP_IRQ_SIFIVE_PLIC_STARTING,
 	CPUHP_AP_ARM_MVEBU_COHERENCY,
 	CPUHP_AP_MICROCODE_LOADER,
-- 
1.8.3.1

[PATCH V14 13/15] irqchip: Add LoongArch CPU interrupt controller support

[Jianmin Lv]

From: Huacai Chen <chenhuacai@loongson.cn>

LoongArch CPUINTC stands for CSR.ECFG/CSR.ESTAT and related interrupt
controller that described in Section 7.4 of "LoongArch Reference Manual,
Vol 1". For more information please refer Documentation/loongarch/irq-
chip-model.rst.

LoongArch CPUINTC has 13 interrupt sources: SWI0~1, HWI0~7, IPI, TI
(Timer) and PCOV (PMC). IRQ mappings of HWI0~7 are configurable (can be
created from DT/ACPI), but IPI, TI (Timer) and PCOV (PMC) are hardcoded
bits, so we define get_xxx_irq() for them.

Co-developed-by: Jianmin Lv <lvjianmin@loongson.cn>
Signed-off-by: Jianmin Lv <lvjianmin@loongson.cn>
Signed-off-by: Huacai Chen <chenhuacai@loongson.cn>
---
 arch/loongarch/include/asm/irq.h    |   4 --
 arch/loongarch/kernel/irq.c         |   1 -
 drivers/irqchip/Kconfig             |  10 +++
 drivers/irqchip/Makefile            |   1 +
 drivers/irqchip/irq-loongarch-cpu.c | 135 ++++++++++++++++++++++++++++++++++++
 5 files changed, 146 insertions(+), 5 deletions(-)
 create mode 100644 drivers/irqchip/irq-loongarch-cpu.c

diff --git a/arch/loongarch/include/asm/irq.h b/arch/loongarch/include/asm/irq.h
index a826ac4..46bc9828 100644
--- a/arch/loongarch/include/asm/irq.h
+++ b/arch/loongarch/include/asm/irq.h
@@ -94,13 +94,10 @@ struct acpi_vector_group {
 struct acpi_madt_msi_pic;
 struct acpi_madt_lpc_pic;
 
-struct irq_domain *loongarch_cpu_irq_init(void);
-
 int liointc_acpi_init(struct irq_domain *parent,
 					struct acpi_madt_lio_pic *acpi_liointc);
 int eiointc_acpi_init(struct irq_domain *parent,
 					struct acpi_madt_eio_pic *acpi_eiointc);
-
 int htvec_acpi_init(struct irq_domain *parent,
 					struct acpi_madt_ht_pic *acpi_htvec);
 int pch_lpc_acpi_init(struct irq_domain *parent,
@@ -120,7 +117,6 @@ int pch_pic_acpi_init(struct irq_domain *parent,
 extern struct acpi_madt_msi_pic *acpi_pchmsi[MAX_IO_PICS];
 extern struct acpi_madt_bio_pic *acpi_pchpic[MAX_IO_PICS];
 
-extern struct irq_domain *cpu_domain;
 extern struct fwnode_handle *liointc_handle;
 extern struct fwnode_handle *pch_lpc_handle;
 extern struct fwnode_handle *pch_pic_handle[MAX_IO_PICS];
diff --git a/arch/loongarch/kernel/irq.c b/arch/loongarch/kernel/irq.c
index 06f2a15..7474a22 100644
--- a/arch/loongarch/kernel/irq.c
+++ b/arch/loongarch/kernel/irq.c
@@ -25,7 +25,6 @@
 DEFINE_PER_CPU_SHARED_ALIGNED(irq_cpustat_t, irq_stat);
 EXPORT_PER_CPU_SYMBOL(irq_stat);
 
-struct irq_domain *cpu_domain;
 struct acpi_vector_group pch_group[MAX_IO_PICS];
 struct acpi_vector_group msi_group[MAX_IO_PICS];
 
diff --git a/drivers/irqchip/Kconfig b/drivers/irqchip/Kconfig
index e918579..ebfa2cd 100644
--- a/drivers/irqchip/Kconfig
+++ b/drivers/irqchip/Kconfig
@@ -546,6 +546,16 @@ config EXYNOS_IRQ_COMBINER
 	  Say yes here to add support for the IRQ combiner devices embedded
 	  in Samsung Exynos chips.
 
+config IRQ_LOONGARCH_CPU
+	bool
+	select GENERIC_IRQ_CHIP
+	select IRQ_DOMAIN
+	select GENERIC_IRQ_EFFECTIVE_AFF_MASK
+	help
+	  Support for the LoongArch CPU Interrupt Controller. For details of
+	  irq chip hierarchy on LoongArch platforms please read the document
+	  Documentation/loongarch/irq-chip-model.rst.
+
 config LOONGSON_LIOINTC
 	bool "Loongson Local I/O Interrupt Controller"
 	depends on MACH_LOONGSON64
diff --git a/drivers/irqchip/Makefile b/drivers/irqchip/Makefile
index 0cfd4f0..e559007 100644
--- a/drivers/irqchip/Makefile
+++ b/drivers/irqchip/Makefile
@@ -103,6 +103,7 @@ obj-$(CONFIG_LS1X_IRQ)			+= irq-ls1x.o
 obj-$(CONFIG_TI_SCI_INTR_IRQCHIP)	+= irq-ti-sci-intr.o
 obj-$(CONFIG_TI_SCI_INTA_IRQCHIP)	+= irq-ti-sci-inta.o
 obj-$(CONFIG_TI_PRUSS_INTC)		+= irq-pruss-intc.o
+obj-$(CONFIG_IRQ_LOONGARCH_CPU)		+= irq-loongarch-cpu.o
 obj-$(CONFIG_LOONGSON_LIOINTC)		+= irq-loongson-liointc.o
 obj-$(CONFIG_LOONGSON_EIOINTC)		+= irq-loongson-eiointc.o
 obj-$(CONFIG_LOONGSON_HTPIC)		+= irq-loongson-htpic.o
diff --git a/drivers/irqchip/irq-loongarch-cpu.c b/drivers/irqchip/irq-loongarch-cpu.c
new file mode 100644
index 0000000..c2f7411
--- /dev/null
+++ b/drivers/irqchip/irq-loongarch-cpu.c
@@ -0,0 +1,135 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2020-2022 Loongson Technology Corporation Limited
+ */
+
+#include <linux/init.h>
+#include <linux/kernel.h>
+#include <linux/interrupt.h>
+#include <linux/irq.h>
+#include <linux/irqchip.h>
+#include <linux/irqdomain.h>
+
+#include <asm/loongarch.h>
+#include <asm/setup.h>
+
+static struct irq_domain *irq_domain;
+
+static void mask_loongarch_irq(struct irq_data *d)
+{
+	clear_csr_ecfg(ECFGF(d->hwirq));
+}
+
+static void unmask_loongarch_irq(struct irq_data *d)
+{
+	set_csr_ecfg(ECFGF(d->hwirq));
+}
+
+static struct irq_chip cpu_irq_controller = {
+	.name		= "CPUINTC",
+	.irq_mask	= mask_loongarch_irq,
+	.irq_unmask	= unmask_loongarch_irq,
+};
+
+static void handle_cpu_irq(struct pt_regs *regs)
+{
+	int hwirq;
+	unsigned int estat = read_csr_estat() & CSR_ESTAT_IS;
+
+	while ((hwirq = ffs(estat))) {
+		estat &= ~BIT(hwirq - 1);
+		generic_handle_domain_irq(irq_domain, hwirq - 1);
+	}
+}
+
+int get_ipi_irq(void)
+{
+	return irq_create_mapping(irq_domain, EXCCODE_IPI - EXCCODE_INT_START);
+}
+
+int get_pmc_irq(void)
+{
+	return irq_create_mapping(irq_domain, EXCCODE_PMC - EXCCODE_INT_START);
+}
+
+int get_timer_irq(void)
+{
+	return irq_create_mapping(irq_domain, EXCCODE_TIMER - EXCCODE_INT_START);
+}
+
+static int loongarch_cpu_intc_map(struct irq_domain *d, unsigned int irq,
+			     irq_hw_number_t hwirq)
+{
+	irq_set_noprobe(irq);
+	irq_set_chip_and_handler(irq, &cpu_irq_controller, handle_percpu_irq);
+
+	return 0;
+}
+
+static const struct irq_domain_ops loongarch_cpu_intc_irq_domain_ops = {
+	.map = loongarch_cpu_intc_map,
+	.xlate = irq_domain_xlate_onecell,
+};
+
+static int __init loongarch_cpu_irq_init(void)
+{
+	struct fwnode_handle *domain_handle;
+
+	/* Mask interrupts. */
+	clear_csr_ecfg(ECFG0_IM);
+	clear_csr_estat(ESTATF_IP);
+
+	domain_handle = irq_domain_alloc_fwnode(NULL);
+	irq_domain = irq_domain_create_linear(domain_handle, EXCCODE_INT_NUM,
+					&loongarch_cpu_intc_irq_domain_ops, NULL);
+
+	if (!irq_domain)
+		panic("Failed to add irqdomain for LoongArch CPU");
+
+	set_handle_irq(&handle_cpu_irq);
+
+	return 0;
+}
+
+static int __init
+liointc_parse_madt(union acpi_subtable_headers *header,
+		       const unsigned long end)
+{
+	struct acpi_madt_lio_pic *liointc_entry = (struct acpi_madt_lio_pic *)header;
+
+	return liointc_acpi_init(irq_domain, liointc_entry);
+}
+
+static int __init
+eiointc_parse_madt(union acpi_subtable_headers *header,
+		       const unsigned long end)
+{
+	struct acpi_madt_eio_pic *eiointc_entry = (struct acpi_madt_eio_pic *)header;
+
+	return eiointc_acpi_init(irq_domain, eiointc_entry);
+}
+
+static int __init acpi_cascade_irqdomain_init(void)
+{
+	acpi_table_parse_madt(ACPI_MADT_TYPE_LIO_PIC,
+			      liointc_parse_madt, 0);
+	acpi_table_parse_madt(ACPI_MADT_TYPE_EIO_PIC,
+			      eiointc_parse_madt, 0);
+	return 0;
+}
+
+static int __init coreintc_acpi_init_v1(union acpi_subtable_headers *header,
+				   const unsigned long end)
+{
+	if (irq_domain)
+		return 0;
+
+	loongarch_cpu_irq_init();
+	acpi_cascade_irqdomain_init();
+
+	return 0;
+}
+
+IRQCHIP_ACPI_DECLARE(coreintc_v1, ACPI_MADT_TYPE_CORE_PIC,
+		NULL, ACPI_MADT_CORE_PIC_VERSION_V1,
+		coreintc_acpi_init_v1);
-- 
1.8.3.1

[PATCH V14 14/15] irqchip / ACPI: Introduce ACPI_IRQ_MODEL_LPIC for LoongArch

[Jianmin Lv]

For LoongArch, ACPI_IRQ_MODEL_LPIC is introduced, and then the
callback acpi_get_gsi_domain_id and acpi_gsi_to_irq_fallback are
implemented.

The acpi_get_gsi_domain_id callback returns related fwnode handle
of irqdomain for different GSI range.

The acpi_gsi_to_irq_fallback will create new mapping for gsi when
the mapping of it is not found.

Signed-off-by: Jianmin Lv <lvjianmin@loongson.cn>
---
 drivers/acpi/bus.c                  |  3 +++
 drivers/irqchip/irq-loongarch-cpu.c | 37 +++++++++++++++++++++++++++++++++++++
 include/linux/acpi.h                |  1 +
 3 files changed, 41 insertions(+)

diff --git a/drivers/acpi/bus.c b/drivers/acpi/bus.c
index 86fa61a..63fbf00 100644
--- a/drivers/acpi/bus.c
+++ b/drivers/acpi/bus.c
@@ -1145,6 +1145,9 @@ static int __init acpi_bus_init_irq(void)
 	case ACPI_IRQ_MODEL_PLATFORM:
 		message = "platform specific model";
 		break;
+	case ACPI_IRQ_MODEL_LPIC:
+		message = "LPIC";
+		break;
 	default:
 		pr_info("Unknown interrupt routing model\n");
 		return -ENODEV;
diff --git a/drivers/irqchip/irq-loongarch-cpu.c b/drivers/irqchip/irq-loongarch-cpu.c
index c2f7411..1b241d7 100644
--- a/drivers/irqchip/irq-loongarch-cpu.c
+++ b/drivers/irqchip/irq-loongarch-cpu.c
@@ -15,6 +15,41 @@
 
 static struct irq_domain *irq_domain;
 
+static int lpic_gsi_to_irq(u32 gsi)
+{
+	/* Only pch irqdomain transferring is required for LoongArch. */
+	if (gsi >= GSI_MIN_PCH_IRQ && gsi <= GSI_MAX_PCH_IRQ)
+		return acpi_register_gsi(NULL, gsi, ACPI_LEVEL_SENSITIVE, ACPI_ACTIVE_HIGH);
+	return -1;
+}
+
+static struct fwnode_handle *lpic_get_gsi_domain_id(u32 gsi)
+{
+	int id;
+	struct fwnode_handle *domain_handle = NULL;
+
+	switch (gsi) {
+	case GSI_MIN_CPU_IRQ ... GSI_MAX_CPU_IRQ:
+		if (liointc_handle)
+			domain_handle = liointc_handle;
+		break;
+
+	case GSI_MIN_LPC_IRQ ... GSI_MAX_LPC_IRQ:
+		if (pch_lpc_handle)
+			domain_handle = pch_lpc_handle;
+		break;
+
+	case GSI_MIN_PCH_IRQ ... GSI_MAX_PCH_IRQ:
+		id = find_pch_pic(gsi);
+		if (id >= 0 && pch_pic_handle[id])
+			domain_handle = pch_pic_handle[id];
+
+		break;
+	}
+
+	return domain_handle;
+}
+
 static void mask_loongarch_irq(struct irq_data *d)
 {
 	clear_csr_ecfg(ECFGF(d->hwirq));
@@ -87,6 +122,8 @@ static int __init loongarch_cpu_irq_init(void)
 		panic("Failed to add irqdomain for LoongArch CPU");
 
 	set_handle_irq(&handle_cpu_irq);
+	acpi_set_irq_model(ACPI_IRQ_MODEL_LPIC, lpic_get_gsi_domain_id);
+	acpi_set_gsi_to_irq_fallback(lpic_gsi_to_irq);
 
 	return 0;
 }
diff --git a/include/linux/acpi.h b/include/linux/acpi.h
index 71d3719..1bec0a3 100644
--- a/include/linux/acpi.h
+++ b/include/linux/acpi.h
@@ -105,6 +105,7 @@ enum acpi_irq_model_id {
 	ACPI_IRQ_MODEL_IOSAPIC,
 	ACPI_IRQ_MODEL_PLATFORM,
 	ACPI_IRQ_MODEL_GIC,
+	ACPI_IRQ_MODEL_LPIC,
 	ACPI_IRQ_MODEL_COUNT
 };
 
-- 
1.8.3.1

[PATCH V14 15/15] LoongArch: Fix irq number for timer and ipi

[Jianmin Lv]

After supporting LoongArch CPUINTC controller driver, the
irq number of interrupt source from CPUINTC is needed to transfer
from CPUINTC irqdomain, so use api of CPUINTC to transfer it.

Signed-off-by: Jianmin Lv <lvjianmin@loongson.cn>
---
 arch/loongarch/kernel/irq.c  | 2 +-
 arch/loongarch/kernel/time.c | 2 +-
 2 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/arch/loongarch/kernel/irq.c b/arch/loongarch/kernel/irq.c
index 7474a22..8f06364 100644
--- a/arch/loongarch/kernel/irq.c
+++ b/arch/loongarch/kernel/irq.c
@@ -104,7 +104,7 @@ void __init init_IRQ(void)
 	init_vec_parent_group();
 	irqchip_init();
 #ifdef CONFIG_SMP
-	ipi_irq = EXCCODE_IPI - EXCCODE_INT_START;
+	ipi_irq = get_ipi_irq();
 	irq_set_percpu_devid(ipi_irq);
 	r = request_percpu_irq(ipi_irq, loongson3_ipi_interrupt, "IPI", &ipi_dummy_dev);
 	if (r < 0)
diff --git a/arch/loongarch/kernel/time.c b/arch/loongarch/kernel/time.c
index fe68238..4a04aa6 100644
--- a/arch/loongarch/kernel/time.c
+++ b/arch/loongarch/kernel/time.c
@@ -132,7 +132,7 @@ int constant_clockevent_init(void)
 	struct clock_event_device *cd;
 	static int timer_irq_installed = 0;
 
-	irq = EXCCODE_TIMER - EXCCODE_INT_START;
+	irq = get_timer_irq();
 
 	cd = &per_cpu(constant_clockevent_device, cpu);
 
-- 
1.8.3.1

Re: [PATCH V14 07/15] irqchip/loongson-pch-pic: Add ACPI init support

[kernel test robot]

Hi Jianmin,

I love your patch! Yet something to improve:

[auto build test ERROR on tip/irq/core]
[also build test ERROR on rafael-pm/linux-next linus/master v5.19-rc4 next-20220701]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch]

url:    https://github.com/intel-lab-lkp/linux/commits/Jianmin-Lv/irqchip-Add-LoongArch-related-irqchip-drivers/20220703-164922
base:   https://git.kernel.org/pub/scm/linux/kernel/git/tip/tip.git ac165aab469895de059a4a191a2e04ddb5421d0e
config: hexagon-buildonly-randconfig-r005-20220703 (https://download.01.org/0day-ci/archive/20220703/202207031820.EptpeQ5R-lkp@intel.com/config)
compiler: clang version 15.0.0 (https://github.com/llvm/llvm-project 5d787689b14574fe58ba9798563f4a6df6059fbf)
reproduce (this is a W=1 build):
        wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross
        chmod +x ~/bin/make.cross
        # https://github.com/intel-lab-lkp/linux/commit/3889e0bcc694bb0465b7cf65e2a722f3f74dd0b2
        git remote add linux-review https://github.com/intel-lab-lkp/linux
        git fetch --no-tags linux-review Jianmin-Lv/irqchip-Add-LoongArch-related-irqchip-drivers/20220703-164922
        git checkout 3889e0bcc694bb0465b7cf65e2a722f3f74dd0b2
        # save the config file
        mkdir build_dir && cp config build_dir/.config
        COMPILER_INSTALL_PATH=$HOME/0day COMPILER=clang make.cross W=1 O=build_dir ARCH=hexagon SHELL=/bin/bash drivers/irqchip/

If you fix the issue, kindly add following tag where applicable
Reported-by: kernel test robot <lkp@intel.com>

All error/warnings (new ones prefixed by >>):

>> drivers/irqchip/irq-loongson-pch-pic.c:47:37: error: use of undeclared identifier 'MAX_IO_PICS'
   static struct pch_pic *pch_pic_priv[MAX_IO_PICS];
                                       ^
   drivers/irqchip/irq-loongson-pch-pic.c:49:38: error: use of undeclared identifier 'MAX_IO_PICS'
   struct fwnode_handle *pch_pic_handle[MAX_IO_PICS];
                                        ^
   drivers/irqchip/irq-loongson-pch-pic.c:56:18: error: use of undeclared identifier 'MAX_IO_PICS'
           for (i = 0; i < MAX_IO_PICS; i++) {
                           ^
>> drivers/irqchip/irq-loongson-pch-pic.c:51:5: warning: no previous prototype for function 'find_pch_pic' [-Wmissing-prototypes]
   int find_pch_pic(u32 gsi)
       ^
   drivers/irqchip/irq-loongson-pch-pic.c:51:1: note: declare 'static' if the function is not intended to be used outside of this translation unit
   int find_pch_pic(u32 gsi)
   ^
   static 
>> drivers/irqchip/irq-loongson-pch-pic.c:266:22: error: call to undeclared function 'readq'; ISO C99 and later do not support implicit function declarations [-Wimplicit-function-declaration]
           priv->vec_count = ((readq(priv->base) >> 48) & 0xff) + 1;
                               ^
>> drivers/irqchip/irq-loongson-pch-pic.c:266:40: warning: shift count >= width of type [-Wshift-count-overflow]
           priv->vec_count = ((readq(priv->base) >> 48) & 0xff) + 1;
                                                 ^  ~~
   2 warnings and 4 errors generated.


vim +/MAX_IO_PICS +47 drivers/irqchip/irq-loongson-pch-pic.c

    46	
  > 47	static struct pch_pic *pch_pic_priv[MAX_IO_PICS];
    48	
    49	struct fwnode_handle *pch_pic_handle[MAX_IO_PICS];
    50	
  > 51	int find_pch_pic(u32 gsi)
    52	{
    53		int i;
    54	
    55		/* Find the PCH_PIC that manages this GSI. */
    56		for (i = 0; i < MAX_IO_PICS; i++) {
    57			struct pch_pic *priv = pch_pic_priv[i];
    58	
    59			if (!priv)
    60				return -1;
    61	
    62			if (gsi >= priv->gsi_base && gsi < (priv->gsi_base + priv->vec_count))
    63				return i;
    64		}
    65	
    66		pr_err("ERROR: Unable to locate PCH_PIC for GSI %d\n", gsi);
    67		return -1;
    68	}
    69	

-- 
0-DAY CI Kernel Test Service
https://01.org/lkp

Re: [PATCH V14 03/15] ACPI: irq: Allow acpi_gsi_to_irq() to have an arch-specific fallback

[Marc Zyngier]

On Sun, 03 Jul 2022 09:45:20 +0100,
Jianmin Lv <lvjianmin@loongson.cn> wrote:
> 
> From: Marc Zyngier <maz@kernel.org>
> 
> It appears that the generic version of acpi_gsi_to_irq() doesn't
> fallback to establishing a mapping if there is no pre-existing
> one while the x86 version does.
> 
> While arm64 seems unaffected by it, LoongArch is relying on the x86
> behaviour. In an effort to prevent new architectures from reinventing
> the proverbial wheel, provide an optional callback that the arch code
> can set to restore the x86 behaviour.
> 
> Hopefully we can eventually get rid of this in the future once
> the expected behaviour has been clarified.
> 
> Reported-by: Jianmin Lv <lvjianmin@loongson.cn>
> Signed-off-by: Marc Zyngier <maz@kernel.org>
> Signed-off-by: Jianmin Lv <lvjianmin@loongson.cn>

Same thing about this patch. It is your duty to collect the tags when
you repost a series.

Thanks,

	M.

-- 
Without deviation from the norm, progress is not possible.

Re: [PATCH V14 02/15] APCI: irq: Add support for multiple GSI domains

[Marc Zyngier]

On Sun, 03 Jul 2022 09:45:19 +0100,
Jianmin Lv <lvjianmin@loongson.cn> wrote:
> 
> From: Marc Zyngier <maz@kernel.org>
> 
> In an unfortunate departure from the ACPI spec, the LoongArch
> architecture split its GSI space across multiple interrupt
> controllers.
> 
> In order to be able to reuse the core code and prevent
> architectures from reinventing an already square wheel, offer
> the arch code the ability to register a dispatcher function
> that will return the domain fwnode for a given GSI.
> 
> The ARM GIC drivers are updated to support this (with a single
> domain, as intended).
> 
> Signed-off-by: Marc Zyngier <maz@kernel.org>
> Cc: Hanjun Guo <guohanjun@huawei.com>
> Cc: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
> Signed-off-by: Jianmin Lv <lvjianmin@loongson.cn>

This patch was reviewed and tested by Hanjun. Why aren't the tags
included here?

	M.

-- 
Without deviation from the norm, progress is not possible.

Re: [PATCH V14 01/15] ACPICA: MADT: Add LoongArch APICs support

[Marc Zyngier]

On Sun, 03 Jul 2022 09:45:18 +0100,
Jianmin Lv <lvjianmin@loongson.cn> wrote:
> 
> From: Huacai Chen <chenhuacai@loongson.cn>
> 
> LoongArch-specific interrupt controllers (similar to APIC) are added
> in the next revision of ACPI Specification (current revision is 6.4),
> which including CORE_PIC (CPUINTC), LIO_PIC (LIOINTC), EIO_PIC (EIOINTC),
> HT_PIC (HTVECINTC), BIO_PIC (PCHINTC), LPC_PIC (PCHLPC) and MSI_PIC
> (PCHMSI). This patch add their definition.
> 
> ACPI changes of LoongArch-specific interrupt controllers have already
> been approved in the ECRs, and will be public in the next revision of
> ACPI Specification.
> 
> Reference: https://mantis.uefi.org/mantis/view.php?id=2203
> Reference: https://mantis.uefi.org/mantis/view.php?id=2313

These links are pretty useless without an account on uefi.org (most
people don't have one, and I certainly don't). Is there a link to
something *public*?

Thanks,

	M.

-- 
Without deviation from the norm, progress is not possible.

Re: [PATCH V14 10/15] irqchip/loongson-liointc: Add ACPI init support

[Marc Zyngier]

On Sun, 03 Jul 2022 09:45:27 +0100,
Jianmin Lv <lvjianmin@loongson.cn> wrote:
> 
> From: Huacai Chen <chenhuacai@loongson.cn>
> 
> LIOINTC stands for "Legacy I/O Interrupts" that described in Section
> 11.1 of "Loongson 3A5000 Processor Reference Manual". For more
> information please refer Documentation/loongarch/irq-chip-model.rst.
> 
> Co-developed-by: Jianmin Lv <lvjianmin@loongson.cn>
> Signed-off-by: Jianmin Lv <lvjianmin@loongson.cn>
> Signed-off-by: Huacai Chen <chenhuacai@loongson.cn>
> ---
>  arch/loongarch/include/asm/irq.h       |   4 +-
>  arch/loongarch/kernel/irq.c            |   1 -
>  drivers/irqchip/irq-loongson-liointc.c | 227 ++++++++++++++++++++++-----------
>  3 files changed, 154 insertions(+), 78 deletions(-)
> 
> diff --git a/arch/loongarch/include/asm/irq.h b/arch/loongarch/include/asm/irq.h
> index 8775dc6..b4c7956 100644
> --- a/arch/loongarch/include/asm/irq.h
> +++ b/arch/loongarch/include/asm/irq.h
> @@ -97,7 +97,7 @@ static inline void eiointc_enable(void)
>  
>  struct irq_domain *loongarch_cpu_irq_init(void);
>  
> -struct irq_domain *liointc_acpi_init(struct irq_domain *parent,
> +int liointc_acpi_init(struct irq_domain *parent,
>  					struct acpi_madt_lio_pic *acpi_liointc);
>  struct irq_domain *eiointc_acpi_init(struct irq_domain *parent,
>  					struct acpi_madt_eio_pic *acpi_eiointc);
> @@ -122,7 +122,7 @@ int pch_pic_acpi_init(struct irq_domain *parent,
>  extern struct acpi_madt_bio_pic *acpi_pchpic[MAX_IO_PICS];
>  
>  extern struct irq_domain *cpu_domain;
> -extern struct irq_domain *liointc_domain;
> +extern struct fwnode_handle *liointc_handle;
>  extern struct fwnode_handle *pch_lpc_handle;
>  extern struct fwnode_handle *pch_pic_handle[MAX_IO_PICS];
>  
> diff --git a/arch/loongarch/kernel/irq.c b/arch/loongarch/kernel/irq.c
> index ce21281..b04201c 100644
> --- a/arch/loongarch/kernel/irq.c
> +++ b/arch/loongarch/kernel/irq.c
> @@ -26,7 +26,6 @@
>  EXPORT_PER_CPU_SYMBOL(irq_stat);
>  
>  struct irq_domain *cpu_domain;
> -struct irq_domain *liointc_domain;
>  
>  /*
>   * 'what should we do if we get a hw irq event on an illegal vector'.
> diff --git a/drivers/irqchip/irq-loongson-liointc.c b/drivers/irqchip/irq-loongson-liointc.c
> index 8d05d8b..526ade4 100644
> --- a/drivers/irqchip/irq-loongson-liointc.c
> +++ b/drivers/irqchip/irq-loongson-liointc.c
> @@ -23,7 +23,7 @@
>  #endif
>  
>  #define LIOINTC_CHIP_IRQ	32
> -#define LIOINTC_NUM_PARENT 4
> +#define LIOINTC_NUM_PARENT	4
>  #define LIOINTC_NUM_CORES	4
>  
>  #define LIOINTC_INTC_CHIP_START	0x20
> @@ -58,6 +58,8 @@ struct liointc_priv {
>  	bool				has_lpc_irq_errata;
>  };
>  
> +struct fwnode_handle *liointc_handle;
> +
>  static void liointc_chained_handle_irq(struct irq_desc *desc)
>  {
>  	struct liointc_handler_data *handler = irq_desc_get_handler_data(desc);
> @@ -153,97 +155,82 @@ static void liointc_resume(struct irq_chip_generic *gc)
>  	irq_gc_unlock_irqrestore(gc, flags);
>  }
>  
> -static const char * const parent_names[] = {"int0", "int1", "int2", "int3"};
> -static const char * const core_reg_names[] = {"isr0", "isr1", "isr2", "isr3"};
> +static int parent_irq[LIOINTC_NUM_PARENT];
> +static u32 parent_int_map[LIOINTC_NUM_PARENT];
> +static const char *const parent_names[] = {"int0", "int1", "int2", "int3"};
> +static const char *const core_reg_names[] = {"isr0", "isr1", "isr2", "isr3"};
>  
> -static void __iomem *liointc_get_reg_byname(struct device_node *node,
> -						const char *name)
> +#ifdef CONFIG_ACPI
> +static int liointc_domain_xlate(struct irq_domain *d, struct device_node *ctrlr,
> +			     const u32 *intspec, unsigned int intsize,
> +			     unsigned long *out_hwirq, unsigned int *out_type)
>  {
> -	int index = of_property_match_string(node, "reg-names", name);
> -
> -	if (index < 0)
> -		return NULL;
> -
> -	return of_iomap(node, index);
> +	if (WARN_ON(intsize < 1))
> +		return -EINVAL;
> +	*out_hwirq = intspec[0] - GSI_MIN_CPU_IRQ;
> +	*out_type = IRQ_TYPE_NONE;
> +	return 0;
>  }
>  
> -static int __init liointc_of_init(struct device_node *node,
> -				  struct device_node *parent)
> +const struct irq_domain_ops acpi_irq_gc_ops = {

This should be static.

> +	.map	= irq_map_generic_chip,
> +	.unmap  = irq_unmap_generic_chip,
> +	.xlate	= liointc_domain_xlate,
> +};
> +#endif
> +
> +static int liointc_init(phys_addr_t addr, unsigned long size, int revision,
> +		struct fwnode_handle *domain_handle, struct device_node *node)
>  {
> +	int i, err;
> +	void __iomem *base;
> +	struct irq_chip_type *ct;
>  	struct irq_chip_generic *gc;
>  	struct irq_domain *domain;
> -	struct irq_chip_type *ct;
>  	struct liointc_priv *priv;
> -	void __iomem *base;
> -	u32 of_parent_int_map[LIOINTC_NUM_PARENT];
> -	int parent_irq[LIOINTC_NUM_PARENT];
> -	bool have_parent = FALSE;
> -	int sz, i, err = 0;
>  
>  	priv = kzalloc(sizeof(*priv), GFP_KERNEL);
>  	if (!priv)
>  		return -ENOMEM;
>  
> -	if (of_device_is_compatible(node, "loongson,liointc-2.0")) {
> -		base = liointc_get_reg_byname(node, "main");
> -		if (!base) {
> -			err = -ENODEV;
> -			goto out_free_priv;
> -		}
> +	base = ioremap(addr, size);
> +	if (!base)
> +		goto out_free_priv;
>  
> -		for (i = 0; i < LIOINTC_NUM_CORES; i++)
> -			priv->core_isr[i] = liointc_get_reg_byname(node, core_reg_names[i]);
> -		if (!priv->core_isr[0]) {
> -			err = -ENODEV;
> -			goto out_iounmap_base;
> -		}
> -	} else {
> -		base = of_iomap(node, 0);
> -		if (!base) {
> -			err = -ENODEV;
> -			goto out_free_priv;
> -		}
> +	for (i = 0; i < LIOINTC_NUM_CORES; i++)
> +		priv->core_isr[i] = base + LIOINTC_REG_INTC_STATUS;
>  
> -		for (i = 0; i < LIOINTC_NUM_CORES; i++)
> -			priv->core_isr[i] = base + LIOINTC_REG_INTC_STATUS;
> -	}
> +	for (i = 0; i < LIOINTC_NUM_PARENT; i++)
> +		priv->handler[i].parent_int_map = parent_int_map[i];
>  
> -	for (i = 0; i < LIOINTC_NUM_PARENT; i++) {
> -		parent_irq[i] = of_irq_get_byname(node, parent_names[i]);
> -		if (parent_irq[i] > 0)
> -			have_parent = TRUE;
> -	}
> -	if (!have_parent) {
> -		err = -ENODEV;
> -		goto out_iounmap_isr;
> -	}
> +	if (revision > 1) {
> +		for (i = 0; i < LIOINTC_NUM_CORES; i++) {
> +			int index = of_property_match_string(node,
> +					"reg-names", core_reg_names[i]);
>  
> -	sz = of_property_read_variable_u32_array(node,
> -						"loongson,parent_int_map",
> -						&of_parent_int_map[0],
> -						LIOINTC_NUM_PARENT,
> -						LIOINTC_NUM_PARENT);
> -	if (sz < 4) {
> -		pr_err("loongson-liointc: No parent_int_map\n");
> -		err = -ENODEV;
> -		goto out_iounmap_isr;
> -	}
> +			if (index < 0)
> +				return -EINVAL;
>  
> -	for (i = 0; i < LIOINTC_NUM_PARENT; i++)
> -		priv->handler[i].parent_int_map = of_parent_int_map[i];
> +			priv->core_isr[i] = of_iomap(node, index);
> +		}
> +	}
>  
>  	/* Setup IRQ domain */
> -	domain = irq_domain_add_linear(node, 32,
> +#ifdef CONFIG_ACPI
> +	domain = irq_domain_create_linear(domain_handle, LIOINTC_CHIP_IRQ,
> +					&acpi_irq_gc_ops, priv);
> +#else
> +	domain = irq_domain_create_linear(domain_handle, LIOINTC_CHIP_IRQ,
>  					&irq_generic_chip_ops, priv);
> +#endif

This feels wrong. The ACPI vs OF decision should be a runtime
one. Maybe you don't have that issue yet because MIPS is only OF and
LoongArch only ACPI, but it remains that this should be done
dynamically.

Please try to rewrite it as:

	if (!acpi_disabled)
		[... ACPI stuff ...]
	else
		[... OF stuff ...]

This should apply to all other cases where you have similar distinctions.

Thanks,

	M.

-- 
Without deviation from the norm, progress is not possible.

Re: [PATCH V14 00/15] irqchip: Add LoongArch-related irqchip drivers

[Hu Zeyuan]

Hi,Jianmin,
Could you CC the kernel mailing list of loongarch[1] when you submitting 
patches for LoongArch?

[1]loongarch@lists.linux.dev

Thanks!

在 2022/7/3 16:45, Jianmin Lv 写道:
> LoongArch is a new RISC ISA, which is a bit like MIPS or RISC-V.
> LoongArch includes a reduced 32-bit version (LA32R), a standard 32-bit
> version (LA32S) and a 64-bit version (LA64). LoongArch use ACPI as its
> boot protocol LoongArch-specific interrupt controllers (similar to APIC)
> are already added in the ACPI Specification 6.5(which may be published in
> early June this year and the board is reviewing the draft).
> 
> Currently, LoongArch based processors (e.g. Loongson-3A5000) can only
> work together with LS7A chipsets. The irq chips in LoongArch computers
> include CPUINTC (CPU Core Interrupt Controller), LIOINTC (Legacy I/O
> Interrupt Controller), EIOINTC (Extended I/O Interrupt Controller),
> HTVECINTC (Hyper-Transport Vector Interrupt Controller), PCH-PIC (Main
> Interrupt Controller in LS7A chipset), PCH-LPC (LPC Interrupt Controller
> in LS7A chipset) and PCH-MSI (MSI Interrupt Controller).
> 
> CPUINTC is a per-core controller (in CPU), LIOINTC/EIOINTC/HTVECINTC are
> per-package controllers (in CPU), while PCH-PIC/PCH-LPC/PCH-MSI are all
> controllers out of CPU (i.e., in chipsets). These controllers (in other
> words, irqchips) are linked in a hierarchy, and there are two models of
> hierarchy (legacy model and extended model).
> 
> Legacy IRQ model:
> 
> In this model, the IPI (Inter-Processor Interrupt) and CPU Local Timer
> interrupt go to CPUINTC directly, CPU UARTS interrupts go to LIOINTC,
> while all other devices interrupts go to PCH-PIC/PCH-LPC/PCH-MSI and
> gathered by HTVECINTC, and then go to LIOINTC, and then CPUINTC.
> 
>   +---------------------------------------------+
>   |                                             |
>   |    +-----+     +---------+     +-------+    |
>   |    | IPI | --> | CPUINTC | <-- | Timer |    |
>   |    +-----+     +---------+     +-------+    |
>   |                     ^                       |
>   |                     |                       |
>   |                +---------+     +-------+    |
>   |                | LIOINTC | <-- | UARTs |    |
>   |                +---------+     +-------+    |
>   |                     ^                       |
>   |                     |                       |
>   |               +-----------+                 |
>   |               | HTVECINTC |                 |
>   |               +-----------+                 |
>   |                ^         ^                  |
>   |                |         |                  |
>   |          +---------+ +---------+            |
>   |          | PCH-PIC | | PCH-MSI |            |
>   |          +---------+ +---------+            |
>   |            ^     ^           ^              |
>   |            |     |           |              |
>   |    +---------+ +---------+ +---------+      |
>   |    | PCH-LPC | | Devices | | Devices |      |
>   |    +---------+ +---------+ +---------+      |
>   |         ^                                   |
>   |         |                                   |
>   |    +---------+                              |
>   |    | Devices |                              |
>   |    +---------+                              |
>   |                                             |
>   |                                             |
>   +---------------------------------------------+
> 
> Extended IRQ model:
> 
> In this model, the IPI (Inter-Processor Interrupt) and CPU Local Timer
> interrupt go to CPUINTC directly, CPU UARTS interrupts go to LIOINTC,
> while all other devices interrupts go to PCH-PIC/PCH-LPC/PCH-MSI and
> gathered by EIOINTC, and then go to to CPUINTC directly.
> 
>   +--------------------------------------------------------+
>   |                                                        |
>   |         +-----+     +---------+     +-------+          |
>   |         | IPI | --> | CPUINTC | <-- | Timer |          |
>   |         +-----+     +---------+     +-------+          |
>   |                      ^       ^                         |
>   |                      |       |                         |
>   |               +---------+ +---------+     +-------+    |
>   |               | EIOINTC | | LIOINTC | <-- | UARTs |    |
>   |               +---------+ +---------+     +-------+    |
>   |                ^       ^                               |
>   |                |       |                               |
>   |         +---------+ +---------+                        |
>   |         | PCH-PIC | | PCH-MSI |                        |
>   |         +---------+ +---------+                        |
>   |           ^     ^           ^                          |
>   |           |     |           |                          |
>   |   +---------+ +---------+ +---------+                  |
>   |   | PCH-LPC | | Devices | | Devices |                  |
>   |   +---------+ +---------+ +---------+                  |
>   |        ^                                               |
>   |        |                                               |
>   |   +---------+                                          |
>   |   | Devices |                                          |
>   |   +---------+                                          |
>   |                                                        |
>   |                                                        |
>   +--------------------------------------------------------+
> 
> The hierarchy model is constructed by parsing irq contronler structures
> in MADT. Some controllers((e.g. LIOINTC, HTVECINTC, EIOINTC and PCH-LPC)
> are hardcodingly connected to their parents, so their irqdomins are
> separately routed to their parents in a fixed way. Some controllers
> (e.g. PCH-PIC and PCH-MSI) could be routed to different parents for different
> CPU. The firmware will config EIOINTC for the newer CPU and config HTVECINTC
> for old CPU in MADT. By this way, PCH-PIC and PCH-MSI irqdomain can only be
> routed one parent irqdomin: HTVECINTC or EIOINTC.
> 
> 
> Example of irqchip topology in a system with  two chipsets:
> 
>   +------------------------------------------------------------+
>   |                                                            |
>   |                     +------------------+                   |
>   |                     |      CPUINTC     |                   |
>   |                     +------------------+                   |
>   |                     ^                  ^                   |
>   |                     |                  |                   |
>   |          +----------+                  +----------+        |
>   |          | EIOINTC 0|                  | EIOINTC 1|        |
>   |          +----------+                  +----------+        |
>   |          ^          ^                  ^          ^        |
>   |          |          |                  |          |        |
>   | +----------+   +----------+   +----------+    +----------+ |
>   | | PCH-PIC 0|   | PCH-MSI 0|   | PCH-PIC 1|    | PCH-MSI 1| |
>   | +----------+   +----------+   +----------+    +----------+ |
>   |                                                            |
>   |                                                            |
>   +------------------------------------------------------------+
> 
> For systems with two chipsets, there are tow group(consists of EIOINTC, PCH-PIC and PCH-MSI) irqdomains,
> and each group has same node id. So we defined a structure to mantain the relation of node and it's parent irqdomain.
> 
> struct acpi_vector_group {
>          int node;
> 	int pci_segment;
>          struct irq_domain *parent;
> };
> 
> The initialization and use of acpi_vector_group array are following:
> 
> 1 Entry of struct acpi_vector_group array initialization:
> 
> By parsing MCFG, the node id（from bit44-47 of Base Address）and pci segment are extracted. And from MADT, we have the node id of each EIOINTC.
> 
> entry.node = node id of pci segment
> entry.pci_segment = pci segment (only for msi irqdomain)
> 
> By matching node id of entry and EIOINTC to set parent.
> 
> entry.parent = EIOINTC irqdomain(node id of EIOINTC == node id of pci segment)
> 
> 2 Get parent irqdomain for PCH-PIC:
> 
>>From MADT, we have the node id of each PCH-PIC(from bit44-47 of Base Address).
> if (node of entry i == node of PCH-PIC)
> 	return entrys[i].parent;
> 
> 3 Get parent irqdomain for PCH-MSI of pci segment:
> 
> 	return entrys[i].parent; (i is the index of msi irqdomain)
> 
> 4 How to select a correct irqdomain to map irq for a device?
> For devices using legacy irq behind PCH-PIC, GSI is used to select correct PCH-PIC irqdomain.
> For devices using msi irq behind PCH-MSI, the pci segmen of the device is used to select correct PCH-MSI irqdomain.
> 
> V1 -> V2:
> 1, Remove queued patches;
> 2, Move common logic of DT/ACPI probing to common functions;
> 3, Split .suspend()/.resume() functions to separate patches.
> 
> V2 -> V3:
> 1, Fix a bug for loongson-pch-pic probe;
> 2, Some minor improvements for LPC controller.
> 
> V3 -> V4:
> 1, Rework the CPU interrupt controller driver;
> 2, Some minor improvements for other controllers.
> 
> V4 -> V5:
> 1, Add a description of LoonArch's IRQ model;
> 2, Support multiple EIOINTCs in one system;
> 3, Some minor improvements for other controllers.
> 
> V5 -> V6:
> 1, Attach a fwnode to CPUINTC irq domain;
> 2, Use raw spinlock instead of generic spinlock;
> 3, Improve the method of restoring EIOINTC state;
> 4, Update documentation, comments and commit messages.
> 
> V6 -> V7:
> 1, Fix build warnings reported by kernel test robot.
> 
> V7 -> V8:
> 1, Add arguments sanity checking for irqchip init functions;
> 2, Support Loongson-3C5000 (One NUMA Node includes 4 EIOINTC Node).
> 
> V8 -> V9:
> 1, Rebase on 5.17-rc5;
> 2, Update cover letter;
> 3, Some small improvements.
> 
> V9 -> V10:
> 1, Rebase on 5.17-rc6;
> 2, Fix build warnings reported by kernel test robot.
> 
> V10 -> V11:
> 1, Rebase on 5.18-rc4;
> 2, Fix irq affinity setting for EIOINTC;
> 3, Fix hwirq allocation failure for EIOINTC.
> 
> V11 -> RFC:
> 1, Refactored the way to build irqchip hierarchy topology.
> 
> RFC -> RFC V2:
> 1, Move all IO-interrupt related code to driver/irqchip from arch directory.
> 2. Add description for an example of two chipsets system.
> 
> RFC V2 -> RFC V3:
> 1, Add support for multiple GSI domains
> 2, Use ACPI_GENERIC_GSI for GSI handling
> 3, Drop suspend-resume stuff
> 4, Export fwnode handles instead of irq domain handles
> 
> RFC V3 -> V12:
> 1, Address patch attributions of the patch series
> 
> V12 -> V13
> 1 Based on 5.19-rc2
> 2 Remove arch specified gsi code
> 3 Split some 'common' code into the various drivers where they belong.
> 4 Allow acpi_gsi_to_irq() to have an arch-specific fallback
> 
> V13 -> V14
> 1 Add LoongArch-specified APICs definition
> 2 Use the way in CPUINTC driver to call pch-pic and pch-msi entry
> 3 Fix compiling and regression issue for OF path
> 
> Huacai Chen (8):
>    ACPICA: MADT: Add LoongArch APICs support
>    irqchip: Add Loongson PCH LPC controller support
>    irqchip/loongson-pch-pic: Add ACPI init support
>    irqchip/loongson-pch-msi: Add ACPI init support
>    irqchip/loongson-htvec: Add ACPI init support
>    irqchip/loongson-liointc: Add ACPI init support
>    irqchip: Add Loongson Extended I/O interrupt controller support
>    irqchip: Add LoongArch CPU interrupt controller support
> 
> Jianmin Lv (5):
>    genirq/generic_chip: export irq_unmap_generic_chip
>    LoongArch: Use ACPI_GENERIC_GSI for gsi handling
>    LoongArch: prepare to support multiple pch-pic and pch-msi irqdomain
>    irqchip / ACPI: Introduce ACPI_IRQ_MODEL_LPIC for LoongArch
>    LoongArch: Fix irq number for timer and ipi
> 
> Marc Zyngier (2):
>    APCI: irq: Add support for multiple GSI domains
>    ACPI: irq: Allow acpi_gsi_to_irq() to have an arch-specific fallback
> 
>   arch/loongarch/Kconfig                      |   1 +
>   arch/loongarch/include/asm/irq.h            |  42 ++-
>   arch/loongarch/kernel/acpi.c                |  65 -----
>   arch/loongarch/kernel/irq.c                 |  45 ++-
>   arch/loongarch/kernel/time.c                |   2 +-
>   arch/mips/include/asm/mach-loongson64/irq.h |   2 +-
>   drivers/acpi/bus.c                          |   3 +
>   drivers/acpi/irq.c                          |  58 ++--
>   drivers/irqchip/Kconfig                     |  28 ++
>   drivers/irqchip/Makefile                    |   3 +
>   drivers/irqchip/irq-gic-v3.c                |  18 +-
>   drivers/irqchip/irq-gic.c                   |  18 +-
>   drivers/irqchip/irq-loongarch-cpu.c         | 169 ++++++++++++
>   drivers/irqchip/irq-loongson-eiointc.c      | 413 ++++++++++++++++++++++++++++
>   drivers/irqchip/irq-loongson-htvec.c        | 145 +++++++---
>   drivers/irqchip/irq-loongson-liointc.c      | 227 ++++++++++-----
>   drivers/irqchip/irq-loongson-pch-lpc.c      | 207 ++++++++++++++
>   drivers/irqchip/irq-loongson-pch-msi.c      | 131 ++++++---
>   drivers/irqchip/irq-loongson-pch-pic.c      | 177 +++++++++---
>   include/acpi/actbl2.h                       | 127 ++++++++-
>   include/linux/acpi.h                        |   4 +-
>   include/linux/cpuhotplug.h                  |   1 +
>   include/linux/irq.h                         |   1 +
>   kernel/irq/generic-chip.c                   |   2 +-
>   24 files changed, 1578 insertions(+), 311 deletions(-)
>   create mode 100644 drivers/irqchip/irq-loongarch-cpu.c
>   create mode 100644 drivers/irqchip/irq-loongson-eiointc.c
>   create mode 100644 drivers/irqchip/irq-loongson-pch-lpc.c
> 

Re: [PATCH V14 12/15] irqchip: Add Loongson Extended I/O interrupt controller support

[Marc Zyngier]

On Sun, 03 Jul 2022 09:45:29 +0100,
Jianmin Lv <lvjianmin@loongson.cn> wrote:
> 
> From: Huacai Chen <chenhuacai@loongson.cn>
> 
> EIOINTC stands for "Extended I/O Interrupts" that described in Section
> 11.2 of "Loongson 3A5000 Processor Reference Manual". For more
> information please refer Documentation/loongarch/irq-chip-model.rst.
> 
> Loongson-3A5000 has 4 cores per NUMA node, and each NUMA node has an
> EIOINTC; while Loongson-3C5000 has 16 cores per NUMA node, and each NUMA
> node has 4 EIOINTCs. In other words, 16 cores of one NUMA node in
> Loongson-3C5000 are organized in 4 groups, each group connects to an
> EIOINTC. We call the "group" here as an EIOINTC node, so each EIOINTC
> node always includes 4 cores (both in Loongson-3A5000 and Loongson-
> 3C5000).
> 
> Co-developed-by: Jianmin Lv <lvjianmin@loongson.cn>
> Signed-off-by: Jianmin Lv <lvjianmin@loongson.cn>
> Signed-off-by: Huacai Chen <chenhuacai@loongson.cn>
> ---
>  arch/loongarch/include/asm/irq.h       |  11 +-
>  drivers/irqchip/Kconfig                |  10 +
>  drivers/irqchip/Makefile               |   1 +
>  drivers/irqchip/irq-loongson-eiointc.c | 413 +++++++++++++++++++++++++++++++++
>  include/linux/cpuhotplug.h             |   1 +
>  5 files changed, 426 insertions(+), 10 deletions(-)
>  create mode 100644 drivers/irqchip/irq-loongson-eiointc.c
> 
> diff --git a/arch/loongarch/include/asm/irq.h b/arch/loongarch/include/asm/irq.h
> index a07315a..a826ac4 100644
> --- a/arch/loongarch/include/asm/irq.h
> +++ b/arch/loongarch/include/asm/irq.h
> @@ -87,15 +87,6 @@ struct acpi_vector_group {
>  extern int find_pch_pic(u32 gsi);
>  extern int eiointc_get_node(int id);
>  
> -static inline void eiointc_enable(void)
> -{
> -	uint64_t misc;
> -
> -	misc = iocsr_read64(LOONGARCH_IOCSR_MISC_FUNC);
> -	misc |= IOCSR_MISC_FUNC_EXT_IOI_EN;
> -	iocsr_write64(misc, LOONGARCH_IOCSR_MISC_FUNC);
> -}
> -
>  struct acpi_madt_lio_pic;
>  struct acpi_madt_eio_pic;
>  struct acpi_madt_ht_pic;
> @@ -107,7 +98,7 @@ static inline void eiointc_enable(void)
>  
>  int liointc_acpi_init(struct irq_domain *parent,
>  					struct acpi_madt_lio_pic *acpi_liointc);
> -struct irq_domain *eiointc_acpi_init(struct irq_domain *parent,
> +int eiointc_acpi_init(struct irq_domain *parent,
>  					struct acpi_madt_eio_pic *acpi_eiointc);
>  
>  int htvec_acpi_init(struct irq_domain *parent,
> diff --git a/drivers/irqchip/Kconfig b/drivers/irqchip/Kconfig
> index c1d527f..e918579 100644
> --- a/drivers/irqchip/Kconfig
> +++ b/drivers/irqchip/Kconfig
> @@ -555,6 +555,16 @@ config LOONGSON_LIOINTC
>  	help
>  	  Support for the Loongson Local I/O Interrupt Controller.
>  
> +config LOONGSON_EIOINTC
> +	bool "Loongson Extend I/O Interrupt Controller"
> +	depends on LOONGARCH
> +	depends on MACH_LOONGSON64
> +	default MACH_LOONGSON64
> +	select IRQ_DOMAIN_HIERARCHY
> +	select GENERIC_IRQ_CHIP
> +	help
> +	  Support for the Loongson3 Extend I/O Interrupt Vector Controller.
> +
>  config LOONGSON_HTPIC
>  	bool "Loongson3 HyperTransport PIC Controller"
>  	depends on MACH_LOONGSON64 && MIPS
> diff --git a/drivers/irqchip/Makefile b/drivers/irqchip/Makefile
> index 242b8b3..0cfd4f0 100644
> --- a/drivers/irqchip/Makefile
> +++ b/drivers/irqchip/Makefile
> @@ -104,6 +104,7 @@ obj-$(CONFIG_TI_SCI_INTR_IRQCHIP)	+= irq-ti-sci-intr.o
>  obj-$(CONFIG_TI_SCI_INTA_IRQCHIP)	+= irq-ti-sci-inta.o
>  obj-$(CONFIG_TI_PRUSS_INTC)		+= irq-pruss-intc.o
>  obj-$(CONFIG_LOONGSON_LIOINTC)		+= irq-loongson-liointc.o
> +obj-$(CONFIG_LOONGSON_EIOINTC)		+= irq-loongson-eiointc.o
>  obj-$(CONFIG_LOONGSON_HTPIC)		+= irq-loongson-htpic.o
>  obj-$(CONFIG_LOONGSON_HTVEC)		+= irq-loongson-htvec.o
>  obj-$(CONFIG_LOONGSON_PCH_PIC)		+= irq-loongson-pch-pic.o
> diff --git a/drivers/irqchip/irq-loongson-eiointc.c b/drivers/irqchip/irq-loongson-eiointc.c
> new file mode 100644
> index 0000000..9ddb9ac
> --- /dev/null
> +++ b/drivers/irqchip/irq-loongson-eiointc.c
> @@ -0,0 +1,413 @@
> +// SPDX-License-Identifier: GPL-2.0
> +/*
> + * Loongson Extend I/O Interrupt Controller support
> + *
> + * Copyright (C) 2020-2022 Loongson Technology Corporation Limited
> + */
> +
> +#define pr_fmt(fmt) "eiointc: " fmt
> +
> +#include <linux/interrupt.h>
> +#include <linux/irq.h>
> +#include <linux/irqchip.h>
> +#include <linux/irqdomain.h>
> +#include <linux/irqchip/chained_irq.h>
> +#include <linux/kernel.h>
> +#include <linux/platform_device.h>
> +#include <linux/of_address.h>
> +#include <linux/of_irq.h>
> +#include <linux/of_platform.h>
> +
> +#define EIOINTC_REG_NODEMAP	0x14a0
> +#define EIOINTC_REG_IPMAP	0x14c0
> +#define EIOINTC_REG_ENABLE	0x1600
> +#define EIOINTC_REG_BOUNCE	0x1680
> +#define EIOINTC_REG_ISR		0x1800
> +#define EIOINTC_REG_ROUTE	0x1c00
> +
> +#define VEC_REG_COUNT		4
> +#define VEC_COUNT_PER_REG	64
> +#define VEC_COUNT		(VEC_REG_COUNT * VEC_COUNT_PER_REG)
> +#define VEC_REG_IDX(irq_id)	((irq_id) / VEC_COUNT_PER_REG)
> +#define VEC_REG_BIT(irq_id)     ((irq_id) % VEC_COUNT_PER_REG)
> +#define EIOINTC_ALL_ENABLE	0xffffffff
> +
> +#define MAX_EIO_NODES		(NR_CPUS / CORES_PER_EIO_NODE)
> +
> +static int nr_pics;
> +
> +struct eiointc_priv {
> +	u32			node;
> +	nodemask_t		node_map;
> +	cpumask_t		cpuspan_map;
> +	struct fwnode_handle	*domain_handle;
> +	struct irq_domain	*eiointc_domain;
> +};
> +
> +static struct eiointc_priv *eiointc_priv[MAX_IO_PICS];
> +
> +static void eiointc_enable(void)
> +{
> +	uint64_t misc;
> +
> +	misc = iocsr_read64(LOONGARCH_IOCSR_MISC_FUNC);
> +	misc |= IOCSR_MISC_FUNC_EXT_IOI_EN;
> +	iocsr_write64(misc, LOONGARCH_IOCSR_MISC_FUNC);
> +}
> +
> +static int cpu_to_eio_node(int cpu)
> +{
> +	return cpu_logical_map(cpu) / CORES_PER_EIO_NODE;
> +}
> +
> +static void eiointc_set_irq_route(int pos, unsigned int cpu, unsigned int mnode, nodemask_t *node_map)
> +{
> +	int i, node, cpu_node, route_node;
> +	unsigned char coremap[MAX_EIO_NODES];
> +	uint32_t pos_off, data, data_byte, data_mask;
> +
> +	pos_off = pos & ~3;
> +	data_byte = pos & 3;
> +	data_mask = ~BIT_MASK(data_byte) & 0xf;
> +
> +	memset(coremap, 0, sizeof(unsigned char) * MAX_EIO_NODES);

This would be better written as an initialisation of the array:

	unsigned char coremap[MAX_EIO_NODES] = { };

> +
> +	/* Calculate node and coremap of target irq */
> +	cpu_node = cpu_logical_map(cpu) / CORES_PER_EIO_NODE;
> +	coremap[cpu_node] |= BIT(cpu_logical_map(cpu) % CORES_PER_EIO_NODE);
> +
> +	for_each_online_cpu(i) {
> +		node = cpu_to_eio_node(i);
> +		if (!node_isset(node, *node_map))
> +			continue;
> +
> +		/* EIO node 0 is in charge of inter-node interrupt dispatch */
> +		route_node = (node == mnode) ? cpu_node : node;
> +		data = ((coremap[node] | (route_node << 4)) << (data_byte * 8));
> +		csr_any_send(EIOINTC_REG_ROUTE + pos_off, data, data_mask, node * CORES_PER_EIO_NODE);
> +	}

But the coremap array doesn't make much sense. You only initialise
*one* byte in it, and the rest is always 0. Either it is completely
irrelevant and you should get rid of it, or this is buggy and you
should fix it.

> +}
> +
> +static DEFINE_RAW_SPINLOCK(affinity_lock);
> +
> +static int eiointc_set_irq_affinity(struct irq_data *d, const struct cpumask *affinity, bool force)
> +{
> +	unsigned int cpu;
> +	unsigned long flags;
> +	uint32_t vector, regaddr;
> +	struct cpumask intersect_affinity;
> +	struct eiointc_priv *priv = d->domain->host_data;
> +
> +	if (!IS_ENABLED(CONFIG_SMP))
> +		return -EPERM;

Is it even legal to build this architecture with !SMP?

> +
> +	raw_spin_lock_irqsave(&affinity_lock, flags);
> +
> +	cpumask_and(&intersect_affinity, affinity, cpu_online_mask);
> +	cpumask_and(&intersect_affinity, &intersect_affinity, &priv->cpuspan_map);
> +
> +	if (cpumask_empty(&intersect_affinity)) {
> +		raw_spin_unlock_irqrestore(&affinity_lock, flags);
> +		return -EINVAL;
> +	}
> +	cpu = cpumask_first(&intersect_affinity);
> +
> +	if (!d->parent_data)
> +		vector = d->hwirq;
> +	else
> +		vector = d->parent_data->hwirq;
> +
> +	regaddr = EIOINTC_REG_ENABLE + ((vector >> 5) << 2);
> +
> +	/* Mask target vector */
> +	csr_any_send(regaddr, EIOINTC_ALL_ENABLE & (~BIT(vector & 0x1F)), 0x0, 0);
> +	/* Set route for target vector */
> +	eiointc_set_irq_route(vector, cpu, priv->node, &priv->node_map);
> +	/* Unmask target vector */
> +	csr_any_send(regaddr, EIOINTC_ALL_ENABLE, 0x0, 0);
> +
> +	irq_data_update_effective_affinity(d, cpumask_of(cpu));
> +
> +	raw_spin_unlock_irqrestore(&affinity_lock, flags);
> +
> +	return IRQ_SET_MASK_OK;
> +}
> +
> +static int eiointc_index(int node)
> +{
> +	int i;
> +
> +	for (i = 0; i < nr_pics; i++) {
> +		if (node_isset(node, eiointc_priv[i]->node_map))
> +			return i;
> +	}
> +
> +	return -1;
> +}
> +
> +static int eiointc_router_init(unsigned int cpu)
> +{
> +	int i, bit;
> +	uint32_t data;
> +	uint32_t node = cpu_to_eio_node(cpu);
> +	uint32_t index = eiointc_index(node);
> +
> +	if (index < 0) {
> +		pr_err("Error: invalid nodemap!\n");
> +		return -1;
> +	}
> +
> +	if ((cpu_logical_map(cpu) % CORES_PER_EIO_NODE) == 0) {
> +		eiointc_enable();
> +
> +		for (i = 0; i < VEC_COUNT / 32; i++) {
> +			data = (((1 << (i * 2 + 1)) << 16) | (1 << (i * 2)));
> +			iocsr_write32(data, EIOINTC_REG_NODEMAP + i * 4);
> +		}
> +
> +		for (i = 0; i < VEC_COUNT / 32 / 4; i++) {
> +			bit = BIT(1 + index); /* Route to IP[1 + index] */
> +			data = bit | (bit << 8) | (bit << 16) | (bit << 24);
> +			iocsr_write32(data, EIOINTC_REG_IPMAP + i * 4);
> +		}
> +
> +		for (i = 0; i < VEC_COUNT / 4; i++) {
> +			/* Route to Node-0 Core-0 */
> +			if (index == 0)
> +				bit = BIT(cpu_logical_map(0));
> +			else
> +				bit = (eiointc_priv[index]->node << 4) | 1;
> +
> +			data = bit | (bit << 8) | (bit << 16) | (bit << 24);
> +			iocsr_write32(data, EIOINTC_REG_ROUTE + i * 4);
> +		}
> +
> +		for (i = 0; i < VEC_COUNT / 32; i++) {
> +			data = 0xffffffff;
> +			iocsr_write32(data, EIOINTC_REG_ENABLE + i * 4);
> +			iocsr_write32(data, EIOINTC_REG_BOUNCE + i * 4);
> +		}
> +	}
> +
> +	return 0;
> +}
> +
> +static void eiointc_irq_dispatch(struct irq_desc *desc)
> +{
> +	int i;
> +	u64 pending;
> +	bool handled = false;
> +	struct irq_chip *chip = irq_desc_get_chip(desc);
> +	struct eiointc_priv *priv = irq_desc_get_handler_data(desc);
> +
> +	chained_irq_enter(chip, desc);
> +
> +	for (i = 0; i < VEC_REG_COUNT; i++) {
> +		pending = iocsr_read64(EIOINTC_REG_ISR + (i << 3));
> +		iocsr_write64(pending, EIOINTC_REG_ISR + (i << 3));
> +		while (pending) {
> +			int bit = __ffs(pending);
> +			int irq = bit + VEC_COUNT_PER_REG * i;
> +
> +			generic_handle_domain_irq(priv->eiointc_domain, irq);
> +			pending &= ~BIT(bit);
> +			handled = true;
> +		}
> +	}
> +
> +	if (!handled)
> +		spurious_interrupt();
> +
> +	chained_irq_exit(chip, desc);
> +}
> +
> +static void eiointc_ack_irq(struct irq_data *d)
> +{
> +	if (d->parent_data)
> +		irq_chip_ack_parent(d);
> +}
> +
> +static void eiointc_mask_irq(struct irq_data *d)
> +{
> +	if (d->parent_data)
> +		irq_chip_mask_parent(d);
> +}
> +
> +static void eiointc_unmask_irq(struct irq_data *d)
> +{
> +	if (d->parent_data)
> +		irq_chip_unmask_parent(d);
> +}

It is pretty unclear to me under what circumstances some interrupts
have a parent, and some don't.

> +
> +static struct irq_chip eiointc_irq_chip = {
> +	.name			= "EIOINTC",
> +	.irq_ack		= eiointc_ack_irq,
> +	.irq_mask		= eiointc_mask_irq,
> +	.irq_unmask		= eiointc_unmask_irq,
> +	.irq_set_affinity	= eiointc_set_irq_affinity,

Under what circumstances can an interrupt be moved to another CPU?
Given that you have an EIO per 4-cpu group, I can see how the EIO can
move the affinity. But can you move an interrupt to a CPU belonging to
another EOIO? If you can, is any *other* interrupt affected by the
affinity change?

This is specially troubling as in general, chained irq handlers cannot
move interrupts without breaking the affinity of other interrupts, and
I'd like to know where we stand here.

> +};
> +
> +static int eiointc_domain_alloc(struct irq_domain *domain, unsigned int virq,
> +				unsigned int nr_irqs, void *arg)
> +{
> +	int ret;
> +	unsigned int i, type;
> +	unsigned long hwirq = 0;
> +	struct eiointc *priv = domain->host_data;
> +
> +	ret = irq_domain_translate_onecell(domain, arg, &hwirq, &type);
> +	if (ret)
> +		return ret;
> +
> +	for (i = 0; i < nr_irqs; i++) {
> +		irq_domain_set_info(domain, virq + i, hwirq + i, &eiointc_irq_chip,
> +					priv, handle_edge_irq, NULL, NULL);
> +	}
> +
> +	return 0;
> +}
> +
> +static void eiointc_domain_free(struct irq_domain *domain, unsigned int virq,
> +				unsigned int nr_irqs)
> +{
> +	int i;
> +
> +	for (i = 0; i < nr_irqs; i++) {
> +		struct irq_data *d = irq_domain_get_irq_data(domain, virq + i);
> +
> +		irq_set_handler(virq + i, NULL);
> +		irq_domain_reset_irq_data(d);
> +	}
> +}
> +
> +static const struct irq_domain_ops eiointc_domain_ops = {
> +	.translate	= irq_domain_translate_onecell,
> +	.alloc		= eiointc_domain_alloc,
> +	.free		= eiointc_domain_free,
> +};
> +
> +static void acpi_set_vec_parent(int node, struct irq_domain *parent, struct acpi_vector_group *vec_group)
> +{
> +	int i;
> +
> +	if (cpu_has_flatmode)
> +		node = cpu_to_node(node * CORES_PER_EIO_NODE);
> +
> +	for (i = 0; i < MAX_IO_PICS; i++) {
> +		if (node == vec_group[i].node) {
> +			vec_group[i].parent = parent;
> +			return;
> +		}
> +	}
> +}
> +
> +struct irq_domain *acpi_get_vec_parent(int node, struct acpi_vector_group *vec_group)
> +{
> +	int i;
> +
> +	for (i = 0; i < MAX_IO_PICS; i++) {
> +		if (node == vec_group[i].node)
> +			return vec_group[i].parent;
> +	}
> +	return NULL;
> +}
> +
> +static int __init
> +pch_pic_parse_madt(union acpi_subtable_headers *header,
> +		       const unsigned long end)
> +{
> +	struct acpi_madt_bio_pic *pchpic_entry = (struct acpi_madt_bio_pic *)header;
> +	unsigned int node = (pchpic_entry->address >> 44) & 0xf;
> +	struct irq_domain *parent = acpi_get_vec_parent(node, pch_group);
> +
> +	if (parent)
> +		return pch_pic_acpi_init(parent, pchpic_entry);
> +
> +	return -EINVAL;
> +}
> +
> +static int __init
> +pch_msi_parse_madt(union acpi_subtable_headers *header,
> +		       const unsigned long end)
> +{
> +	struct acpi_madt_msi_pic *pchmsi_entry = (struct acpi_madt_msi_pic *)header;
> +	struct irq_domain *parent = acpi_get_vec_parent(eiointc_priv[nr_pics - 1]->node, msi_group);
> +
> +	if (parent)
> +		return pch_msi_acpi_init(parent, pchmsi_entry);
> +
> +	return -EINVAL;
> +}
> +
> +static int __init acpi_cascade_irqdomain_init(void)
> +{
> +	acpi_table_parse_madt(ACPI_MADT_TYPE_BIO_PIC,
> +			      pch_pic_parse_madt, 0);
> +	acpi_table_parse_madt(ACPI_MADT_TYPE_MSI_PIC,
> +			      pch_msi_parse_madt, 1);
> +	return 0;
> +}
> +
> +int __init eiointc_acpi_init(struct irq_domain *parent,
> +				     struct acpi_madt_eio_pic *acpi_eiointc)
> +{
> +	int i, parent_irq;
> +	unsigned long node_map;
> +	struct eiointc_priv *priv;
> +
> +	if (!acpi_eiointc)
> +		return -EINVAL;

How can this happen?

> +
> +	priv = kzalloc(sizeof(*priv), GFP_KERNEL);
> +	if (!priv)
> +		return -ENOMEM;
> +
> +	priv->domain_handle = irq_domain_alloc_fwnode((phys_addr_t *)acpi_eiointc);
> +	if (!priv->domain_handle) {
> +		pr_err("Unable to allocate domain handle\n");
> +		goto out_free_priv;
> +	}
> +
> +	priv->node = acpi_eiointc->node;
> +	node_map = acpi_eiointc->node_map ? : -1ULL;
> +
> +	for_each_possible_cpu(i) {
> +		if (node_map & (1ULL << cpu_to_eio_node(i))) {
> +			node_set(cpu_to_eio_node(i), priv->node_map);
> +			cpumask_or(&priv->cpuspan_map, &priv->cpuspan_map, cpumask_of(i));
> +		}
> +	}
> +
> +	/* Setup IRQ domain */
> +	priv->eiointc_domain = irq_domain_create_linear(priv->domain_handle, VEC_COUNT,
> +					&eiointc_domain_ops, priv);
> +	if (!priv->eiointc_domain) {
> +		pr_err("loongson-eiointc: cannot add IRQ domain\n");
> +		goto out_free_handle;
> +	}
> +
> +	eiointc_priv[nr_pics++] = priv;
> +
> +	eiointc_router_init(0);
> +
> +	parent_irq = irq_create_mapping(parent, acpi_eiointc->cascade);
> +	irq_set_chained_handler_and_data(parent_irq, eiointc_irq_dispatch, priv);
> +
> +	cpuhp_setup_state_nocalls(CPUHP_AP_IRQ_LOONGARCH_STARTING,
> +				  "irqchip/loongarch/intc:starting",
> +				  eiointc_router_init, NULL);
> +
> +	acpi_set_vec_parent(acpi_eiointc->node, priv->eiointc_domain, pch_group);
> +	acpi_set_vec_parent(acpi_eiointc->node, priv->eiointc_domain, msi_group);
> +	acpi_cascade_irqdomain_init();
> +
> +	return 0;
> +
> +out_free_handle:
> +	irq_domain_free_fwnode(priv->domain_handle);
> +	priv->domain_handle = NULL;
> +out_free_priv:
> +	kfree(priv);
> +
> +	return -ENOMEM;
> +}
> diff --git a/include/linux/cpuhotplug.h b/include/linux/cpuhotplug.h
> index 19f0dbf..de662f3 100644
> --- a/include/linux/cpuhotplug.h
> +++ b/include/linux/cpuhotplug.h
> @@ -151,6 +151,7 @@ enum cpuhp_state {
>  	CPUHP_AP_IRQ_BCM2836_STARTING,
>  	CPUHP_AP_IRQ_MIPS_GIC_STARTING,
>  	CPUHP_AP_IRQ_RISCV_STARTING,
> +	CPUHP_AP_IRQ_LOONGARCH_STARTING,
>  	CPUHP_AP_IRQ_SIFIVE_PLIC_STARTING,
>  	CPUHP_AP_ARM_MVEBU_COHERENCY,
>  	CPUHP_AP_MICROCODE_LOADER,
> -- 
> 1.8.3.1
> 
> 

Thanks,

	M.

-- 
Without deviation from the norm, progress is not possible.

Re: [PATCH V14 13/15] irqchip: Add LoongArch CPU interrupt controller support

[Marc Zyngier]

On Sun, 03 Jul 2022 09:45:30 +0100,
Jianmin Lv <lvjianmin@loongson.cn> wrote:
> 
> From: Huacai Chen <chenhuacai@loongson.cn>
> 
> LoongArch CPUINTC stands for CSR.ECFG/CSR.ESTAT and related interrupt
> controller that described in Section 7.4 of "LoongArch Reference Manual,
> Vol 1". For more information please refer Documentation/loongarch/irq-
> chip-model.rst.
> 
> LoongArch CPUINTC has 13 interrupt sources: SWI0~1, HWI0~7, IPI, TI
> (Timer) and PCOV (PMC). IRQ mappings of HWI0~7 are configurable (can be
> created from DT/ACPI), but IPI, TI (Timer) and PCOV (PMC) are hardcoded
> bits, so we define get_xxx_irq() for them.

I really dislike this practice. Even if these 3 interrupts are well
known (their hwirqs are set in stone), you should be able to directly
create the interrupt from the rest of the kernel code.

All you have to do is to expose the fwnode_handle in the arch code
(just like you do for other interrupt controllers), retrieve the
domain and perform the mapping. No need for any extra arch-specific
API in the irqchip controller.

It would also be good to mention that this irqchip driver also probes
the all the rest of the interrupt hierarchy.

Thanks,

	M.

-- 
Without deviation from the norm, progress is not possible.

Re: [PATCH V14 00/15] irqchip: Add LoongArch-related irqchip drivers

[Marc Zyngier]

+ Rafael, Robert

On Sun, 03 Jul 2022 09:45:17 +0100,
Jianmin Lv <lvjianmin@loongson.cn> wrote:
> 
> LoongArch is a new RISC ISA, which is a bit like MIPS or RISC-V.
> LoongArch includes a reduced 32-bit version (LA32R), a standard 32-bit
> version (LA32S) and a 64-bit version (LA64). LoongArch use ACPI as its
> boot protocol LoongArch-specific interrupt controllers (similar to APIC)
> are already added in the ACPI Specification 6.5(which may be published in
> early June this year and the board is reviewing the draft).

Can the ACPI/ACPICA maintainers eyeball patch #1 in this series[1]? It
adds some new, yet unpublished ACPI MADT updates, and I need an Ack on
that before considering taking this series.

Patches 2 and 3 could also do with an Ack from the ACPI maintainers
(though Hanjun did review an earlier version).

Thanks,
	M.

[1] https://lore.kernel.org/r/1656837932-18257-2-git-send-email-lvjianmin@loongson.cn

-- 
Without deviation from the norm, progress is not possible.

Re: [PATCH V14 14/15] irqchip / ACPI: Introduce ACPI_IRQ_MODEL_LPIC for LoongArch

[Marc Zyngier]

On Sun, 03 Jul 2022 09:45:31 +0100,
Jianmin Lv <lvjianmin@loongson.cn> wrote:
> 
> For LoongArch, ACPI_IRQ_MODEL_LPIC is introduced, and then the
> callback acpi_get_gsi_domain_id and acpi_gsi_to_irq_fallback are
> implemented.
> 
> The acpi_get_gsi_domain_id callback returns related fwnode handle
> of irqdomain for different GSI range.
> 
> The acpi_gsi_to_irq_fallback will create new mapping for gsi when
> the mapping of it is not found.
> 
> Signed-off-by: Jianmin Lv <lvjianmin@loongson.cn>
> ---
>  drivers/acpi/bus.c                  |  3 +++
>  drivers/irqchip/irq-loongarch-cpu.c | 37 +++++++++++++++++++++++++++++++++++++
>  include/linux/acpi.h                |  1 +
>  3 files changed, 41 insertions(+)
> 
> diff --git a/drivers/acpi/bus.c b/drivers/acpi/bus.c
> index 86fa61a..63fbf00 100644
> --- a/drivers/acpi/bus.c
> +++ b/drivers/acpi/bus.c
> @@ -1145,6 +1145,9 @@ static int __init acpi_bus_init_irq(void)
>  	case ACPI_IRQ_MODEL_PLATFORM:
>  		message = "platform specific model";
>  		break;
> +	case ACPI_IRQ_MODEL_LPIC:
> +		message = "LPIC";
> +		break;
>  	default:
>  		pr_info("Unknown interrupt routing model\n");
>  		return -ENODEV;
> diff --git a/drivers/irqchip/irq-loongarch-cpu.c b/drivers/irqchip/irq-loongarch-cpu.c
> index c2f7411..1b241d7 100644
> --- a/drivers/irqchip/irq-loongarch-cpu.c
> +++ b/drivers/irqchip/irq-loongarch-cpu.c
> @@ -15,6 +15,41 @@
>  
>  static struct irq_domain *irq_domain;
>  
> +static int lpic_gsi_to_irq(u32 gsi)
> +{
> +	/* Only pch irqdomain transferring is required for LoongArch. */
> +	if (gsi >= GSI_MIN_PCH_IRQ && gsi <= GSI_MAX_PCH_IRQ)
> +		return acpi_register_gsi(NULL, gsi, ACPI_LEVEL_SENSITIVE, ACPI_ACTIVE_HIGH);
> +	return -1;

The expected return value on failure is 0 (which indicates that no
interrupt was mapped). Here, things will break as acpi_gsi_to_irq()
stores the result as unsigned, and compares the result to 0.

	M.

-- 
Without deviation from the norm, progress is not possible.

Re: [PATCH V14 12/15] irqchip: Add Loongson Extended I/O interrupt controller support

[maobibo]

Jianmin,

Since eiointc driver for loongarch comes from scratch, 
can we add only single node support for eiointc at beginning? 
And then add multiple-node support after the first version merged.

To be frankly, it is actually hard to understand logic of eiointc
for multiple-node support. However it is just my suggestion from my point
and the final code and decision comes from your self.

regards
bibo,mao

在 2022/7/3 16:45, Jianmin Lv 写道:
> From: Huacai Chen <chenhuacai@loongson.cn>
> 
> EIOINTC stands for "Extended I/O Interrupts" that described in Section
> 11.2 of "Loongson 3A5000 Processor Reference Manual". For more
> information please refer Documentation/loongarch/irq-chip-model.rst.
> 
> Loongson-3A5000 has 4 cores per NUMA node, and each NUMA node has an
> EIOINTC; while Loongson-3C5000 has 16 cores per NUMA node, and each NUMA
> node has 4 EIOINTCs. In other words, 16 cores of one NUMA node in
> Loongson-3C5000 are organized in 4 groups, each group connects to an
> EIOINTC. We call the "group" here as an EIOINTC node, so each EIOINTC
> node always includes 4 cores (both in Loongson-3A5000 and Loongson-
> 3C5000).
> 
> Co-developed-by: Jianmin Lv <lvjianmin@loongson.cn>
> Signed-off-by: Jianmin Lv <lvjianmin@loongson.cn>
> Signed-off-by: Huacai Chen <chenhuacai@loongson.cn>
> ---
>  arch/loongarch/include/asm/irq.h       |  11 +-
>  drivers/irqchip/Kconfig                |  10 +
>  drivers/irqchip/Makefile               |   1 +
>  drivers/irqchip/irq-loongson-eiointc.c | 413 +++++++++++++++++++++++++++++++++
>  include/linux/cpuhotplug.h             |   1 +
>  5 files changed, 426 insertions(+), 10 deletions(-)
>  create mode 100644 drivers/irqchip/irq-loongson-eiointc.c
> 
> diff --git a/arch/loongarch/include/asm/irq.h b/arch/loongarch/include/asm/irq.h
> index a07315a..a826ac4 100644
> --- a/arch/loongarch/include/asm/irq.h
> +++ b/arch/loongarch/include/asm/irq.h
> @@ -87,15 +87,6 @@ struct acpi_vector_group {
>  extern int find_pch_pic(u32 gsi);
>  extern int eiointc_get_node(int id);
>  
> -static inline void eiointc_enable(void)
> -{
> -	uint64_t misc;
> -
> -	misc = iocsr_read64(LOONGARCH_IOCSR_MISC_FUNC);
> -	misc |= IOCSR_MISC_FUNC_EXT_IOI_EN;
> -	iocsr_write64(misc, LOONGARCH_IOCSR_MISC_FUNC);
> -}
> -
>  struct acpi_madt_lio_pic;
>  struct acpi_madt_eio_pic;
>  struct acpi_madt_ht_pic;
> @@ -107,7 +98,7 @@ static inline void eiointc_enable(void)
>  
>  int liointc_acpi_init(struct irq_domain *parent,
>  					struct acpi_madt_lio_pic *acpi_liointc);
> -struct irq_domain *eiointc_acpi_init(struct irq_domain *parent,
> +int eiointc_acpi_init(struct irq_domain *parent,
>  					struct acpi_madt_eio_pic *acpi_eiointc);
>  
>  int htvec_acpi_init(struct irq_domain *parent,
> diff --git a/drivers/irqchip/Kconfig b/drivers/irqchip/Kconfig
> index c1d527f..e918579 100644
> --- a/drivers/irqchip/Kconfig
> +++ b/drivers/irqchip/Kconfig
> @@ -555,6 +555,16 @@ config LOONGSON_LIOINTC
>  	help
>  	  Support for the Loongson Local I/O Interrupt Controller.
>  
> +config LOONGSON_EIOINTC
> +	bool "Loongson Extend I/O Interrupt Controller"
> +	depends on LOONGARCH
> +	depends on MACH_LOONGSON64
> +	default MACH_LOONGSON64
> +	select IRQ_DOMAIN_HIERARCHY
> +	select GENERIC_IRQ_CHIP
> +	help
> +	  Support for the Loongson3 Extend I/O Interrupt Vector Controller.
> +
>  config LOONGSON_HTPIC
>  	bool "Loongson3 HyperTransport PIC Controller"
>  	depends on MACH_LOONGSON64 && MIPS
> diff --git a/drivers/irqchip/Makefile b/drivers/irqchip/Makefile
> index 242b8b3..0cfd4f0 100644
> --- a/drivers/irqchip/Makefile
> +++ b/drivers/irqchip/Makefile
> @@ -104,6 +104,7 @@ obj-$(CONFIG_TI_SCI_INTR_IRQCHIP)	+= irq-ti-sci-intr.o
>  obj-$(CONFIG_TI_SCI_INTA_IRQCHIP)	+= irq-ti-sci-inta.o
>  obj-$(CONFIG_TI_PRUSS_INTC)		+= irq-pruss-intc.o
>  obj-$(CONFIG_LOONGSON_LIOINTC)		+= irq-loongson-liointc.o
> +obj-$(CONFIG_LOONGSON_EIOINTC)		+= irq-loongson-eiointc.o
>  obj-$(CONFIG_LOONGSON_HTPIC)		+= irq-loongson-htpic.o
>  obj-$(CONFIG_LOONGSON_HTVEC)		+= irq-loongson-htvec.o
>  obj-$(CONFIG_LOONGSON_PCH_PIC)		+= irq-loongson-pch-pic.o
> diff --git a/drivers/irqchip/irq-loongson-eiointc.c b/drivers/irqchip/irq-loongson-eiointc.c
> new file mode 100644
> index 0000000..9ddb9ac
> --- /dev/null
> +++ b/drivers/irqchip/irq-loongson-eiointc.c
> @@ -0,0 +1,413 @@
> +// SPDX-License-Identifier: GPL-2.0
> +/*
> + * Loongson Extend I/O Interrupt Controller support
> + *
> + * Copyright (C) 2020-2022 Loongson Technology Corporation Limited
> + */
> +
> +#define pr_fmt(fmt) "eiointc: " fmt
> +
> +#include <linux/interrupt.h>
> +#include <linux/irq.h>
> +#include <linux/irqchip.h>
> +#include <linux/irqdomain.h>
> +#include <linux/irqchip/chained_irq.h>
> +#include <linux/kernel.h>
> +#include <linux/platform_device.h>
> +#include <linux/of_address.h>
> +#include <linux/of_irq.h>
> +#include <linux/of_platform.h>
> +
> +#define EIOINTC_REG_NODEMAP	0x14a0
> +#define EIOINTC_REG_IPMAP	0x14c0
> +#define EIOINTC_REG_ENABLE	0x1600
> +#define EIOINTC_REG_BOUNCE	0x1680
> +#define EIOINTC_REG_ISR		0x1800
> +#define EIOINTC_REG_ROUTE	0x1c00
> +
> +#define VEC_REG_COUNT		4
> +#define VEC_COUNT_PER_REG	64
> +#define VEC_COUNT		(VEC_REG_COUNT * VEC_COUNT_PER_REG)
> +#define VEC_REG_IDX(irq_id)	((irq_id) / VEC_COUNT_PER_REG)
> +#define VEC_REG_BIT(irq_id)     ((irq_id) % VEC_COUNT_PER_REG)
> +#define EIOINTC_ALL_ENABLE	0xffffffff
> +
> +#define MAX_EIO_NODES		(NR_CPUS / CORES_PER_EIO_NODE)
> +
> +static int nr_pics;
> +
> +struct eiointc_priv {
> +	u32			node;
> +	nodemask_t		node_map;
> +	cpumask_t		cpuspan_map;
> +	struct fwnode_handle	*domain_handle;
> +	struct irq_domain	*eiointc_domain;
> +};
> +
> +static struct eiointc_priv *eiointc_priv[MAX_IO_PICS];
> +
> +static void eiointc_enable(void)
> +{
> +	uint64_t misc;
> +
> +	misc = iocsr_read64(LOONGARCH_IOCSR_MISC_FUNC);
> +	misc |= IOCSR_MISC_FUNC_EXT_IOI_EN;
> +	iocsr_write64(misc, LOONGARCH_IOCSR_MISC_FUNC);
> +}
> +
> +static int cpu_to_eio_node(int cpu)
> +{
> +	return cpu_logical_map(cpu) / CORES_PER_EIO_NODE;
> +}
> +
> +static void eiointc_set_irq_route(int pos, unsigned int cpu, unsigned int mnode, nodemask_t *node_map)
> +{
> +	int i, node, cpu_node, route_node;
> +	unsigned char coremap[MAX_EIO_NODES];
> +	uint32_t pos_off, data, data_byte, data_mask;
> +
> +	pos_off = pos & ~3;
> +	data_byte = pos & 3;
> +	data_mask = ~BIT_MASK(data_byte) & 0xf;
> +
> +	memset(coremap, 0, sizeof(unsigned char) * MAX_EIO_NODES);
> +
> +	/* Calculate node and coremap of target irq */
> +	cpu_node = cpu_logical_map(cpu) / CORES_PER_EIO_NODE;
> +	coremap[cpu_node] |= BIT(cpu_logical_map(cpu) % CORES_PER_EIO_NODE);
> +
> +	for_each_online_cpu(i) {
> +		node = cpu_to_eio_node(i);
> +		if (!node_isset(node, *node_map))
> +			continue;
> +
> +		/* EIO node 0 is in charge of inter-node interrupt dispatch */
> +		route_node = (node == mnode) ? cpu_node : node;
> +		data = ((coremap[node] | (route_node << 4)) << (data_byte * 8));
> +		csr_any_send(EIOINTC_REG_ROUTE + pos_off, data, data_mask, node * CORES_PER_EIO_NODE);
> +	}
> +}
> +
> +static DEFINE_RAW_SPINLOCK(affinity_lock);
> +
> +static int eiointc_set_irq_affinity(struct irq_data *d, const struct cpumask *affinity, bool force)
> +{
> +	unsigned int cpu;
> +	unsigned long flags;
> +	uint32_t vector, regaddr;
> +	struct cpumask intersect_affinity;
> +	struct eiointc_priv *priv = d->domain->host_data;
> +
> +	if (!IS_ENABLED(CONFIG_SMP))
> +		return -EPERM;
> +
> +	raw_spin_lock_irqsave(&affinity_lock, flags);
> +
> +	cpumask_and(&intersect_affinity, affinity, cpu_online_mask);
> +	cpumask_and(&intersect_affinity, &intersect_affinity, &priv->cpuspan_map);
> +
> +	if (cpumask_empty(&intersect_affinity)) {
> +		raw_spin_unlock_irqrestore(&affinity_lock, flags);
> +		return -EINVAL;
> +	}
> +	cpu = cpumask_first(&intersect_affinity);
> +
> +	if (!d->parent_data)
> +		vector = d->hwirq;
> +	else
> +		vector = d->parent_data->hwirq;
> +
> +	regaddr = EIOINTC_REG_ENABLE + ((vector >> 5) << 2);
> +
> +	/* Mask target vector */
> +	csr_any_send(regaddr, EIOINTC_ALL_ENABLE & (~BIT(vector & 0x1F)), 0x0, 0);
> +	/* Set route for target vector */
> +	eiointc_set_irq_route(vector, cpu, priv->node, &priv->node_map);
> +	/* Unmask target vector */
> +	csr_any_send(regaddr, EIOINTC_ALL_ENABLE, 0x0, 0);
> +
> +	irq_data_update_effective_affinity(d, cpumask_of(cpu));
> +
> +	raw_spin_unlock_irqrestore(&affinity_lock, flags);
> +
> +	return IRQ_SET_MASK_OK;
> +}
> +
> +static int eiointc_index(int node)
> +{
> +	int i;
> +
> +	for (i = 0; i < nr_pics; i++) {
> +		if (node_isset(node, eiointc_priv[i]->node_map))
> +			return i;
> +	}
> +
> +	return -1;
> +}
> +
> +static int eiointc_router_init(unsigned int cpu)
> +{
> +	int i, bit;
> +	uint32_t data;
> +	uint32_t node = cpu_to_eio_node(cpu);
> +	uint32_t index = eiointc_index(node);
> +
> +	if (index < 0) {
> +		pr_err("Error: invalid nodemap!\n");
> +		return -1;
> +	}
> +
> +	if ((cpu_logical_map(cpu) % CORES_PER_EIO_NODE) == 0) {
> +		eiointc_enable();
> +
> +		for (i = 0; i < VEC_COUNT / 32; i++) {
> +			data = (((1 << (i * 2 + 1)) << 16) | (1 << (i * 2)));
> +			iocsr_write32(data, EIOINTC_REG_NODEMAP + i * 4);
> +		}
> +
> +		for (i = 0; i < VEC_COUNT / 32 / 4; i++) {
> +			bit = BIT(1 + index); /* Route to IP[1 + index] */
> +			data = bit | (bit << 8) | (bit << 16) | (bit << 24);
> +			iocsr_write32(data, EIOINTC_REG_IPMAP + i * 4);
> +		}
> +
> +		for (i = 0; i < VEC_COUNT / 4; i++) {
> +			/* Route to Node-0 Core-0 */
> +			if (index == 0)
> +				bit = BIT(cpu_logical_map(0));
> +			else
> +				bit = (eiointc_priv[index]->node << 4) | 1;
> +
> +			data = bit | (bit << 8) | (bit << 16) | (bit << 24);
> +			iocsr_write32(data, EIOINTC_REG_ROUTE + i * 4);
> +		}
> +
> +		for (i = 0; i < VEC_COUNT / 32; i++) {
> +			data = 0xffffffff;
> +			iocsr_write32(data, EIOINTC_REG_ENABLE + i * 4);
> +			iocsr_write32(data, EIOINTC_REG_BOUNCE + i * 4);
> +		}
> +	}
> +
> +	return 0;
> +}
> +
> +static void eiointc_irq_dispatch(struct irq_desc *desc)
> +{
> +	int i;
> +	u64 pending;
> +	bool handled = false;
> +	struct irq_chip *chip = irq_desc_get_chip(desc);
> +	struct eiointc_priv *priv = irq_desc_get_handler_data(desc);
> +
> +	chained_irq_enter(chip, desc);
> +
> +	for (i = 0; i < VEC_REG_COUNT; i++) {
> +		pending = iocsr_read64(EIOINTC_REG_ISR + (i << 3));
> +		iocsr_write64(pending, EIOINTC_REG_ISR + (i << 3));
> +		while (pending) {
> +			int bit = __ffs(pending);
> +			int irq = bit + VEC_COUNT_PER_REG * i;
> +
> +			generic_handle_domain_irq(priv->eiointc_domain, irq);
> +			pending &= ~BIT(bit);
> +			handled = true;
> +		}
> +	}
> +
> +	if (!handled)
> +		spurious_interrupt();
> +
> +	chained_irq_exit(chip, desc);
> +}
> +
> +static void eiointc_ack_irq(struct irq_data *d)
> +{
> +	if (d->parent_data)
> +		irq_chip_ack_parent(d);
> +}
> +
> +static void eiointc_mask_irq(struct irq_data *d)
> +{
> +	if (d->parent_data)
> +		irq_chip_mask_parent(d);
> +}
> +
> +static void eiointc_unmask_irq(struct irq_data *d)
> +{
> +	if (d->parent_data)
> +		irq_chip_unmask_parent(d);
> +}
> +
> +static struct irq_chip eiointc_irq_chip = {
> +	.name			= "EIOINTC",
> +	.irq_ack		= eiointc_ack_irq,
> +	.irq_mask		= eiointc_mask_irq,
> +	.irq_unmask		= eiointc_unmask_irq,
> +	.irq_set_affinity	= eiointc_set_irq_affinity,
> +};
> +
> +static int eiointc_domain_alloc(struct irq_domain *domain, unsigned int virq,
> +				unsigned int nr_irqs, void *arg)
> +{
> +	int ret;
> +	unsigned int i, type;
> +	unsigned long hwirq = 0;
> +	struct eiointc *priv = domain->host_data;
> +
> +	ret = irq_domain_translate_onecell(domain, arg, &hwirq, &type);
> +	if (ret)
> +		return ret;
> +
> +	for (i = 0; i < nr_irqs; i++) {
> +		irq_domain_set_info(domain, virq + i, hwirq + i, &eiointc_irq_chip,
> +					priv, handle_edge_irq, NULL, NULL);
> +	}
> +
> +	return 0;
> +}
> +
> +static void eiointc_domain_free(struct irq_domain *domain, unsigned int virq,
> +				unsigned int nr_irqs)
> +{
> +	int i;
> +
> +	for (i = 0; i < nr_irqs; i++) {
> +		struct irq_data *d = irq_domain_get_irq_data(domain, virq + i);
> +
> +		irq_set_handler(virq + i, NULL);
> +		irq_domain_reset_irq_data(d);
> +	}
> +}
> +
> +static const struct irq_domain_ops eiointc_domain_ops = {
> +	.translate	= irq_domain_translate_onecell,
> +	.alloc		= eiointc_domain_alloc,
> +	.free		= eiointc_domain_free,
> +};
> +
> +static void acpi_set_vec_parent(int node, struct irq_domain *parent, struct acpi_vector_group *vec_group)
> +{
> +	int i;
> +
> +	if (cpu_has_flatmode)
> +		node = cpu_to_node(node * CORES_PER_EIO_NODE);
> +
> +	for (i = 0; i < MAX_IO_PICS; i++) {
> +		if (node == vec_group[i].node) {
> +			vec_group[i].parent = parent;
> +			return;
> +		}
> +	}
> +}
> +
> +struct irq_domain *acpi_get_vec_parent(int node, struct acpi_vector_group *vec_group)
> +{
> +	int i;
> +
> +	for (i = 0; i < MAX_IO_PICS; i++) {
> +		if (node == vec_group[i].node)
> +			return vec_group[i].parent;
> +	}
> +	return NULL;
> +}
> +
> +static int __init
> +pch_pic_parse_madt(union acpi_subtable_headers *header,
> +		       const unsigned long end)
> +{
> +	struct acpi_madt_bio_pic *pchpic_entry = (struct acpi_madt_bio_pic *)header;
> +	unsigned int node = (pchpic_entry->address >> 44) & 0xf;
> +	struct irq_domain *parent = acpi_get_vec_parent(node, pch_group);
> +
> +	if (parent)
> +		return pch_pic_acpi_init(parent, pchpic_entry);
> +
> +	return -EINVAL;
> +}
> +
> +static int __init
> +pch_msi_parse_madt(union acpi_subtable_headers *header,
> +		       const unsigned long end)
> +{
> +	struct acpi_madt_msi_pic *pchmsi_entry = (struct acpi_madt_msi_pic *)header;
> +	struct irq_domain *parent = acpi_get_vec_parent(eiointc_priv[nr_pics - 1]->node, msi_group);
> +
> +	if (parent)
> +		return pch_msi_acpi_init(parent, pchmsi_entry);
> +
> +	return -EINVAL;
> +}
> +
> +static int __init acpi_cascade_irqdomain_init(void)
> +{
> +	acpi_table_parse_madt(ACPI_MADT_TYPE_BIO_PIC,
> +			      pch_pic_parse_madt, 0);
> +	acpi_table_parse_madt(ACPI_MADT_TYPE_MSI_PIC,
> +			      pch_msi_parse_madt, 1);
> +	return 0;
> +}
> +
> +int __init eiointc_acpi_init(struct irq_domain *parent,
> +				     struct acpi_madt_eio_pic *acpi_eiointc)
> +{
> +	int i, parent_irq;
> +	unsigned long node_map;
> +	struct eiointc_priv *priv;
> +
> +	if (!acpi_eiointc)
> +		return -EINVAL;
> +
> +	priv = kzalloc(sizeof(*priv), GFP_KERNEL);
> +	if (!priv)
> +		return -ENOMEM;
> +
> +	priv->domain_handle = irq_domain_alloc_fwnode((phys_addr_t *)acpi_eiointc);
> +	if (!priv->domain_handle) {
> +		pr_err("Unable to allocate domain handle\n");
> +		goto out_free_priv;
> +	}
> +
> +	priv->node = acpi_eiointc->node;
> +	node_map = acpi_eiointc->node_map ? : -1ULL;
> +
> +	for_each_possible_cpu(i) {
> +		if (node_map & (1ULL << cpu_to_eio_node(i))) {
> +			node_set(cpu_to_eio_node(i), priv->node_map);
> +			cpumask_or(&priv->cpuspan_map, &priv->cpuspan_map, cpumask_of(i));
> +		}
> +	}
> +
> +	/* Setup IRQ domain */
> +	priv->eiointc_domain = irq_domain_create_linear(priv->domain_handle, VEC_COUNT,
> +					&eiointc_domain_ops, priv);
> +	if (!priv->eiointc_domain) {
> +		pr_err("loongson-eiointc: cannot add IRQ domain\n");
> +		goto out_free_handle;
> +	}
> +
> +	eiointc_priv[nr_pics++] = priv;
> +
> +	eiointc_router_init(0);
> +
> +	parent_irq = irq_create_mapping(parent, acpi_eiointc->cascade);
> +	irq_set_chained_handler_and_data(parent_irq, eiointc_irq_dispatch, priv);
> +
> +	cpuhp_setup_state_nocalls(CPUHP_AP_IRQ_LOONGARCH_STARTING,
> +				  "irqchip/loongarch/intc:starting",
> +				  eiointc_router_init, NULL);
> +
> +	acpi_set_vec_parent(acpi_eiointc->node, priv->eiointc_domain, pch_group);
> +	acpi_set_vec_parent(acpi_eiointc->node, priv->eiointc_domain, msi_group);
> +	acpi_cascade_irqdomain_init();
> +
> +	return 0;
> +
> +out_free_handle:
> +	irq_domain_free_fwnode(priv->domain_handle);
> +	priv->domain_handle = NULL;
> +out_free_priv:
> +	kfree(priv);
> +
> +	return -ENOMEM;
> +}
> diff --git a/include/linux/cpuhotplug.h b/include/linux/cpuhotplug.h
> index 19f0dbf..de662f3 100644
> --- a/include/linux/cpuhotplug.h
> +++ b/include/linux/cpuhotplug.h
> @@ -151,6 +151,7 @@ enum cpuhp_state {
>  	CPUHP_AP_IRQ_BCM2836_STARTING,
>  	CPUHP_AP_IRQ_MIPS_GIC_STARTING,
>  	CPUHP_AP_IRQ_RISCV_STARTING,
> +	CPUHP_AP_IRQ_LOONGARCH_STARTING,
>  	CPUHP_AP_IRQ_SIFIVE_PLIC_STARTING,
>  	CPUHP_AP_ARM_MVEBU_COHERENCY,
>  	CPUHP_AP_MICROCODE_LOADER,

Re: [PATCH V14 00/15] irqchip: Add LoongArch-related irqchip drivers

[Jianmin Lv]

Ok, Zeyuan, I'll CC loongarch@lists.linux.dev in future version.

On 2022/7/7 下午8:08, Hu Zeyuan wrote:
> Hi,Jianmin,
> Could you CC the kernel mailing list of loongarch[1] when you submitting 
> patches for LoongArch?
> 
> [1]loongarch@lists.linux.dev
> 
> Thanks!
> 
> 在 2022/7/3 16:45, Jianmin Lv 写道:
>> LoongArch is a new RISC ISA, which is a bit like MIPS or RISC-V.
>> LoongArch includes a reduced 32-bit version (LA32R), a standard 32-bit
>> version (LA32S) and a 64-bit version (LA64). LoongArch use ACPI as its
>> boot protocol LoongArch-specific interrupt controllers (similar to APIC)
>> are already added in the ACPI Specification 6.5(which may be published in
>> early June this year and the board is reviewing the draft).
>>
>> Currently, LoongArch based processors (e.g. Loongson-3A5000) can only
>> work together with LS7A chipsets. The irq chips in LoongArch computers
>> include CPUINTC (CPU Core Interrupt Controller), LIOINTC (Legacy I/O
>> Interrupt Controller), EIOINTC (Extended I/O Interrupt Controller),
>> HTVECINTC (Hyper-Transport Vector Interrupt Controller), PCH-PIC (Main
>> Interrupt Controller in LS7A chipset), PCH-LPC (LPC Interrupt Controller
>> in LS7A chipset) and PCH-MSI (MSI Interrupt Controller).
>>
>> CPUINTC is a per-core controller (in CPU), LIOINTC/EIOINTC/HTVECINTC are
>> per-package controllers (in CPU), while PCH-PIC/PCH-LPC/PCH-MSI are all
>> controllers out of CPU (i.e., in chipsets). These controllers (in other
>> words, irqchips) are linked in a hierarchy, and there are two models of
>> hierarchy (legacy model and extended model).
>>
>> Legacy IRQ model:
>>
>> In this model, the IPI (Inter-Processor Interrupt) and CPU Local Timer
>> interrupt go to CPUINTC directly, CPU UARTS interrupts go to LIOINTC,
>> while all other devices interrupts go to PCH-PIC/PCH-LPC/PCH-MSI and
>> gathered by HTVECINTC, and then go to LIOINTC, and then CPUINTC.
>>
>>   +---------------------------------------------+
>>   |                                             |
>>   |    +-----+     +---------+     +-------+    |
>>   |    | IPI | --> | CPUINTC | <-- | Timer |    |
>>   |    +-----+     +---------+     +-------+    |
>>   |                     ^                       |
>>   |                     |                       |
>>   |                +---------+     +-------+    |
>>   |                | LIOINTC | <-- | UARTs |    |
>>   |                +---------+     +-------+    |
>>   |                     ^                       |
>>   |                     |                       |
>>   |               +-----------+                 |
>>   |               | HTVECINTC |                 |
>>   |               +-----------+                 |
>>   |                ^         ^                  |
>>   |                |         |                  |
>>   |          +---------+ +---------+            |
>>   |          | PCH-PIC | | PCH-MSI |            |
>>   |          +---------+ +---------+            |
>>   |            ^     ^           ^              |
>>   |            |     |           |              |
>>   |    +---------+ +---------+ +---------+      |
>>   |    | PCH-LPC | | Devices | | Devices |      |
>>   |    +---------+ +---------+ +---------+      |
>>   |         ^                                   |
>>   |         |                                   |
>>   |    +---------+                              |
>>   |    | Devices |                              |
>>   |    +---------+                              |
>>   |                                             |
>>   |                                             |
>>   +---------------------------------------------+
>>
>> Extended IRQ model:
>>
>> In this model, the IPI (Inter-Processor Interrupt) and CPU Local Timer
>> interrupt go to CPUINTC directly, CPU UARTS interrupts go to LIOINTC,
>> while all other devices interrupts go to PCH-PIC/PCH-LPC/PCH-MSI and
>> gathered by EIOINTC, and then go to to CPUINTC directly.
>>
>>   +--------------------------------------------------------+
>>   |                                                        |
>>   |         +-----+     +---------+     +-------+          |
>>   |         | IPI | --> | CPUINTC | <-- | Timer |          |
>>   |         +-----+     +---------+     +-------+          |
>>   |                      ^       ^                         |
>>   |                      |       |                         |
>>   |               +---------+ +---------+     +-------+    |
>>   |               | EIOINTC | | LIOINTC | <-- | UARTs |    |
>>   |               +---------+ +---------+     +-------+    |
>>   |                ^       ^                               |
>>   |                |       |                               |
>>   |         +---------+ +---------+                        |
>>   |         | PCH-PIC | | PCH-MSI |                        |
>>   |         +---------+ +---------+                        |
>>   |           ^     ^           ^                          |
>>   |           |     |           |                          |
>>   |   +---------+ +---------+ +---------+                  |
>>   |   | PCH-LPC | | Devices | | Devices |                  |
>>   |   +---------+ +---------+ +---------+                  |
>>   |        ^                                               |
>>   |        |                                               |
>>   |   +---------+                                          |
>>   |   | Devices |                                          |
>>   |   +---------+                                          |
>>   |                                                        |
>>   |                                                        |
>>   +--------------------------------------------------------+
>>
>> The hierarchy model is constructed by parsing irq contronler structures
>> in MADT. Some controllers((e.g. LIOINTC, HTVECINTC, EIOINTC and PCH-LPC)
>> are hardcodingly connected to their parents, so their irqdomins are
>> separately routed to their parents in a fixed way. Some controllers
>> (e.g. PCH-PIC and PCH-MSI) could be routed to different parents for 
>> different
>> CPU. The firmware will config EIOINTC for the newer CPU and config 
>> HTVECINTC
>> for old CPU in MADT. By this way, PCH-PIC and PCH-MSI irqdomain can 
>> only be
>> routed one parent irqdomin: HTVECINTC or EIOINTC.
>>
>>
>> Example of irqchip topology in a system with  two chipsets:
>>
>>   +------------------------------------------------------------+
>>   |                                                            |
>>   |                     +------------------+                   |
>>   |                     |      CPUINTC     |                   |
>>   |                     +------------------+                   |
>>   |                     ^                  ^                   |
>>   |                     |                  |                   |
>>   |          +----------+                  +----------+        |
>>   |          | EIOINTC 0|                  | EIOINTC 1|        |
>>   |          +----------+                  +----------+        |
>>   |          ^          ^                  ^          ^        |
>>   |          |          |                  |          |        |
>>   | +----------+   +----------+   +----------+    +----------+ |
>>   | | PCH-PIC 0|   | PCH-MSI 0|   | PCH-PIC 1|    | PCH-MSI 1| |
>>   | +----------+   +----------+   +----------+    +----------+ |
>>   |                                                            |
>>   |                                                            |
>>   +------------------------------------------------------------+
>>
>> For systems with two chipsets, there are tow group(consists of 
>> EIOINTC, PCH-PIC and PCH-MSI) irqdomains,
>> and each group has same node id. So we defined a structure to mantain 
>> the relation of node and it's parent irqdomain.
>>
>> struct acpi_vector_group {
>>          int node;
>>     int pci_segment;
>>          struct irq_domain *parent;
>> };
>>
>> The initialization and use of acpi_vector_group array are following:
>>
>> 1 Entry of struct acpi_vector_group array initialization:
>>
>> By parsing MCFG, the node id（from bit44-47 of Base Address）and pci 
>> segment are extracted. And from MADT, we have the node id of each 
>> EIOINTC.
>>
>> entry.node = node id of pci segment
>> entry.pci_segment = pci segment (only for msi irqdomain)
>>
>> By matching node id of entry and EIOINTC to set parent.
>>
>> entry.parent = EIOINTC irqdomain(node id of EIOINTC == node id of pci 
>> segment)
>>
>> 2 Get parent irqdomain for PCH-PIC:
>>
>>> From MADT, we have the node id of each PCH-PIC(from bit44-47 of Base 
>>> Address).
>> if (node of entry i == node of PCH-PIC)
>>     return entrys[i].parent;
>>
>> 3 Get parent irqdomain for PCH-MSI of pci segment:
>>
>>     return entrys[i].parent; (i is the index of msi irqdomain)
>>
>> 4 How to select a correct irqdomain to map irq for a device?
>> For devices using legacy irq behind PCH-PIC, GSI is used to select 
>> correct PCH-PIC irqdomain.
>> For devices using msi irq behind PCH-MSI, the pci segmen of the device 
>> is used to select correct PCH-MSI irqdomain.
>>
>> V1 -> V2:
>> 1, Remove queued patches;
>> 2, Move common logic of DT/ACPI probing to common functions;
>> 3, Split .suspend()/.resume() functions to separate patches.
>>
>> V2 -> V3:
>> 1, Fix a bug for loongson-pch-pic probe;
>> 2, Some minor improvements for LPC controller.
>>
>> V3 -> V4:
>> 1, Rework the CPU interrupt controller driver;
>> 2, Some minor improvements for other controllers.
>>
>> V4 -> V5:
>> 1, Add a description of LoonArch's IRQ model;
>> 2, Support multiple EIOINTCs in one system;
>> 3, Some minor improvements for other controllers.
>>
>> V5 -> V6:
>> 1, Attach a fwnode to CPUINTC irq domain;
>> 2, Use raw spinlock instead of generic spinlock;
>> 3, Improve the method of restoring EIOINTC state;
>> 4, Update documentation, comments and commit messages.
>>
>> V6 -> V7:
>> 1, Fix build warnings reported by kernel test robot.
>>
>> V7 -> V8:
>> 1, Add arguments sanity checking for irqchip init functions;
>> 2, Support Loongson-3C5000 (One NUMA Node includes 4 EIOINTC Node).
>>
>> V8 -> V9:
>> 1, Rebase on 5.17-rc5;
>> 2, Update cover letter;
>> 3, Some small improvements.
>>
>> V9 -> V10:
>> 1, Rebase on 5.17-rc6;
>> 2, Fix build warnings reported by kernel test robot.
>>
>> V10 -> V11:
>> 1, Rebase on 5.18-rc4;
>> 2, Fix irq affinity setting for EIOINTC;
>> 3, Fix hwirq allocation failure for EIOINTC.
>>
>> V11 -> RFC:
>> 1, Refactored the way to build irqchip hierarchy topology.
>>
>> RFC -> RFC V2:
>> 1, Move all IO-interrupt related code to driver/irqchip from arch 
>> directory.
>> 2. Add description for an example of two chipsets system.
>>
>> RFC V2 -> RFC V3:
>> 1, Add support for multiple GSI domains
>> 2, Use ACPI_GENERIC_GSI for GSI handling
>> 3, Drop suspend-resume stuff
>> 4, Export fwnode handles instead of irq domain handles
>>
>> RFC V3 -> V12:
>> 1, Address patch attributions of the patch series
>>
>> V12 -> V13
>> 1 Based on 5.19-rc2
>> 2 Remove arch specified gsi code
>> 3 Split some 'common' code into the various drivers where they belong.
>> 4 Allow acpi_gsi_to_irq() to have an arch-specific fallback
>>
>> V13 -> V14
>> 1 Add LoongArch-specified APICs definition
>> 2 Use the way in CPUINTC driver to call pch-pic and pch-msi entry
>> 3 Fix compiling and regression issue for OF path
>>
>> Huacai Chen (8):
>>    ACPICA: MADT: Add LoongArch APICs support
>>    irqchip: Add Loongson PCH LPC controller support
>>    irqchip/loongson-pch-pic: Add ACPI init support
>>    irqchip/loongson-pch-msi: Add ACPI init support
>>    irqchip/loongson-htvec: Add ACPI init support
>>    irqchip/loongson-liointc: Add ACPI init support
>>    irqchip: Add Loongson Extended I/O interrupt controller support
>>    irqchip: Add LoongArch CPU interrupt controller support
>>
>> Jianmin Lv (5):
>>    genirq/generic_chip: export irq_unmap_generic_chip
>>    LoongArch: Use ACPI_GENERIC_GSI for gsi handling
>>    LoongArch: prepare to support multiple pch-pic and pch-msi irqdomain
>>    irqchip / ACPI: Introduce ACPI_IRQ_MODEL_LPIC for LoongArch
>>    LoongArch: Fix irq number for timer and ipi
>>
>> Marc Zyngier (2):
>>    APCI: irq: Add support for multiple GSI domains
>>    ACPI: irq: Allow acpi_gsi_to_irq() to have an arch-specific fallback
>>
>>   arch/loongarch/Kconfig                      |   1 +
>>   arch/loongarch/include/asm/irq.h            |  42 ++-
>>   arch/loongarch/kernel/acpi.c                |  65 -----
>>   arch/loongarch/kernel/irq.c                 |  45 ++-
>>   arch/loongarch/kernel/time.c                |   2 +-
>>   arch/mips/include/asm/mach-loongson64/irq.h |   2 +-
>>   drivers/acpi/bus.c                          |   3 +
>>   drivers/acpi/irq.c                          |  58 ++--
>>   drivers/irqchip/Kconfig                     |  28 ++
>>   drivers/irqchip/Makefile                    |   3 +
>>   drivers/irqchip/irq-gic-v3.c                |  18 +-
>>   drivers/irqchip/irq-gic.c                   |  18 +-
>>   drivers/irqchip/irq-loongarch-cpu.c         | 169 ++++++++++++
>>   drivers/irqchip/irq-loongson-eiointc.c      | 413 
>> ++++++++++++++++++++++++++++
>>   drivers/irqchip/irq-loongson-htvec.c        | 145 +++++++---
>>   drivers/irqchip/irq-loongson-liointc.c      | 227 ++++++++++-----
>>   drivers/irqchip/irq-loongson-pch-lpc.c      | 207 ++++++++++++++
>>   drivers/irqchip/irq-loongson-pch-msi.c      | 131 ++++++---
>>   drivers/irqchip/irq-loongson-pch-pic.c      | 177 +++++++++---
>>   include/acpi/actbl2.h                       | 127 ++++++++-
>>   include/linux/acpi.h                        |   4 +-
>>   include/linux/cpuhotplug.h                  |   1 +
>>   include/linux/irq.h                         |   1 +
>>   kernel/irq/generic-chip.c                   |   2 +-
>>   24 files changed, 1578 insertions(+), 311 deletions(-)
>>   create mode 100644 drivers/irqchip/irq-loongarch-cpu.c
>>   create mode 100644 drivers/irqchip/irq-loongson-eiointc.c
>>   create mode 100644 drivers/irqchip/irq-loongson-pch-lpc.c
>>

Re: [PATCH V14 14/15] irqchip / ACPI: Introduce ACPI_IRQ_MODEL_LPIC for LoongArch

[Jianmin Lv]

On 2022/7/7 下午8:59, Marc Zyngier wrote:
> On Sun, 03 Jul 2022 09:45:31 +0100,
> Jianmin Lv <lvjianmin@loongson.cn> wrote:
>>
>> For LoongArch, ACPI_IRQ_MODEL_LPIC is introduced, and then the
>> callback acpi_get_gsi_domain_id and acpi_gsi_to_irq_fallback are
>> implemented.
>>
>> The acpi_get_gsi_domain_id callback returns related fwnode handle
>> of irqdomain for different GSI range.
>>
>> The acpi_gsi_to_irq_fallback will create new mapping for gsi when
>> the mapping of it is not found.
>>
>> Signed-off-by: Jianmin Lv <lvjianmin@loongson.cn>
>> ---
>>   drivers/acpi/bus.c                  |  3 +++
>>   drivers/irqchip/irq-loongarch-cpu.c | 37 +++++++++++++++++++++++++++++++++++++
>>   include/linux/acpi.h                |  1 +
>>   3 files changed, 41 insertions(+)
>>
>> diff --git a/drivers/acpi/bus.c b/drivers/acpi/bus.c
>> index 86fa61a..63fbf00 100644
>> --- a/drivers/acpi/bus.c
>> +++ b/drivers/acpi/bus.c
>> @@ -1145,6 +1145,9 @@ static int __init acpi_bus_init_irq(void)
>>   	case ACPI_IRQ_MODEL_PLATFORM:
>>   		message = "platform specific model";
>>   		break;
>> +	case ACPI_IRQ_MODEL_LPIC:
>> +		message = "LPIC";
>> +		break;
>>   	default:
>>   		pr_info("Unknown interrupt routing model\n");
>>   		return -ENODEV;
>> diff --git a/drivers/irqchip/irq-loongarch-cpu.c b/drivers/irqchip/irq-loongarch-cpu.c
>> index c2f7411..1b241d7 100644
>> --- a/drivers/irqchip/irq-loongarch-cpu.c
>> +++ b/drivers/irqchip/irq-loongarch-cpu.c
>> @@ -15,6 +15,41 @@
>>   
>>   static struct irq_domain *irq_domain;
>>   
>> +static int lpic_gsi_to_irq(u32 gsi)
>> +{
>> +	/* Only pch irqdomain transferring is required for LoongArch. */
>> +	if (gsi >= GSI_MIN_PCH_IRQ && gsi <= GSI_MAX_PCH_IRQ)
>> +		return acpi_register_gsi(NULL, gsi, ACPI_LEVEL_SENSITIVE, ACPI_ACTIVE_HIGH);
>> +	return -1;
> 
> The expected return value on failure is 0 (which indicates that no
> interrupt was mapped). Here, things will break as acpi_gsi_to_irq()
> stores the result as unsigned, and compares the result to 0.
> 

Ok, thanks, I'll change the return value to 0 on failure and change 
return type to unsigned int.


> 	M.
> 

Re: [PATCH V14 02/15] APCI: irq: Add support for multiple GSI domains

[Jianmin Lv]

On 2022/7/7 下午6:16, Marc Zyngier wrote:
> On Sun, 03 Jul 2022 09:45:19 +0100,
> Jianmin Lv <lvjianmin@loongson.cn> wrote:
>>
>> From: Marc Zyngier <maz@kernel.org>
>>
>> In an unfortunate departure from the ACPI spec, the LoongArch
>> architecture split its GSI space across multiple interrupt
>> controllers.
>>
>> In order to be able to reuse the core code and prevent
>> architectures from reinventing an already square wheel, offer
>> the arch code the ability to register a dispatcher function
>> that will return the domain fwnode for a given GSI.
>>
>> The ARM GIC drivers are updated to support this (with a single
>> domain, as intended).
>>
>> Signed-off-by: Marc Zyngier <maz@kernel.org>
>> Cc: Hanjun Guo <guohanjun@huawei.com>
>> Cc: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
>> Signed-off-by: Jianmin Lv <lvjianmin@loongson.cn>
> 
> This patch was reviewed and tested by Hanjun. Why aren't the tags
> included here?
> 

Ok, thanks for your guidance, I'll add them in next version.

> 	M.
> 

Re: [PATCH V14 03/15] ACPI: irq: Allow acpi_gsi_to_irq() to have an arch-specific fallback

[Jianmin Lv]

On 2022/7/7 下午6:14, Marc Zyngier wrote:
> On Sun, 03 Jul 2022 09:45:20 +0100,
> Jianmin Lv <lvjianmin@loongson.cn> wrote:
>>
>> From: Marc Zyngier <maz@kernel.org>
>>
>> It appears that the generic version of acpi_gsi_to_irq() doesn't
>> fallback to establishing a mapping if there is no pre-existing
>> one while the x86 version does.
>>
>> While arm64 seems unaffected by it, LoongArch is relying on the x86
>> behaviour. In an effort to prevent new architectures from reinventing
>> the proverbial wheel, provide an optional callback that the arch code
>> can set to restore the x86 behaviour.
>>
>> Hopefully we can eventually get rid of this in the future once
>> the expected behaviour has been clarified.
>>
>> Reported-by: Jianmin Lv <lvjianmin@loongson.cn>
>> Signed-off-by: Marc Zyngier <maz@kernel.org>
>> Signed-off-by: Jianmin Lv <lvjianmin@loongson.cn>
> 
> Same thing about this patch. It is your duty to collect the tags when
> you repost a series.
>

Ok, thanks, I'll add tags from Hanjun.


> Thanks,
> 
> 	M.
> 

Re: [PATCH V14 01/15] ACPICA: MADT: Add LoongArch APICs support

[Jianmin Lv]

On 2022/7/7 下午6:18, Marc Zyngier wrote:
> On Sun, 03 Jul 2022 09:45:18 +0100,
> Jianmin Lv <lvjianmin@loongson.cn> wrote:
>>
>> From: Huacai Chen <chenhuacai@loongson.cn>
>>
>> LoongArch-specific interrupt controllers (similar to APIC) are added
>> in the next revision of ACPI Specification (current revision is 6.4),
>> which including CORE_PIC (CPUINTC), LIO_PIC (LIOINTC), EIO_PIC (EIOINTC),
>> HT_PIC (HTVECINTC), BIO_PIC (PCHINTC), LPC_PIC (PCHLPC) and MSI_PIC
>> (PCHMSI). This patch add their definition.
>>
>> ACPI changes of LoongArch-specific interrupt controllers have already
>> been approved in the ECRs, and will be public in the next revision of
>> ACPI Specification.
>>
>> Reference: https://mantis.uefi.org/mantis/view.php?id=2203
>> Reference: https://mantis.uefi.org/mantis/view.php?id=2313
> 
> These links are pretty useless without an account on uefi.org (most
> people don't have one, and I certainly don't). Is there a link to
> something *public*?
> 

Sorry for inaccessible links, I take the patch from ACPICA, and the 
links here are intended to provide to ACPI maintainers when the patch 
was submitted to ACPICA.

The ACPI spec 6.5 is not published yet, and I have asked the ACPI spec 
work group, their reply is that I can not share the unpublished spec
draft link to the public, only using for member to review. I think
I can put the ECR(Engineering Change Request) file that described
LoongArch APICs on my github and put the link in the patch.

https://github.com/lvjianmin-loongson/acpica/blob/master/Add%20APIC%20Structures%20for%20Loongarch%20in%20MADT-rev3.pdf

 From mail of the ACPI spec work group , the ACPI spec 6.5 will be 
published in late July or early August.


> Thanks,
> 
> 	M.
> 

Re: [PATCH V14 13/15] irqchip: Add LoongArch CPU interrupt controller support

[Jianmin Lv]

On 2022/7/7 下午8:44, Marc Zyngier wrote:
> On Sun, 03 Jul 2022 09:45:30 +0100,
> Jianmin Lv <lvjianmin@loongson.cn> wrote:
>>
>> From: Huacai Chen <chenhuacai@loongson.cn>
>>
>> LoongArch CPUINTC stands for CSR.ECFG/CSR.ESTAT and related interrupt
>> controller that described in Section 7.4 of "LoongArch Reference Manual,
>> Vol 1". For more information please refer Documentation/loongarch/irq-
>> chip-model.rst.
>>
>> LoongArch CPUINTC has 13 interrupt sources: SWI0~1, HWI0~7, IPI, TI
>> (Timer) and PCOV (PMC). IRQ mappings of HWI0~7 are configurable (can be
>> created from DT/ACPI), but IPI, TI (Timer) and PCOV (PMC) are hardcoded
>> bits, so we define get_xxx_irq() for them.
> 
> I really dislike this practice. Even if these 3 interrupts are well
> known (their hwirqs are set in stone), you should be able to directly
> create the interrupt from the rest of the kernel code.
> 
> All you have to do is to expose the fwnode_handle in the arch code
> (just like you do for other interrupt controllers), retrieve the
> domain and perform the mapping. No need for any extra arch-specific
> API in the irqchip controller.
> 
> It would also be good to mention that this irqchip driver also probes
> the all the rest of the interrupt hierarchy.
> 

Ok, thanks, I'll change it in next version.


> Thanks,
> 
> 	M.
> 

Re: [PATCH V14 10/15] irqchip/loongson-liointc: Add ACPI init support

[Jianmin Lv]

On 2022/7/7 下午6:34, Marc Zyngier wrote:
> On Sun, 03 Jul 2022 09:45:27 +0100,
> Jianmin Lv <lvjianmin@loongson.cn> wrote:
>>
>> From: Huacai Chen <chenhuacai@loongson.cn>
>>
>> LIOINTC stands for "Legacy I/O Interrupts" that described in Section
>> 11.1 of "Loongson 3A5000 Processor Reference Manual". For more
>> information please refer Documentation/loongarch/irq-chip-model.rst.
>>
>> Co-developed-by: Jianmin Lv <lvjianmin@loongson.cn>
>> Signed-off-by: Jianmin Lv <lvjianmin@loongson.cn>
>> Signed-off-by: Huacai Chen <chenhuacai@loongson.cn>
>> ---
>>   arch/loongarch/include/asm/irq.h       |   4 +-
>>   arch/loongarch/kernel/irq.c            |   1 -
>>   drivers/irqchip/irq-loongson-liointc.c | 227 ++++++++++++++++++++++-----------
>>   3 files changed, 154 insertions(+), 78 deletions(-)
>>
>> diff --git a/arch/loongarch/include/asm/irq.h b/arch/loongarch/include/asm/irq.h
>> index 8775dc6..b4c7956 100644
>> --- a/arch/loongarch/include/asm/irq.h
>> +++ b/arch/loongarch/include/asm/irq.h
>> @@ -97,7 +97,7 @@ static inline void eiointc_enable(void)
>>   
>>   struct irq_domain *loongarch_cpu_irq_init(void);
>>   
>> -struct irq_domain *liointc_acpi_init(struct irq_domain *parent,
>> +int liointc_acpi_init(struct irq_domain *parent,
>>   					struct acpi_madt_lio_pic *acpi_liointc);
>>   struct irq_domain *eiointc_acpi_init(struct irq_domain *parent,
>>   					struct acpi_madt_eio_pic *acpi_eiointc);
>> @@ -122,7 +122,7 @@ int pch_pic_acpi_init(struct irq_domain *parent,
>>   extern struct acpi_madt_bio_pic *acpi_pchpic[MAX_IO_PICS];
>>   
>>   extern struct irq_domain *cpu_domain;
>> -extern struct irq_domain *liointc_domain;
>> +extern struct fwnode_handle *liointc_handle;
>>   extern struct fwnode_handle *pch_lpc_handle;
>>   extern struct fwnode_handle *pch_pic_handle[MAX_IO_PICS];
>>   
>> diff --git a/arch/loongarch/kernel/irq.c b/arch/loongarch/kernel/irq.c
>> index ce21281..b04201c 100644
>> --- a/arch/loongarch/kernel/irq.c
>> +++ b/arch/loongarch/kernel/irq.c
>> @@ -26,7 +26,6 @@
>>   EXPORT_PER_CPU_SYMBOL(irq_stat);
>>   
>>   struct irq_domain *cpu_domain;
>> -struct irq_domain *liointc_domain;
>>   
>>   /*
>>    * 'what should we do if we get a hw irq event on an illegal vector'.
>> diff --git a/drivers/irqchip/irq-loongson-liointc.c b/drivers/irqchip/irq-loongson-liointc.c
>> index 8d05d8b..526ade4 100644
>> --- a/drivers/irqchip/irq-loongson-liointc.c
>> +++ b/drivers/irqchip/irq-loongson-liointc.c
>> @@ -23,7 +23,7 @@
>>   #endif
>>   
>>   #define LIOINTC_CHIP_IRQ	32
>> -#define LIOINTC_NUM_PARENT 4
>> +#define LIOINTC_NUM_PARENT	4
>>   #define LIOINTC_NUM_CORES	4
>>   
>>   #define LIOINTC_INTC_CHIP_START	0x20
>> @@ -58,6 +58,8 @@ struct liointc_priv {
>>   	bool				has_lpc_irq_errata;
>>   };
>>   
>> +struct fwnode_handle *liointc_handle;
>> +
>>   static void liointc_chained_handle_irq(struct irq_desc *desc)
>>   {
>>   	struct liointc_handler_data *handler = irq_desc_get_handler_data(desc);
>> @@ -153,97 +155,82 @@ static void liointc_resume(struct irq_chip_generic *gc)
>>   	irq_gc_unlock_irqrestore(gc, flags);
>>   }
>>   
>> -static const char * const parent_names[] = {"int0", "int1", "int2", "int3"};
>> -static const char * const core_reg_names[] = {"isr0", "isr1", "isr2", "isr3"};
>> +static int parent_irq[LIOINTC_NUM_PARENT];
>> +static u32 parent_int_map[LIOINTC_NUM_PARENT];
>> +static const char *const parent_names[] = {"int0", "int1", "int2", "int3"};
>> +static const char *const core_reg_names[] = {"isr0", "isr1", "isr2", "isr3"};
>>   
>> -static void __iomem *liointc_get_reg_byname(struct device_node *node,
>> -						const char *name)
>> +#ifdef CONFIG_ACPI
>> +static int liointc_domain_xlate(struct irq_domain *d, struct device_node *ctrlr,
>> +			     const u32 *intspec, unsigned int intsize,
>> +			     unsigned long *out_hwirq, unsigned int *out_type)
>>   {
>> -	int index = of_property_match_string(node, "reg-names", name);
>> -
>> -	if (index < 0)
>> -		return NULL;
>> -
>> -	return of_iomap(node, index);
>> +	if (WARN_ON(intsize < 1))
>> +		return -EINVAL;
>> +	*out_hwirq = intspec[0] - GSI_MIN_CPU_IRQ;
>> +	*out_type = IRQ_TYPE_NONE;
>> +	return 0;
>>   }
>>   
>> -static int __init liointc_of_init(struct device_node *node,
>> -				  struct device_node *parent)
>> +const struct irq_domain_ops acpi_irq_gc_ops = {
> 
> This should be static.
> 

Ok, thanks, I'll change it.


>> +	.map	= irq_map_generic_chip,
>> +	.unmap  = irq_unmap_generic_chip,
>> +	.xlate	= liointc_domain_xlate,
>> +};
>> +#endif
>> +
>> +static int liointc_init(phys_addr_t addr, unsigned long size, int revision,
>> +		struct fwnode_handle *domain_handle, struct device_node *node)
>>   {
>> +	int i, err;
>> +	void __iomem *base;
>> +	struct irq_chip_type *ct;
>>   	struct irq_chip_generic *gc;
>>   	struct irq_domain *domain;
>> -	struct irq_chip_type *ct;
>>   	struct liointc_priv *priv;
>> -	void __iomem *base;
>> -	u32 of_parent_int_map[LIOINTC_NUM_PARENT];
>> -	int parent_irq[LIOINTC_NUM_PARENT];
>> -	bool have_parent = FALSE;
>> -	int sz, i, err = 0;
>>   
>>   	priv = kzalloc(sizeof(*priv), GFP_KERNEL);
>>   	if (!priv)
>>   		return -ENOMEM;
>>   
>> -	if (of_device_is_compatible(node, "loongson,liointc-2.0")) {
>> -		base = liointc_get_reg_byname(node, "main");
>> -		if (!base) {
>> -			err = -ENODEV;
>> -			goto out_free_priv;
>> -		}
>> +	base = ioremap(addr, size);
>> +	if (!base)
>> +		goto out_free_priv;
>>   
>> -		for (i = 0; i < LIOINTC_NUM_CORES; i++)
>> -			priv->core_isr[i] = liointc_get_reg_byname(node, core_reg_names[i]);
>> -		if (!priv->core_isr[0]) {
>> -			err = -ENODEV;
>> -			goto out_iounmap_base;
>> -		}
>> -	} else {
>> -		base = of_iomap(node, 0);
>> -		if (!base) {
>> -			err = -ENODEV;
>> -			goto out_free_priv;
>> -		}
>> +	for (i = 0; i < LIOINTC_NUM_CORES; i++)
>> +		priv->core_isr[i] = base + LIOINTC_REG_INTC_STATUS;
>>   
>> -		for (i = 0; i < LIOINTC_NUM_CORES; i++)
>> -			priv->core_isr[i] = base + LIOINTC_REG_INTC_STATUS;
>> -	}
>> +	for (i = 0; i < LIOINTC_NUM_PARENT; i++)
>> +		priv->handler[i].parent_int_map = parent_int_map[i];
>>   
>> -	for (i = 0; i < LIOINTC_NUM_PARENT; i++) {
>> -		parent_irq[i] = of_irq_get_byname(node, parent_names[i]);
>> -		if (parent_irq[i] > 0)
>> -			have_parent = TRUE;
>> -	}
>> -	if (!have_parent) {
>> -		err = -ENODEV;
>> -		goto out_iounmap_isr;
>> -	}
>> +	if (revision > 1) {
>> +		for (i = 0; i < LIOINTC_NUM_CORES; i++) {
>> +			int index = of_property_match_string(node,
>> +					"reg-names", core_reg_names[i]);
>>   
>> -	sz = of_property_read_variable_u32_array(node,
>> -						"loongson,parent_int_map",
>> -						&of_parent_int_map[0],
>> -						LIOINTC_NUM_PARENT,
>> -						LIOINTC_NUM_PARENT);
>> -	if (sz < 4) {
>> -		pr_err("loongson-liointc: No parent_int_map\n");
>> -		err = -ENODEV;
>> -		goto out_iounmap_isr;
>> -	}
>> +			if (index < 0)
>> +				return -EINVAL;
>>   
>> -	for (i = 0; i < LIOINTC_NUM_PARENT; i++)
>> -		priv->handler[i].parent_int_map = of_parent_int_map[i];
>> +			priv->core_isr[i] = of_iomap(node, index);
>> +		}
>> +	}
>>   
>>   	/* Setup IRQ domain */
>> -	domain = irq_domain_add_linear(node, 32,
>> +#ifdef CONFIG_ACPI
>> +	domain = irq_domain_create_linear(domain_handle, LIOINTC_CHIP_IRQ,
>> +					&acpi_irq_gc_ops, priv);
>> +#else
>> +	domain = irq_domain_create_linear(domain_handle, LIOINTC_CHIP_IRQ,
>>   					&irq_generic_chip_ops, priv);
>> +#endif
> 
> This feels wrong. The ACPI vs OF decision should be a runtime
> one. Maybe you don't have that issue yet because MIPS is only OF and
> LoongArch only ACPI, but it remains that this should be done
> dynamically.
> 
> Please try to rewrite it as:
> 
> 	if (!acpi_disabled)
> 		[... ACPI stuff ...]
> 	else
> 		[... OF stuff ...]
> 
> This should apply to all other cases where you have similar distinctions.
> 

Ok, thanks, I'll change all the patch series according to your 
suggestion here.


> Thanks,
> 
> 	M.
> 

Re: [PATCH V14 12/15] irqchip: Add Loongson Extended I/O interrupt controller support

[Jianmin Lv]

Hi, bibo

Thanks for your suggestion. Yes, the logic is more complex on multiple 
node, but I think we should support both single and multiple nodes at 
same time as the driver supported both from beginng and has been 
verified on them. Of cause, I'm very happy to discuss issues about the 
driver.:)



On 2022/7/7 下午9:22, maobibo wrote:
> Jianmin,
> 
> Since eiointc driver for loongarch comes from scratch,
> can we add only single node support for eiointc at beginning?
> And then add multiple-node support after the first version merged.
> 
> To be frankly, it is actually hard to understand logic of eiointc
> for multiple-node support. However it is just my suggestion from my point
> and the final code and decision comes from your self.
> 
> regards
> bibo,mao
> 
> 在 2022/7/3 16:45, Jianmin Lv 写道:
>> From: Huacai Chen <chenhuacai@loongson.cn>
>>
>> EIOINTC stands for "Extended I/O Interrupts" that described in Section
>> 11.2 of "Loongson 3A5000 Processor Reference Manual". For more
>> information please refer Documentation/loongarch/irq-chip-model.rst.
>>
>> Loongson-3A5000 has 4 cores per NUMA node, and each NUMA node has an
>> EIOINTC; while Loongson-3C5000 has 16 cores per NUMA node, and each NUMA
>> node has 4 EIOINTCs. In other words, 16 cores of one NUMA node in
>> Loongson-3C5000 are organized in 4 groups, each group connects to an
>> EIOINTC. We call the "group" here as an EIOINTC node, so each EIOINTC
>> node always includes 4 cores (both in Loongson-3A5000 and Loongson-
>> 3C5000).
>>
>> Co-developed-by: Jianmin Lv <lvjianmin@loongson.cn>
>> Signed-off-by: Jianmin Lv <lvjianmin@loongson.cn>
>> Signed-off-by: Huacai Chen <chenhuacai@loongson.cn>
>> ---
>>   arch/loongarch/include/asm/irq.h       |  11 +-
>>   drivers/irqchip/Kconfig                |  10 +
>>   drivers/irqchip/Makefile               |   1 +
>>   drivers/irqchip/irq-loongson-eiointc.c | 413 +++++++++++++++++++++++++++++++++
>>   include/linux/cpuhotplug.h             |   1 +
>>   5 files changed, 426 insertions(+), 10 deletions(-)
>>   create mode 100644 drivers/irqchip/irq-loongson-eiointc.c
>>
>> diff --git a/arch/loongarch/include/asm/irq.h b/arch/loongarch/include/asm/irq.h
>> index a07315a..a826ac4 100644
>> --- a/arch/loongarch/include/asm/irq.h
>> +++ b/arch/loongarch/include/asm/irq.h
>> @@ -87,15 +87,6 @@ struct acpi_vector_group {
>>   extern int find_pch_pic(u32 gsi);
>>   extern int eiointc_get_node(int id);
>>   
>> -static inline void eiointc_enable(void)
>> -{
>> -	uint64_t misc;
>> -
>> -	misc = iocsr_read64(LOONGARCH_IOCSR_MISC_FUNC);
>> -	misc |= IOCSR_MISC_FUNC_EXT_IOI_EN;
>> -	iocsr_write64(misc, LOONGARCH_IOCSR_MISC_FUNC);
>> -}
>> -
>>   struct acpi_madt_lio_pic;
>>   struct acpi_madt_eio_pic;
>>   struct acpi_madt_ht_pic;
>> @@ -107,7 +98,7 @@ static inline void eiointc_enable(void)
>>   
>>   int liointc_acpi_init(struct irq_domain *parent,
>>   					struct acpi_madt_lio_pic *acpi_liointc);
>> -struct irq_domain *eiointc_acpi_init(struct irq_domain *parent,
>> +int eiointc_acpi_init(struct irq_domain *parent,
>>   					struct acpi_madt_eio_pic *acpi_eiointc);
>>   
>>   int htvec_acpi_init(struct irq_domain *parent,
>> diff --git a/drivers/irqchip/Kconfig b/drivers/irqchip/Kconfig
>> index c1d527f..e918579 100644
>> --- a/drivers/irqchip/Kconfig
>> +++ b/drivers/irqchip/Kconfig
>> @@ -555,6 +555,16 @@ config LOONGSON_LIOINTC
>>   	help
>>   	  Support for the Loongson Local I/O Interrupt Controller.
>>   
>> +config LOONGSON_EIOINTC
>> +	bool "Loongson Extend I/O Interrupt Controller"
>> +	depends on LOONGARCH
>> +	depends on MACH_LOONGSON64
>> +	default MACH_LOONGSON64
>> +	select IRQ_DOMAIN_HIERARCHY
>> +	select GENERIC_IRQ_CHIP
>> +	help
>> +	  Support for the Loongson3 Extend I/O Interrupt Vector Controller.
>> +
>>   config LOONGSON_HTPIC
>>   	bool "Loongson3 HyperTransport PIC Controller"
>>   	depends on MACH_LOONGSON64 && MIPS
>> diff --git a/drivers/irqchip/Makefile b/drivers/irqchip/Makefile
>> index 242b8b3..0cfd4f0 100644
>> --- a/drivers/irqchip/Makefile
>> +++ b/drivers/irqchip/Makefile
>> @@ -104,6 +104,7 @@ obj-$(CONFIG_TI_SCI_INTR_IRQCHIP)	+= irq-ti-sci-intr.o
>>   obj-$(CONFIG_TI_SCI_INTA_IRQCHIP)	+= irq-ti-sci-inta.o
>>   obj-$(CONFIG_TI_PRUSS_INTC)		+= irq-pruss-intc.o
>>   obj-$(CONFIG_LOONGSON_LIOINTC)		+= irq-loongson-liointc.o
>> +obj-$(CONFIG_LOONGSON_EIOINTC)		+= irq-loongson-eiointc.o
>>   obj-$(CONFIG_LOONGSON_HTPIC)		+= irq-loongson-htpic.o
>>   obj-$(CONFIG_LOONGSON_HTVEC)		+= irq-loongson-htvec.o
>>   obj-$(CONFIG_LOONGSON_PCH_PIC)		+= irq-loongson-pch-pic.o
>> diff --git a/drivers/irqchip/irq-loongson-eiointc.c b/drivers/irqchip/irq-loongson-eiointc.c
>> new file mode 100644
>> index 0000000..9ddb9ac
>> --- /dev/null
>> +++ b/drivers/irqchip/irq-loongson-eiointc.c
>> @@ -0,0 +1,413 @@
>> +// SPDX-License-Identifier: GPL-2.0
>> +/*
>> + * Loongson Extend I/O Interrupt Controller support
>> + *
>> + * Copyright (C) 2020-2022 Loongson Technology Corporation Limited
>> + */
>> +
>> +#define pr_fmt(fmt) "eiointc: " fmt
>> +
>> +#include <linux/interrupt.h>
>> +#include <linux/irq.h>
>> +#include <linux/irqchip.h>
>> +#include <linux/irqdomain.h>
>> +#include <linux/irqchip/chained_irq.h>
>> +#include <linux/kernel.h>
>> +#include <linux/platform_device.h>
>> +#include <linux/of_address.h>
>> +#include <linux/of_irq.h>
>> +#include <linux/of_platform.h>
>> +
>> +#define EIOINTC_REG_NODEMAP	0x14a0
>> +#define EIOINTC_REG_IPMAP	0x14c0
>> +#define EIOINTC_REG_ENABLE	0x1600
>> +#define EIOINTC_REG_BOUNCE	0x1680
>> +#define EIOINTC_REG_ISR		0x1800
>> +#define EIOINTC_REG_ROUTE	0x1c00
>> +
>> +#define VEC_REG_COUNT		4
>> +#define VEC_COUNT_PER_REG	64
>> +#define VEC_COUNT		(VEC_REG_COUNT * VEC_COUNT_PER_REG)
>> +#define VEC_REG_IDX(irq_id)	((irq_id) / VEC_COUNT_PER_REG)
>> +#define VEC_REG_BIT(irq_id)     ((irq_id) % VEC_COUNT_PER_REG)
>> +#define EIOINTC_ALL_ENABLE	0xffffffff
>> +
>> +#define MAX_EIO_NODES		(NR_CPUS / CORES_PER_EIO_NODE)
>> +
>> +static int nr_pics;
>> +
>> +struct eiointc_priv {
>> +	u32			node;
>> +	nodemask_t		node_map;
>> +	cpumask_t		cpuspan_map;
>> +	struct fwnode_handle	*domain_handle;
>> +	struct irq_domain	*eiointc_domain;
>> +};
>> +
>> +static struct eiointc_priv *eiointc_priv[MAX_IO_PICS];
>> +
>> +static void eiointc_enable(void)
>> +{
>> +	uint64_t misc;
>> +
>> +	misc = iocsr_read64(LOONGARCH_IOCSR_MISC_FUNC);
>> +	misc |= IOCSR_MISC_FUNC_EXT_IOI_EN;
>> +	iocsr_write64(misc, LOONGARCH_IOCSR_MISC_FUNC);
>> +}
>> +
>> +static int cpu_to_eio_node(int cpu)
>> +{
>> +	return cpu_logical_map(cpu) / CORES_PER_EIO_NODE;
>> +}
>> +
>> +static void eiointc_set_irq_route(int pos, unsigned int cpu, unsigned int mnode, nodemask_t *node_map)
>> +{
>> +	int i, node, cpu_node, route_node;
>> +	unsigned char coremap[MAX_EIO_NODES];
>> +	uint32_t pos_off, data, data_byte, data_mask;
>> +
>> +	pos_off = pos & ~3;
>> +	data_byte = pos & 3;
>> +	data_mask = ~BIT_MASK(data_byte) & 0xf;
>> +
>> +	memset(coremap, 0, sizeof(unsigned char) * MAX_EIO_NODES);
>> +
>> +	/* Calculate node and coremap of target irq */
>> +	cpu_node = cpu_logical_map(cpu) / CORES_PER_EIO_NODE;
>> +	coremap[cpu_node] |= BIT(cpu_logical_map(cpu) % CORES_PER_EIO_NODE);
>> +
>> +	for_each_online_cpu(i) {
>> +		node = cpu_to_eio_node(i);
>> +		if (!node_isset(node, *node_map))
>> +			continue;
>> +
>> +		/* EIO node 0 is in charge of inter-node interrupt dispatch */
>> +		route_node = (node == mnode) ? cpu_node : node;
>> +		data = ((coremap[node] | (route_node << 4)) << (data_byte * 8));
>> +		csr_any_send(EIOINTC_REG_ROUTE + pos_off, data, data_mask, node * CORES_PER_EIO_NODE);
>> +	}
>> +}
>> +
>> +static DEFINE_RAW_SPINLOCK(affinity_lock);
>> +
>> +static int eiointc_set_irq_affinity(struct irq_data *d, const struct cpumask *affinity, bool force)
>> +{
>> +	unsigned int cpu;
>> +	unsigned long flags;
>> +	uint32_t vector, regaddr;
>> +	struct cpumask intersect_affinity;
>> +	struct eiointc_priv *priv = d->domain->host_data;
>> +
>> +	if (!IS_ENABLED(CONFIG_SMP))
>> +		return -EPERM;
>> +
>> +	raw_spin_lock_irqsave(&affinity_lock, flags);
>> +
>> +	cpumask_and(&intersect_affinity, affinity, cpu_online_mask);
>> +	cpumask_and(&intersect_affinity, &intersect_affinity, &priv->cpuspan_map);
>> +
>> +	if (cpumask_empty(&intersect_affinity)) {
>> +		raw_spin_unlock_irqrestore(&affinity_lock, flags);
>> +		return -EINVAL;
>> +	}
>> +	cpu = cpumask_first(&intersect_affinity);
>> +
>> +	if (!d->parent_data)
>> +		vector = d->hwirq;
>> +	else
>> +		vector = d->parent_data->hwirq;
>> +
>> +	regaddr = EIOINTC_REG_ENABLE + ((vector >> 5) << 2);
>> +
>> +	/* Mask target vector */
>> +	csr_any_send(regaddr, EIOINTC_ALL_ENABLE & (~BIT(vector & 0x1F)), 0x0, 0);
>> +	/* Set route for target vector */
>> +	eiointc_set_irq_route(vector, cpu, priv->node, &priv->node_map);
>> +	/* Unmask target vector */
>> +	csr_any_send(regaddr, EIOINTC_ALL_ENABLE, 0x0, 0);
>> +
>> +	irq_data_update_effective_affinity(d, cpumask_of(cpu));
>> +
>> +	raw_spin_unlock_irqrestore(&affinity_lock, flags);
>> +
>> +	return IRQ_SET_MASK_OK;
>> +}
>> +
>> +static int eiointc_index(int node)
>> +{
>> +	int i;
>> +
>> +	for (i = 0; i < nr_pics; i++) {
>> +		if (node_isset(node, eiointc_priv[i]->node_map))
>> +			return i;
>> +	}
>> +
>> +	return -1;
>> +}
>> +
>> +static int eiointc_router_init(unsigned int cpu)
>> +{
>> +	int i, bit;
>> +	uint32_t data;
>> +	uint32_t node = cpu_to_eio_node(cpu);
>> +	uint32_t index = eiointc_index(node);
>> +
>> +	if (index < 0) {
>> +		pr_err("Error: invalid nodemap!\n");
>> +		return -1;
>> +	}
>> +
>> +	if ((cpu_logical_map(cpu) % CORES_PER_EIO_NODE) == 0) {
>> +		eiointc_enable();
>> +
>> +		for (i = 0; i < VEC_COUNT / 32; i++) {
>> +			data = (((1 << (i * 2 + 1)) << 16) | (1 << (i * 2)));
>> +			iocsr_write32(data, EIOINTC_REG_NODEMAP + i * 4);
>> +		}
>> +
>> +		for (i = 0; i < VEC_COUNT / 32 / 4; i++) {
>> +			bit = BIT(1 + index); /* Route to IP[1 + index] */
>> +			data = bit | (bit << 8) | (bit << 16) | (bit << 24);
>> +			iocsr_write32(data, EIOINTC_REG_IPMAP + i * 4);
>> +		}
>> +
>> +		for (i = 0; i < VEC_COUNT / 4; i++) {
>> +			/* Route to Node-0 Core-0 */
>> +			if (index == 0)
>> +				bit = BIT(cpu_logical_map(0));
>> +			else
>> +				bit = (eiointc_priv[index]->node << 4) | 1;
>> +
>> +			data = bit | (bit << 8) | (bit << 16) | (bit << 24);
>> +			iocsr_write32(data, EIOINTC_REG_ROUTE + i * 4);
>> +		}
>> +
>> +		for (i = 0; i < VEC_COUNT / 32; i++) {
>> +			data = 0xffffffff;
>> +			iocsr_write32(data, EIOINTC_REG_ENABLE + i * 4);
>> +			iocsr_write32(data, EIOINTC_REG_BOUNCE + i * 4);
>> +		}
>> +	}
>> +
>> +	return 0;
>> +}
>> +
>> +static void eiointc_irq_dispatch(struct irq_desc *desc)
>> +{
>> +	int i;
>> +	u64 pending;
>> +	bool handled = false;
>> +	struct irq_chip *chip = irq_desc_get_chip(desc);
>> +	struct eiointc_priv *priv = irq_desc_get_handler_data(desc);
>> +
>> +	chained_irq_enter(chip, desc);
>> +
>> +	for (i = 0; i < VEC_REG_COUNT; i++) {
>> +		pending = iocsr_read64(EIOINTC_REG_ISR + (i << 3));
>> +		iocsr_write64(pending, EIOINTC_REG_ISR + (i << 3));
>> +		while (pending) {
>> +			int bit = __ffs(pending);
>> +			int irq = bit + VEC_COUNT_PER_REG * i;
>> +
>> +			generic_handle_domain_irq(priv->eiointc_domain, irq);
>> +			pending &= ~BIT(bit);
>> +			handled = true;
>> +		}
>> +	}
>> +
>> +	if (!handled)
>> +		spurious_interrupt();
>> +
>> +	chained_irq_exit(chip, desc);
>> +}
>> +
>> +static void eiointc_ack_irq(struct irq_data *d)
>> +{
>> +	if (d->parent_data)
>> +		irq_chip_ack_parent(d);
>> +}
>> +
>> +static void eiointc_mask_irq(struct irq_data *d)
>> +{
>> +	if (d->parent_data)
>> +		irq_chip_mask_parent(d);
>> +}
>> +
>> +static void eiointc_unmask_irq(struct irq_data *d)
>> +{
>> +	if (d->parent_data)
>> +		irq_chip_unmask_parent(d);
>> +}
>> +
>> +static struct irq_chip eiointc_irq_chip = {
>> +	.name			= "EIOINTC",
>> +	.irq_ack		= eiointc_ack_irq,
>> +	.irq_mask		= eiointc_mask_irq,
>> +	.irq_unmask		= eiointc_unmask_irq,
>> +	.irq_set_affinity	= eiointc_set_irq_affinity,
>> +};
>> +
>> +static int eiointc_domain_alloc(struct irq_domain *domain, unsigned int virq,
>> +				unsigned int nr_irqs, void *arg)
>> +{
>> +	int ret;
>> +	unsigned int i, type;
>> +	unsigned long hwirq = 0;
>> +	struct eiointc *priv = domain->host_data;
>> +
>> +	ret = irq_domain_translate_onecell(domain, arg, &hwirq, &type);
>> +	if (ret)
>> +		return ret;
>> +
>> +	for (i = 0; i < nr_irqs; i++) {
>> +		irq_domain_set_info(domain, virq + i, hwirq + i, &eiointc_irq_chip,
>> +					priv, handle_edge_irq, NULL, NULL);
>> +	}
>> +
>> +	return 0;
>> +}
>> +
>> +static void eiointc_domain_free(struct irq_domain *domain, unsigned int virq,
>> +				unsigned int nr_irqs)
>> +{
>> +	int i;
>> +
>> +	for (i = 0; i < nr_irqs; i++) {
>> +		struct irq_data *d = irq_domain_get_irq_data(domain, virq + i);
>> +
>> +		irq_set_handler(virq + i, NULL);
>> +		irq_domain_reset_irq_data(d);
>> +	}
>> +}
>> +
>> +static const struct irq_domain_ops eiointc_domain_ops = {
>> +	.translate	= irq_domain_translate_onecell,
>> +	.alloc		= eiointc_domain_alloc,
>> +	.free		= eiointc_domain_free,
>> +};
>> +
>> +static void acpi_set_vec_parent(int node, struct irq_domain *parent, struct acpi_vector_group *vec_group)
>> +{
>> +	int i;
>> +
>> +	if (cpu_has_flatmode)
>> +		node = cpu_to_node(node * CORES_PER_EIO_NODE);
>> +
>> +	for (i = 0; i < MAX_IO_PICS; i++) {
>> +		if (node == vec_group[i].node) {
>> +			vec_group[i].parent = parent;
>> +			return;
>> +		}
>> +	}
>> +}
>> +
>> +struct irq_domain *acpi_get_vec_parent(int node, struct acpi_vector_group *vec_group)
>> +{
>> +	int i;
>> +
>> +	for (i = 0; i < MAX_IO_PICS; i++) {
>> +		if (node == vec_group[i].node)
>> +			return vec_group[i].parent;
>> +	}
>> +	return NULL;
>> +}
>> +
>> +static int __init
>> +pch_pic_parse_madt(union acpi_subtable_headers *header,
>> +		       const unsigned long end)
>> +{
>> +	struct acpi_madt_bio_pic *pchpic_entry = (struct acpi_madt_bio_pic *)header;
>> +	unsigned int node = (pchpic_entry->address >> 44) & 0xf;
>> +	struct irq_domain *parent = acpi_get_vec_parent(node, pch_group);
>> +
>> +	if (parent)
>> +		return pch_pic_acpi_init(parent, pchpic_entry);
>> +
>> +	return -EINVAL;
>> +}
>> +
>> +static int __init
>> +pch_msi_parse_madt(union acpi_subtable_headers *header,
>> +		       const unsigned long end)
>> +{
>> +	struct acpi_madt_msi_pic *pchmsi_entry = (struct acpi_madt_msi_pic *)header;
>> +	struct irq_domain *parent = acpi_get_vec_parent(eiointc_priv[nr_pics - 1]->node, msi_group);
>> +
>> +	if (parent)
>> +		return pch_msi_acpi_init(parent, pchmsi_entry);
>> +
>> +	return -EINVAL;
>> +}
>> +
>> +static int __init acpi_cascade_irqdomain_init(void)
>> +{
>> +	acpi_table_parse_madt(ACPI_MADT_TYPE_BIO_PIC,
>> +			      pch_pic_parse_madt, 0);
>> +	acpi_table_parse_madt(ACPI_MADT_TYPE_MSI_PIC,
>> +			      pch_msi_parse_madt, 1);
>> +	return 0;
>> +}
>> +
>> +int __init eiointc_acpi_init(struct irq_domain *parent,
>> +				     struct acpi_madt_eio_pic *acpi_eiointc)
>> +{
>> +	int i, parent_irq;
>> +	unsigned long node_map;
>> +	struct eiointc_priv *priv;
>> +
>> +	if (!acpi_eiointc)
>> +		return -EINVAL;
>> +
>> +	priv = kzalloc(sizeof(*priv), GFP_KERNEL);
>> +	if (!priv)
>> +		return -ENOMEM;
>> +
>> +	priv->domain_handle = irq_domain_alloc_fwnode((phys_addr_t *)acpi_eiointc);
>> +	if (!priv->domain_handle) {
>> +		pr_err("Unable to allocate domain handle\n");
>> +		goto out_free_priv;
>> +	}
>> +
>> +	priv->node = acpi_eiointc->node;
>> +	node_map = acpi_eiointc->node_map ? : -1ULL;
>> +
>> +	for_each_possible_cpu(i) {
>> +		if (node_map & (1ULL << cpu_to_eio_node(i))) {
>> +			node_set(cpu_to_eio_node(i), priv->node_map);
>> +			cpumask_or(&priv->cpuspan_map, &priv->cpuspan_map, cpumask_of(i));
>> +		}
>> +	}
>> +
>> +	/* Setup IRQ domain */
>> +	priv->eiointc_domain = irq_domain_create_linear(priv->domain_handle, VEC_COUNT,
>> +					&eiointc_domain_ops, priv);
>> +	if (!priv->eiointc_domain) {
>> +		pr_err("loongson-eiointc: cannot add IRQ domain\n");
>> +		goto out_free_handle;
>> +	}
>> +
>> +	eiointc_priv[nr_pics++] = priv;
>> +
>> +	eiointc_router_init(0);
>> +
>> +	parent_irq = irq_create_mapping(parent, acpi_eiointc->cascade);
>> +	irq_set_chained_handler_and_data(parent_irq, eiointc_irq_dispatch, priv);
>> +
>> +	cpuhp_setup_state_nocalls(CPUHP_AP_IRQ_LOONGARCH_STARTING,
>> +				  "irqchip/loongarch/intc:starting",
>> +				  eiointc_router_init, NULL);
>> +
>> +	acpi_set_vec_parent(acpi_eiointc->node, priv->eiointc_domain, pch_group);
>> +	acpi_set_vec_parent(acpi_eiointc->node, priv->eiointc_domain, msi_group);
>> +	acpi_cascade_irqdomain_init();
>> +
>> +	return 0;
>> +
>> +out_free_handle:
>> +	irq_domain_free_fwnode(priv->domain_handle);
>> +	priv->domain_handle = NULL;
>> +out_free_priv:
>> +	kfree(priv);
>> +
>> +	return -ENOMEM;
>> +}
>> diff --git a/include/linux/cpuhotplug.h b/include/linux/cpuhotplug.h
>> index 19f0dbf..de662f3 100644
>> --- a/include/linux/cpuhotplug.h
>> +++ b/include/linux/cpuhotplug.h
>> @@ -151,6 +151,7 @@ enum cpuhp_state {
>>   	CPUHP_AP_IRQ_BCM2836_STARTING,
>>   	CPUHP_AP_IRQ_MIPS_GIC_STARTING,
>>   	CPUHP_AP_IRQ_RISCV_STARTING,
>> +	CPUHP_AP_IRQ_LOONGARCH_STARTING,
>>   	CPUHP_AP_IRQ_SIFIVE_PLIC_STARTING,
>>   	CPUHP_AP_ARM_MVEBU_COHERENCY,
>>   	CPUHP_AP_MICROCODE_LOADER,

RE: [PATCH V14 00/15] irqchip: Add LoongArch-related irqchip drivers

[Moore, Robert]

We can't take any patches that are unreleased in the ACPI specification (legal reasons). Hopefully this will happen this month.

-----Original Message-----
From: Marc Zyngier <maz@kernel.org> 
Sent: Thursday, July 07, 2022 5:52 AM
To: Jianmin Lv <lvjianmin@loongson.cn>; Rafael J Wysocki <rafael@kernel.org>; Moore, Robert <robert.moore@intel.com>
Cc: Thomas Gleixner <tglx@linutronix.de>; linux-kernel@vger.kernel.org; Hanjun Guo <guohanjun@huawei.com>; Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>; Jiaxun Yang <jiaxun.yang@flygoat.com>; Huacai Chen <chenhuacai@loongson.cn>
Subject: Re: [PATCH V14 00/15] irqchip: Add LoongArch-related irqchip drivers

+ Rafael, Robert

On Sun, 03 Jul 2022 09:45:17 +0100,
Jianmin Lv <lvjianmin@loongson.cn> wrote:
> 
> LoongArch is a new RISC ISA, which is a bit like MIPS or RISC-V.
> LoongArch includes a reduced 32-bit version (LA32R), a standard 32-bit 
> version (LA32S) and a 64-bit version (LA64). LoongArch use ACPI as its 
> boot protocol LoongArch-specific interrupt controllers (similar to 
> APIC) are already added in the ACPI Specification 6.5(which may be 
> published in early June this year and the board is reviewing the draft).

Can the ACPI/ACPICA maintainers eyeball patch #1 in this series[1]? It adds some new, yet unpublished ACPI MADT updates, and I need an Ack on that before considering taking this series.

Patches 2 and 3 could also do with an Ack from the ACPI maintainers (though Hanjun did review an earlier version).

Thanks,
	M.

[1] https://lore.kernel.org/r/1656837932-18257-2-git-send-email-lvjianmin@loongson.cn

--
Without deviation from the norm, progress is not possible.

Re: [PATCH V14 12/15] irqchip: Add Loongson Extended I/O interrupt controller support

[Jianmin Lv]

On 2022/7/7 下午8:30, Marc Zyngier wrote:
> On Sun, 03 Jul 2022 09:45:29 +0100,
> Jianmin Lv <lvjianmin@loongson.cn> wrote:
>>
>> From: Huacai Chen <chenhuacai@loongson.cn>
>>
>> EIOINTC stands for "Extended I/O Interrupts" that described in Section
>> 11.2 of "Loongson 3A5000 Processor Reference Manual". For more
>> information please refer Documentation/loongarch/irq-chip-model.rst.
>>
>> Loongson-3A5000 has 4 cores per NUMA node, and each NUMA node has an
>> EIOINTC; while Loongson-3C5000 has 16 cores per NUMA node, and each NUMA
>> node has 4 EIOINTCs. In other words, 16 cores of one NUMA node in
>> Loongson-3C5000 are organized in 4 groups, each group connects to an
>> EIOINTC. We call the "group" here as an EIOINTC node, so each EIOINTC
>> node always includes 4 cores (both in Loongson-3A5000 and Loongson-
>> 3C5000).
>>
>> Co-developed-by: Jianmin Lv <lvjianmin@loongson.cn>
>> Signed-off-by: Jianmin Lv <lvjianmin@loongson.cn>
>> Signed-off-by: Huacai Chen <chenhuacai@loongson.cn>
>> ---
>>   arch/loongarch/include/asm/irq.h       |  11 +-
>>   drivers/irqchip/Kconfig                |  10 +
>>   drivers/irqchip/Makefile               |   1 +
>>   drivers/irqchip/irq-loongson-eiointc.c | 413 +++++++++++++++++++++++++++++++++
>>   include/linux/cpuhotplug.h             |   1 +
>>   5 files changed, 426 insertions(+), 10 deletions(-)
>>   create mode 100644 drivers/irqchip/irq-loongson-eiointc.c
>>
>> diff --git a/arch/loongarch/include/asm/irq.h b/arch/loongarch/include/asm/irq.h
>> index a07315a..a826ac4 100644
>> --- a/arch/loongarch/include/asm/irq.h
>> +++ b/arch/loongarch/include/asm/irq.h
>> @@ -87,15 +87,6 @@ struct acpi_vector_group {
>>   extern int find_pch_pic(u32 gsi);
>>   extern int eiointc_get_node(int id);
>>   
>> -static inline void eiointc_enable(void)
>> -{
>> -	uint64_t misc;
>> -
>> -	misc = iocsr_read64(LOONGARCH_IOCSR_MISC_FUNC);
>> -	misc |= IOCSR_MISC_FUNC_EXT_IOI_EN;
>> -	iocsr_write64(misc, LOONGARCH_IOCSR_MISC_FUNC);
>> -}
>> -
>>   struct acpi_madt_lio_pic;
>>   struct acpi_madt_eio_pic;
>>   struct acpi_madt_ht_pic;
>> @@ -107,7 +98,7 @@ static inline void eiointc_enable(void)
>>   
>>   int liointc_acpi_init(struct irq_domain *parent,
>>   					struct acpi_madt_lio_pic *acpi_liointc);
>> -struct irq_domain *eiointc_acpi_init(struct irq_domain *parent,
>> +int eiointc_acpi_init(struct irq_domain *parent,
>>   					struct acpi_madt_eio_pic *acpi_eiointc);
>>   
>>   int htvec_acpi_init(struct irq_domain *parent,
>> diff --git a/drivers/irqchip/Kconfig b/drivers/irqchip/Kconfig
>> index c1d527f..e918579 100644
>> --- a/drivers/irqchip/Kconfig
>> +++ b/drivers/irqchip/Kconfig
>> @@ -555,6 +555,16 @@ config LOONGSON_LIOINTC
>>   	help
>>   	  Support for the Loongson Local I/O Interrupt Controller.
>>   
>> +config LOONGSON_EIOINTC
>> +	bool "Loongson Extend I/O Interrupt Controller"
>> +	depends on LOONGARCH
>> +	depends on MACH_LOONGSON64
>> +	default MACH_LOONGSON64
>> +	select IRQ_DOMAIN_HIERARCHY
>> +	select GENERIC_IRQ_CHIP
>> +	help
>> +	  Support for the Loongson3 Extend I/O Interrupt Vector Controller.
>> +
>>   config LOONGSON_HTPIC
>>   	bool "Loongson3 HyperTransport PIC Controller"
>>   	depends on MACH_LOONGSON64 && MIPS
>> diff --git a/drivers/irqchip/Makefile b/drivers/irqchip/Makefile
>> index 242b8b3..0cfd4f0 100644
>> --- a/drivers/irqchip/Makefile
>> +++ b/drivers/irqchip/Makefile
>> @@ -104,6 +104,7 @@ obj-$(CONFIG_TI_SCI_INTR_IRQCHIP)	+= irq-ti-sci-intr.o
>>   obj-$(CONFIG_TI_SCI_INTA_IRQCHIP)	+= irq-ti-sci-inta.o
>>   obj-$(CONFIG_TI_PRUSS_INTC)		+= irq-pruss-intc.o
>>   obj-$(CONFIG_LOONGSON_LIOINTC)		+= irq-loongson-liointc.o
>> +obj-$(CONFIG_LOONGSON_EIOINTC)		+= irq-loongson-eiointc.o
>>   obj-$(CONFIG_LOONGSON_HTPIC)		+= irq-loongson-htpic.o
>>   obj-$(CONFIG_LOONGSON_HTVEC)		+= irq-loongson-htvec.o
>>   obj-$(CONFIG_LOONGSON_PCH_PIC)		+= irq-loongson-pch-pic.o
>> diff --git a/drivers/irqchip/irq-loongson-eiointc.c b/drivers/irqchip/irq-loongson-eiointc.c
>> new file mode 100644
>> index 0000000..9ddb9ac
>> --- /dev/null
>> +++ b/drivers/irqchip/irq-loongson-eiointc.c
>> @@ -0,0 +1,413 @@
>> +// SPDX-License-Identifier: GPL-2.0
>> +/*
>> + * Loongson Extend I/O Interrupt Controller support
>> + *
>> + * Copyright (C) 2020-2022 Loongson Technology Corporation Limited
>> + */
>> +
>> +#define pr_fmt(fmt) "eiointc: " fmt
>> +
>> +#include <linux/interrupt.h>
>> +#include <linux/irq.h>
>> +#include <linux/irqchip.h>
>> +#include <linux/irqdomain.h>
>> +#include <linux/irqchip/chained_irq.h>
>> +#include <linux/kernel.h>
>> +#include <linux/platform_device.h>
>> +#include <linux/of_address.h>
>> +#include <linux/of_irq.h>
>> +#include <linux/of_platform.h>
>> +
>> +#define EIOINTC_REG_NODEMAP	0x14a0
>> +#define EIOINTC_REG_IPMAP	0x14c0
>> +#define EIOINTC_REG_ENABLE	0x1600
>> +#define EIOINTC_REG_BOUNCE	0x1680
>> +#define EIOINTC_REG_ISR		0x1800
>> +#define EIOINTC_REG_ROUTE	0x1c00
>> +
>> +#define VEC_REG_COUNT		4
>> +#define VEC_COUNT_PER_REG	64
>> +#define VEC_COUNT		(VEC_REG_COUNT * VEC_COUNT_PER_REG)
>> +#define VEC_REG_IDX(irq_id)	((irq_id) / VEC_COUNT_PER_REG)
>> +#define VEC_REG_BIT(irq_id)     ((irq_id) % VEC_COUNT_PER_REG)
>> +#define EIOINTC_ALL_ENABLE	0xffffffff
>> +
>> +#define MAX_EIO_NODES		(NR_CPUS / CORES_PER_EIO_NODE)
>> +
>> +static int nr_pics;
>> +
>> +struct eiointc_priv {
>> +	u32			node;
>> +	nodemask_t		node_map;
>> +	cpumask_t		cpuspan_map;
>> +	struct fwnode_handle	*domain_handle;
>> +	struct irq_domain	*eiointc_domain;
>> +};
>> +
>> +static struct eiointc_priv *eiointc_priv[MAX_IO_PICS];
>> +
>> +static void eiointc_enable(void)
>> +{
>> +	uint64_t misc;
>> +
>> +	misc = iocsr_read64(LOONGARCH_IOCSR_MISC_FUNC);
>> +	misc |= IOCSR_MISC_FUNC_EXT_IOI_EN;
>> +	iocsr_write64(misc, LOONGARCH_IOCSR_MISC_FUNC);
>> +}
>> +
>> +static int cpu_to_eio_node(int cpu)
>> +{
>> +	return cpu_logical_map(cpu) / CORES_PER_EIO_NODE;
>> +}
>> +
>> +static void eiointc_set_irq_route(int pos, unsigned int cpu, unsigned int mnode, nodemask_t *node_map)
>> +{
>> +	int i, node, cpu_node, route_node;
>> +	unsigned char coremap[MAX_EIO_NODES];
>> +	uint32_t pos_off, data, data_byte, data_mask;
>> +
>> +	pos_off = pos & ~3;
>> +	data_byte = pos & 3;
>> +	data_mask = ~BIT_MASK(data_byte) & 0xf;
>> +
>> +	memset(coremap, 0, sizeof(unsigned char) * MAX_EIO_NODES);
> 
> This would be better written as an initialisation of the array:
> 
> 	unsigned char coremap[MAX_EIO_NODES] = { };
> 
>> +
>> +	/* Calculate node and coremap of target irq */
>> +	cpu_node = cpu_logical_map(cpu) / CORES_PER_EIO_NODE;
>> +	coremap[cpu_node] |= BIT(cpu_logical_map(cpu) % CORES_PER_EIO_NODE);
>> +
>> +	for_each_online_cpu(i) {
>> +		node = cpu_to_eio_node(i);
>> +		if (!node_isset(node, *node_map))
>> +			continue;
>> +
>> +		/* EIO node 0 is in charge of inter-node interrupt dispatch */
>> +		route_node = (node == mnode) ? cpu_node : node;
>> +		data = ((coremap[node] | (route_node << 4)) << (data_byte * 8));
>> +		csr_any_send(EIOINTC_REG_ROUTE + pos_off, data, data_mask, node * CORES_PER_EIO_NODE);
>> +	}
> 
> But the coremap array doesn't make much sense. You only initialise
> *one* byte in it, and the rest is always 0. Either it is completely
> irrelevant and you should get rid of it, or this is buggy and you
> should fix it.
> 

Yes, thanks, Marc, it's confused code here because the definition of 
coremap was no changed when adjust the function previously, a byte typed 
variable is enough.


>> +}
>> +
>> +static DEFINE_RAW_SPINLOCK(affinity_lock);
>> +
>> +static int eiointc_set_irq_affinity(struct irq_data *d, const struct cpumask *affinity, bool force)
>> +{
>> +	unsigned int cpu;
>> +	unsigned long flags;
>> +	uint32_t vector, regaddr;
>> +	struct cpumask intersect_affinity;
>> +	struct eiointc_priv *priv = d->domain->host_data;
>> +
>> +	if (!IS_ENABLED(CONFIG_SMP))
>> +		return -EPERM;
> 
> Is it even legal to build this architecture with !SMP?
> 


It's legal in our internal repo for single core CPU, but now it's not 
allowed to build with !SMP, I'll remove it in next version, and take it 
into account when supporting single core CPU in future.


>> +
>> +	raw_spin_lock_irqsave(&affinity_lock, flags);
>> +
>> +	cpumask_and(&intersect_affinity, affinity, cpu_online_mask);
>> +	cpumask_and(&intersect_affinity, &intersect_affinity, &priv->cpuspan_map);
>> +
>> +	if (cpumask_empty(&intersect_affinity)) {
>> +		raw_spin_unlock_irqrestore(&affinity_lock, flags);
>> +		return -EINVAL;
>> +	}
>> +	cpu = cpumask_first(&intersect_affinity);
>> +
>> +	if (!d->parent_data)
>> +		vector = d->hwirq;
>> +	else
>> +		vector = d->parent_data->hwirq;
>> +
>> +	regaddr = EIOINTC_REG_ENABLE + ((vector >> 5) << 2);
>> +
>> +	/* Mask target vector */
>> +	csr_any_send(regaddr, EIOINTC_ALL_ENABLE & (~BIT(vector & 0x1F)), 0x0, 0);
>> +	/* Set route for target vector */
>> +	eiointc_set_irq_route(vector, cpu, priv->node, &priv->node_map);
>> +	/* Unmask target vector */
>> +	csr_any_send(regaddr, EIOINTC_ALL_ENABLE, 0x0, 0);
>> +
>> +	irq_data_update_effective_affinity(d, cpumask_of(cpu));
>> +
>> +	raw_spin_unlock_irqrestore(&affinity_lock, flags);
>> +
>> +	return IRQ_SET_MASK_OK;
>> +}
>> +
>> +static int eiointc_index(int node)
>> +{
>> +	int i;
>> +
>> +	for (i = 0; i < nr_pics; i++) {
>> +		if (node_isset(node, eiointc_priv[i]->node_map))
>> +			return i;
>> +	}
>> +
>> +	return -1;
>> +}
>> +
>> +static int eiointc_router_init(unsigned int cpu)
>> +{
>> +	int i, bit;
>> +	uint32_t data;
>> +	uint32_t node = cpu_to_eio_node(cpu);
>> +	uint32_t index = eiointc_index(node);
>> +
>> +	if (index < 0) {
>> +		pr_err("Error: invalid nodemap!\n");
>> +		return -1;
>> +	}
>> +
>> +	if ((cpu_logical_map(cpu) % CORES_PER_EIO_NODE) == 0) {
>> +		eiointc_enable();
>> +
>> +		for (i = 0; i < VEC_COUNT / 32; i++) {
>> +			data = (((1 << (i * 2 + 1)) << 16) | (1 << (i * 2)));
>> +			iocsr_write32(data, EIOINTC_REG_NODEMAP + i * 4);
>> +		}
>> +
>> +		for (i = 0; i < VEC_COUNT / 32 / 4; i++) {
>> +			bit = BIT(1 + index); /* Route to IP[1 + index] */
>> +			data = bit | (bit << 8) | (bit << 16) | (bit << 24);
>> +			iocsr_write32(data, EIOINTC_REG_IPMAP + i * 4);
>> +		}
>> +
>> +		for (i = 0; i < VEC_COUNT / 4; i++) {
>> +			/* Route to Node-0 Core-0 */
>> +			if (index == 0)
>> +				bit = BIT(cpu_logical_map(0));
>> +			else
>> +				bit = (eiointc_priv[index]->node << 4) | 1;
>> +
>> +			data = bit | (bit << 8) | (bit << 16) | (bit << 24);
>> +			iocsr_write32(data, EIOINTC_REG_ROUTE + i * 4);
>> +		}
>> +
>> +		for (i = 0; i < VEC_COUNT / 32; i++) {
>> +			data = 0xffffffff;
>> +			iocsr_write32(data, EIOINTC_REG_ENABLE + i * 4);
>> +			iocsr_write32(data, EIOINTC_REG_BOUNCE + i * 4);
>> +		}
>> +	}
>> +
>> +	return 0;
>> +}
>> +
>> +static void eiointc_irq_dispatch(struct irq_desc *desc)
>> +{
>> +	int i;
>> +	u64 pending;
>> +	bool handled = false;
>> +	struct irq_chip *chip = irq_desc_get_chip(desc);
>> +	struct eiointc_priv *priv = irq_desc_get_handler_data(desc);
>> +
>> +	chained_irq_enter(chip, desc);
>> +
>> +	for (i = 0; i < VEC_REG_COUNT; i++) {
>> +		pending = iocsr_read64(EIOINTC_REG_ISR + (i << 3));
>> +		iocsr_write64(pending, EIOINTC_REG_ISR + (i << 3));
>> +		while (pending) {
>> +			int bit = __ffs(pending);
>> +			int irq = bit + VEC_COUNT_PER_REG * i;
>> +
>> +			generic_handle_domain_irq(priv->eiointc_domain, irq);
>> +			pending &= ~BIT(bit);
>> +			handled = true;
>> +		}
>> +	}
>> +
>> +	if (!handled)
>> +		spurious_interrupt();
>> +
>> +	chained_irq_exit(chip, desc);
>> +}
>> +
>> +static void eiointc_ack_irq(struct irq_data *d)
>> +{
>> +	if (d->parent_data)
>> +		irq_chip_ack_parent(d);
>> +}
>> +
>> +static void eiointc_mask_irq(struct irq_data *d)
>> +{
>> +	if (d->parent_data)
>> +		irq_chip_mask_parent(d);
>> +}
>> +
>> +static void eiointc_unmask_irq(struct irq_data *d)
>> +{
>> +	if (d->parent_data)
>> +		irq_chip_unmask_parent(d);
>> +}
> 
> It is pretty unclear to me under what circumstances some interrupts
> have a parent, and some don't.
> 

t seems that parent_data here is always NULL because:

- 'd' passed in is irq_data of eiointc when calling the eiointc 
irqchip's ops function.
- eiointc has no parent domain.

The code(should be cleaned) is here because previous incorrect use to 
eiointc_set_irq_affinity in resume code(which has been cleaned from the 
patch). I'll clean it in next version.

So, we have noting to do here, leaving some empty unmask/mask.


>> +
>> +static struct irq_chip eiointc_irq_chip = {
>> +	.name			= "EIOINTC",
>> +	.irq_ack		= eiointc_ack_irq,
>> +	.irq_mask		= eiointc_mask_irq,
>> +	.irq_unmask		= eiointc_unmask_irq,
>> +	.irq_set_affinity	= eiointc_set_irq_affinity,
> 
> Under what circumstances can an interrupt be moved to another CPU?
> Given that you have an EIO per 4-cpu group, I can see how the EIO can
> move the affinity. But can you move an interrupt to a CPU belonging to
> another EOIO? If you can, is any *other* interrupt affected by the
> affinity change?
> 
> This is specially troubling as in general, chained irq handlers cannot
> move interrupts without breaking the affinity of other interrupts, and
> I'd like to know where we stand here.
> 

Each node(4-core cpu) has an EIO irq controller, the controllers in each
node of a nodes-group in a system are looked as an EIO instance and
configured according to the affinity of an EIO vector.

Although each EIO has 256 vectors, the nodes-group containing the EIO
instance has 256 vectors too, because all the vector in the same 
position in an EIO of each node is responsible for only one I/O 
interrupt. Any vector of the EIO instance in the group can be routed to
any cpu core of an node of the nodes-group, and each EIO has a routing 
register for the same vector, which is required to be configured when 
the vector's affinity is changed.

An I/O irq of PCH-PIC or PCH-MSI is mapped to one vector of the EIO 
instance, when the irq affinity of an vector is required to change, we 
just change routing register of the vector in each EIO hardware, which 
will not affect other vectors(I/O irqs).

The flow of an irq affinity setting for PCH-PIC or PCH-MSI is following:

- an irq of PCH-PIC:

do_set_affinity
-->irqchip ops->irq_set_affinity(d，...) PCH-PIC domain
   -->irqchip ops->irq_set_affinity(d，...) EIOINTC domain

- an irq of PCH-MSI:

do_set_affinity
-->irqchip ops->irq_set_affinity(d，...) PCH-MSI domain
   -->irqchip ops->irq_set_affinity(d，...) MIDDLE domain
     -->irqchip ops->irq_set_affinity(d，...) EIOINTC domain


>> +};
>> +
>> +static int eiointc_domain_alloc(struct irq_domain *domain, unsigned int virq,
>> +				unsigned int nr_irqs, void *arg)
>> +{
>> +	int ret;
>> +	unsigned int i, type;
>> +	unsigned long hwirq = 0;
>> +	struct eiointc *priv = domain->host_data;
>> +
>> +	ret = irq_domain_translate_onecell(domain, arg, &hwirq, &type);
>> +	if (ret)
>> +		return ret;
>> +
>> +	for (i = 0; i < nr_irqs; i++) {
>> +		irq_domain_set_info(domain, virq + i, hwirq + i, &eiointc_irq_chip,
>> +					priv, handle_edge_irq, NULL, NULL);
>> +	}
>> +
>> +	return 0;
>> +}
>> +
>> +static void eiointc_domain_free(struct irq_domain *domain, unsigned int virq,
>> +				unsigned int nr_irqs)
>> +{
>> +	int i;
>> +
>> +	for (i = 0; i < nr_irqs; i++) {
>> +		struct irq_data *d = irq_domain_get_irq_data(domain, virq + i);
>> +
>> +		irq_set_handler(virq + i, NULL);
>> +		irq_domain_reset_irq_data(d);
>> +	}
>> +}
>> +
>> +static const struct irq_domain_ops eiointc_domain_ops = {
>> +	.translate	= irq_domain_translate_onecell,
>> +	.alloc		= eiointc_domain_alloc,
>> +	.free		= eiointc_domain_free,
>> +};
>> +
>> +static void acpi_set_vec_parent(int node, struct irq_domain *parent, struct acpi_vector_group *vec_group)
>> +{
>> +	int i;
>> +
>> +	if (cpu_has_flatmode)
>> +		node = cpu_to_node(node * CORES_PER_EIO_NODE);
>> +
>> +	for (i = 0; i < MAX_IO_PICS; i++) {
>> +		if (node == vec_group[i].node) {
>> +			vec_group[i].parent = parent;
>> +			return;
>> +		}
>> +	}
>> +}
>> +
>> +struct irq_domain *acpi_get_vec_parent(int node, struct acpi_vector_group *vec_group)
>> +{
>> +	int i;
>> +
>> +	for (i = 0; i < MAX_IO_PICS; i++) {
>> +		if (node == vec_group[i].node)
>> +			return vec_group[i].parent;
>> +	}
>> +	return NULL;
>> +}
>> +
>> +static int __init
>> +pch_pic_parse_madt(union acpi_subtable_headers *header,
>> +		       const unsigned long end)
>> +{
>> +	struct acpi_madt_bio_pic *pchpic_entry = (struct acpi_madt_bio_pic *)header;
>> +	unsigned int node = (pchpic_entry->address >> 44) & 0xf;
>> +	struct irq_domain *parent = acpi_get_vec_parent(node, pch_group);
>> +
>> +	if (parent)
>> +		return pch_pic_acpi_init(parent, pchpic_entry);
>> +
>> +	return -EINVAL;
>> +}
>> +
>> +static int __init
>> +pch_msi_parse_madt(union acpi_subtable_headers *header,
>> +		       const unsigned long end)
>> +{
>> +	struct acpi_madt_msi_pic *pchmsi_entry = (struct acpi_madt_msi_pic *)header;
>> +	struct irq_domain *parent = acpi_get_vec_parent(eiointc_priv[nr_pics - 1]->node, msi_group);
>> +
>> +	if (parent)
>> +		return pch_msi_acpi_init(parent, pchmsi_entry);
>> +
>> +	return -EINVAL;
>> +}
>> +
>> +static int __init acpi_cascade_irqdomain_init(void)
>> +{
>> +	acpi_table_parse_madt(ACPI_MADT_TYPE_BIO_PIC,
>> +			      pch_pic_parse_madt, 0);
>> +	acpi_table_parse_madt(ACPI_MADT_TYPE_MSI_PIC,
>> +			      pch_msi_parse_madt, 1);
>> +	return 0;
>> +}
>> +
>> +int __init eiointc_acpi_init(struct irq_domain *parent,
>> +				     struct acpi_madt_eio_pic *acpi_eiointc)
>> +{
>> +	int i, parent_irq;
>> +	unsigned long node_map;
>> +	struct eiointc_priv *priv;
>> +
>> +	if (!acpi_eiointc)
>> +		return -EINVAL;
> 
> How can this happen?
> 

Yes, it's should be cleaned. In previours version, acpi_eiointc is a 
global variable and will be set outside this file. But now, it's not 
global any more, so I'll clean it, thanks.


>> +
>> +	priv = kzalloc(sizeof(*priv), GFP_KERNEL);
>> +	if (!priv)
>> +		return -ENOMEM;
>> +
>> +	priv->domain_handle = irq_domain_alloc_fwnode((phys_addr_t *)acpi_eiointc);
>> +	if (!priv->domain_handle) {
>> +		pr_err("Unable to allocate domain handle\n");
>> +		goto out_free_priv;
>> +	}
>> +
>> +	priv->node = acpi_eiointc->node;
>> +	node_map = acpi_eiointc->node_map ? : -1ULL;
>> +
>> +	for_each_possible_cpu(i) {
>> +		if (node_map & (1ULL << cpu_to_eio_node(i))) {
>> +			node_set(cpu_to_eio_node(i), priv->node_map);
>> +			cpumask_or(&priv->cpuspan_map, &priv->cpuspan_map, cpumask_of(i));
>> +		}
>> +	}
>> +
>> +	/* Setup IRQ domain */
>> +	priv->eiointc_domain = irq_domain_create_linear(priv->domain_handle, VEC_COUNT,
>> +					&eiointc_domain_ops, priv);
>> +	if (!priv->eiointc_domain) {
>> +		pr_err("loongson-eiointc: cannot add IRQ domain\n");
>> +		goto out_free_handle;
>> +	}
>> +
>> +	eiointc_priv[nr_pics++] = priv;
>> +
>> +	eiointc_router_init(0);
>> +
>> +	parent_irq = irq_create_mapping(parent, acpi_eiointc->cascade);
>> +	irq_set_chained_handler_and_data(parent_irq, eiointc_irq_dispatch, priv);
>> +
>> +	cpuhp_setup_state_nocalls(CPUHP_AP_IRQ_LOONGARCH_STARTING,
>> +				  "irqchip/loongarch/intc:starting",
>> +				  eiointc_router_init, NULL);
>> +
>> +	acpi_set_vec_parent(acpi_eiointc->node, priv->eiointc_domain, pch_group);
>> +	acpi_set_vec_parent(acpi_eiointc->node, priv->eiointc_domain, msi_group);
>> +	acpi_cascade_irqdomain_init();
>> +
>> +	return 0;
>> +
>> +out_free_handle:
>> +	irq_domain_free_fwnode(priv->domain_handle);
>> +	priv->domain_handle = NULL;
>> +out_free_priv:
>> +	kfree(priv);
>> +
>> +	return -ENOMEM;
>> +}
>> diff --git a/include/linux/cpuhotplug.h b/include/linux/cpuhotplug.h
>> index 19f0dbf..de662f3 100644
>> --- a/include/linux/cpuhotplug.h
>> +++ b/include/linux/cpuhotplug.h
>> @@ -151,6 +151,7 @@ enum cpuhp_state {
>>   	CPUHP_AP_IRQ_BCM2836_STARTING,
>>   	CPUHP_AP_IRQ_MIPS_GIC_STARTING,
>>   	CPUHP_AP_IRQ_RISCV_STARTING,
>> +	CPUHP_AP_IRQ_LOONGARCH_STARTING,
>>   	CPUHP_AP_IRQ_SIFIVE_PLIC_STARTING,
>>   	CPUHP_AP_ARM_MVEBU_COHERENCY,
>>   	CPUHP_AP_MICROCODE_LOADER,
>> -- 
>> 1.8.3.1
>>
>>
> 
> Thanks,
> 
> 	M.
> 

Re: [PATCH V14 14/15] irqchip / ACPI: Introduce ACPI_IRQ_MODEL_LPIC for LoongArch

[Jianmin Lv]

On 2022/7/8 上午11:17, Jianmin Lv wrote:
> 
> 
> On 2022/7/7 下午8:59, Marc Zyngier wrote:
>> On Sun, 03 Jul 2022 09:45:31 +0100,
>> Jianmin Lv <lvjianmin@loongson.cn> wrote:
>>>
>>> For LoongArch, ACPI_IRQ_MODEL_LPIC is introduced, and then the
>>> callback acpi_get_gsi_domain_id and acpi_gsi_to_irq_fallback are
>>> implemented.
>>>
>>> The acpi_get_gsi_domain_id callback returns related fwnode handle
>>> of irqdomain for different GSI range.
>>>
>>> The acpi_gsi_to_irq_fallback will create new mapping for gsi when
>>> the mapping of it is not found.
>>>
>>> Signed-off-by: Jianmin Lv <lvjianmin@loongson.cn>
>>> ---
>>>   drivers/acpi/bus.c                  |  3 +++
>>>   drivers/irqchip/irq-loongarch-cpu.c | 37 
>>> +++++++++++++++++++++++++++++++++++++
>>>   include/linux/acpi.h                |  1 +
>>>   3 files changed, 41 insertions(+)
>>>
>>> diff --git a/drivers/acpi/bus.c b/drivers/acpi/bus.c
>>> index 86fa61a..63fbf00 100644
>>> --- a/drivers/acpi/bus.c
>>> +++ b/drivers/acpi/bus.c
>>> @@ -1145,6 +1145,9 @@ static int __init acpi_bus_init_irq(void)
>>>       case ACPI_IRQ_MODEL_PLATFORM:
>>>           message = "platform specific model";
>>>           break;
>>> +    case ACPI_IRQ_MODEL_LPIC:
>>> +        message = "LPIC";
>>> +        break;
>>>       default:
>>>           pr_info("Unknown interrupt routing model\n");
>>>           return -ENODEV;
>>> diff --git a/drivers/irqchip/irq-loongarch-cpu.c 
>>> b/drivers/irqchip/irq-loongarch-cpu.c
>>> index c2f7411..1b241d7 100644
>>> --- a/drivers/irqchip/irq-loongarch-cpu.c
>>> +++ b/drivers/irqchip/irq-loongarch-cpu.c
>>> @@ -15,6 +15,41 @@
>>>   static struct irq_domain *irq_domain;
>>> +static int lpic_gsi_to_irq(u32 gsi)
>>> +{
>>> +    /* Only pch irqdomain transferring is required for LoongArch. */
>>> +    if (gsi >= GSI_MIN_PCH_IRQ && gsi <= GSI_MAX_PCH_IRQ)
>>> +        return acpi_register_gsi(NULL, gsi, ACPI_LEVEL_SENSITIVE, 
>>> ACPI_ACTIVE_HIGH);
>>> +    return -1;
>>
>> The expected return value on failure is 0 (which indicates that no
>> interrupt was mapped). Here, things will break as acpi_gsi_to_irq()
>> stores the result as unsigned, and compares the result to 0.
>>
> 
> Ok, thanks, I'll change the return value to 0 on failure and change 
> return type to unsigned int.
> 
> 

Hi, Marc, if the return type is changed to unsigned int, the return type 
of the fallback handler in the patch:
ACPI: irq: Allow acpi_gsi_to_irq() to have an arch-specific fallback

should be changed to unsigned int too, yes?

>>     M.
>>

Re: [PATCH V14 14/15] irqchip / ACPI: Introduce ACPI_IRQ_MODEL_LPIC for LoongArch

[Marc Zyngier]

On 2022-07-14 11:02, Jianmin Lv wrote:
> On 2022/7/8 上午11:17, Jianmin Lv wrote:
>> 
>> 
>> On 2022/7/7 下午8:59, Marc Zyngier wrote:
>>> On Sun, 03 Jul 2022 09:45:31 +0100,
>>> Jianmin Lv <lvjianmin@loongson.cn> wrote:
>>>> 
>>>> For LoongArch, ACPI_IRQ_MODEL_LPIC is introduced, and then the
>>>> callback acpi_get_gsi_domain_id and acpi_gsi_to_irq_fallback are
>>>> implemented.
>>>> 
>>>> The acpi_get_gsi_domain_id callback returns related fwnode handle
>>>> of irqdomain for different GSI range.
>>>> 
>>>> The acpi_gsi_to_irq_fallback will create new mapping for gsi when
>>>> the mapping of it is not found.
>>>> 
>>>> Signed-off-by: Jianmin Lv <lvjianmin@loongson.cn>
>>>> ---
>>>>   drivers/acpi/bus.c                  |  3 +++
>>>>   drivers/irqchip/irq-loongarch-cpu.c | 37 
>>>> +++++++++++++++++++++++++++++++++++++
>>>>   include/linux/acpi.h                |  1 +
>>>>   3 files changed, 41 insertions(+)
>>>> 
>>>> diff --git a/drivers/acpi/bus.c b/drivers/acpi/bus.c
>>>> index 86fa61a..63fbf00 100644
>>>> --- a/drivers/acpi/bus.c
>>>> +++ b/drivers/acpi/bus.c
>>>> @@ -1145,6 +1145,9 @@ static int __init acpi_bus_init_irq(void)
>>>>       case ACPI_IRQ_MODEL_PLATFORM:
>>>>           message = "platform specific model";
>>>>           break;
>>>> +    case ACPI_IRQ_MODEL_LPIC:
>>>> +        message = "LPIC";
>>>> +        break;
>>>>       default:
>>>>           pr_info("Unknown interrupt routing model\n");
>>>>           return -ENODEV;
>>>> diff --git a/drivers/irqchip/irq-loongarch-cpu.c 
>>>> b/drivers/irqchip/irq-loongarch-cpu.c
>>>> index c2f7411..1b241d7 100644
>>>> --- a/drivers/irqchip/irq-loongarch-cpu.c
>>>> +++ b/drivers/irqchip/irq-loongarch-cpu.c
>>>> @@ -15,6 +15,41 @@
>>>>   static struct irq_domain *irq_domain;
>>>> +static int lpic_gsi_to_irq(u32 gsi)
>>>> +{
>>>> +    /* Only pch irqdomain transferring is required for LoongArch. 
>>>> */
>>>> +    if (gsi >= GSI_MIN_PCH_IRQ && gsi <= GSI_MAX_PCH_IRQ)
>>>> +        return acpi_register_gsi(NULL, gsi, ACPI_LEVEL_SENSITIVE, 
>>>> ACPI_ACTIVE_HIGH);
>>>> +    return -1;
>>> 
>>> The expected return value on failure is 0 (which indicates that no
>>> interrupt was mapped). Here, things will break as acpi_gsi_to_irq()
>>> stores the result as unsigned, and compares the result to 0.
>>> 
>> 
>> Ok, thanks, I'll change the return value to 0 on failure and change 
>> return type to unsigned int.
>> 
>> 
> 
> Hi, Marc, if the return type is changed to unsigned int, the return
> type of the fallback handler in the patch:
> ACPI: irq: Allow acpi_gsi_to_irq() to have an arch-specific fallback
> 
> should be changed to unsigned int too, yes?

Yes, of course.

         M.
-- 
Jazz is not dead. It just smells funny...