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[86.58.17.133]) by smtp.gmail.com with ESMTPSA id q4sm1907694edv.24.2021.06.03.08.12.13 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 03 Jun 2021 08:12:14 -0700 (PDT) From: Jernej =?utf-8?B?xaBrcmFiZWM=?= To: Jagan Teki , Icenowy Zheng , Andre Przywara Cc: u-boot@lists.denx.de, linux-sunxi@googlegroups.com Subject: Re: [PATCH v2] sunxi: clock: H6/H616: Fix PLL clock factor encodings Date: Thu, 03 Jun 2021 17:12:13 +0200 Message-ID: <1658772.Ul5fHAyusi@jernej-laptop> In-Reply-To: <20210527004948.0c2ef6b6@slackpad.fritz.box> References: <20210505125305.20564-1-andre.przywara@arm.com> <20210527004948.0c2ef6b6@slackpad.fritz.box> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="UTF-8" X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.34 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.102.4 at phobos.denx.de X-Virus-Status: Clean Hi! Dne =C4=8Detrtek, 27. maj 2021 ob 01:49:48 CEST je Andre Przywara napisal(a= ): > On Wed, 5 May 2021 13:53:05 +0100 > Andre Przywara wrote: >=20 > Hi, >=20 > > Most clock factors and dividers in the H6 PLLs use a "+1 encoding", > > which we were missing on two occasions. >=20 > can someone please confirm that I didn't mess this up? >=20 > Cheers, > Andre >=20 > > This fixes the MMC clock setup on the H6, which could be slightly off d= ue > > to the wrong parent frequency: > > mmc 2 set mod-clk req 52000000 parent 1176000000 n 2 m 12 rate 49000000 > >=20 > > Also the CPU frequency was a tad too high before. > >=20 > > Signed-off-by: Andre Przywara > > --- > > Changelog v1 .. v2: > > - Also fix PLL5 factor calculation (video, currently unused) > > - Also fix PLL1 factor calculation (CPU clock) > >=20 > > arch/arm/include/asm/arch-sunxi/clock_sun50i_h6.h | 4 ++-- > > arch/arm/mach-sunxi/clock_sun50i_h6.c | 2 +- > > 2 files changed, 3 insertions(+), 3 deletions(-) > >=20 > > diff --git a/arch/arm/include/asm/arch-sunxi/clock_sun50i_h6.h > > b/arch/arm/include/asm/arch-sunxi/clock_sun50i_h6.h index > > 62abfc4ef6b..2e076cf594d 100644 > > --- a/arch/arm/include/asm/arch-sunxi/clock_sun50i_h6.h > > +++ b/arch/arm/include/asm/arch-sunxi/clock_sun50i_h6.h > > @@ -233,14 +233,14 @@ struct sunxi_ccm_reg { > >=20 > > #define CCM_PLL1_OUT_EN BIT(27) > > #define CCM_PLL1_CLOCK_TIME_2 (2 << 24) > > #define CCM_PLL1_CTRL_P(p) ((p) << 16) > >=20 > > -#define CCM_PLL1_CTRL_N(n) ((n) << 8) > > +#define CCM_PLL1_CTRL_N(n) (((n) - 1) << 8) > >=20 > > /* pll5 bit field */ > > #define CCM_PLL5_CTRL_EN BIT(31) > > #define CCM_PLL5_LOCK_EN BIT(29) > > #define CCM_PLL5_LOCK BIT(28) > > #define CCM_PLL5_OUT_EN BIT(27) > >=20 > > -#define CCM_PLL5_CTRL_N(n) ((n) << 8) > > +#define CCM_PLL5_CTRL_N(n) (((n) - 1) << 8) H6 and H616 DRAM drivers actually consider this "- 1" in the code. Either d= rop=20 this change or fix DRAM drivers. With that: Reviewed-by: Jernej Skrabec Best regards, Jernej > >=20 > > #define CCM_PLL5_CTRL_DIV1(div1) ((div1) << 0) > > #define CCM_PLL5_CTRL_DIV2(div0) ((div0) << 1) > >=20 > > diff --git a/arch/arm/mach-sunxi/clock_sun50i_h6.c > > b/arch/arm/mach-sunxi/clock_sun50i_h6.c index 492fc4a3fca..a947463e0a5 > > 100644 > > --- a/arch/arm/mach-sunxi/clock_sun50i_h6.c > > +++ b/arch/arm/mach-sunxi/clock_sun50i_h6.c > > @@ -94,7 +94,7 @@ unsigned int clock_get_pll6(void) > >=20 > > int m =3D IS_ENABLED(CONFIG_MACH_SUN50I_H6) ? 4 : 2; > > =09 > > uint32_t rval =3D readl(&ccm->pll6_cfg); > >=20 > > - int n =3D ((rval & CCM_PLL6_CTRL_N_MASK) >> CCM_PLL6_CTRL_N_SHIFT); > > + int n =3D ((rval & CCM_PLL6_CTRL_N_MASK) >> CCM_PLL6_CTRL_N_SHIFT) += =20 1; > >=20 > > int div1 =3D ((rval & CCM_PLL6_CTRL_DIV1_MASK) >> > > =09 > > CCM_PLL6_CTRL_DIV1_SHIFT) + 1; > > =09 > > int div2 =3D ((rval & CCM_PLL6_CTRL_DIV2_MASK) >>