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Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB04.amd.com; pr=C Received: from SATLEXMB04.amd.com (165.204.84.17) by DM6NAM11FT050.mail.protection.outlook.com (10.13.173.111) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.5791.20 via Frontend Transport; Fri, 4 Nov 2022 19:59:58 +0000 Received: from [127.0.1.1] (10.180.168.240) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2375.31; Fri, 4 Nov 2022 14:59:56 -0500 Subject: [PATCH v8 01/13] x86/cpufeatures: Add Slow Memory Bandwidth Allocation feature flag From: Babu Moger To: , , , , CC: , , , , , , , , , , , , , , , , , , , , , , , , Date: Fri, 4 Nov 2022 14:59:56 -0500 Message-ID: <166759199632.3281208.5709918293488898752.stgit@bmoger-ubuntu> In-Reply-To: <166759188265.3281208.11769277079826754455.stgit@bmoger-ubuntu> References: <166759188265.3281208.11769277079826754455.stgit@bmoger-ubuntu> User-Agent: StGit/1.1.dev103+g5369f4c MIME-Version: 1.0 Content-Type: text/plain; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 04 Nov 2022 19:59:58.7387 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 6c8905ac-a3e7-4dda-1911-08dabe9f26e8 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: DM6NAM11FT050.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DS7PR12MB5720 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Add the new AMD feature X86_FEATURE_SMBA. With this feature, the QOS=0A= enforcement policies can be applied to external slow memory connected=0A= to the host. QOS enforcement is accomplished by assigning a Class Of=0A= Service (COS) to a processor and specifying allocations or limits for=0A= that COS for each resource to be allocated.=0A= =0A= This feature is identified by the CPUID Function 8000_0020_EBX_x0.=0A= =0A= CPUID Fn8000_0020_EBX_x0 AMD Bandwidth Enforcement Feature Identifiers=0A= (ECX=3D0)=0A= =0A= Bits Field Name Description=0A= 2 L3SBE L3 external slow memory bandwidth enforcement=0A= =0A= Currently, CXL.memory is the only supported "slow" memory device. With=0A= the support of SMBA feature, the hardware enables bandwidth allocation=0A= on the slow memory devices. If there are multiple slow memory devices=0A= in the system, then the throttling logic groups all the slow sources=0A= together and applies the limit on them as a whole.=0A= =0A= The presence of the SMBA feature(with CXL.memory) is independent of=0A= whether slow memory device is actually present in the system. If there=0A= is no slow memory in the system, then setting a SMBA limit will have no=0A= impact on the performance of the system.=0A= =0A= Presence of CXL memory can be identified by numactl command.=0A= =0A= $numactl -H=0A= available: 2 nodes (0-1)=0A= node 0 cpus: 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16=0A= node 0 size: 63678 MB node 0 free: 59542 MB=0A= node 1 cpus:=0A= node 1 size: 16122 MB=0A= node 1 free: 15627 MB=0A= node distances:=0A= node 0 1=0A= 0: 10 50=0A= 1: 50 10=0A= =0A= CPU list for CXL memory will be empty. The cpu-cxl node distance is=0A= greater than cpu-to-cpu distances. Node 1 has the CXL memory in this=0A= case. CXL memory can also be identified using ACPI SRAT table and=0A= memory maps.=0A= =0A= Feature description is available in the specification, "AMD64=0A= Technology Platform Quality of Service Extensions, Revision: 1.03=0A= Publication # 56375 Revision: 1.03 Issue Date: February 2022".=0A= =0A= Link: https://www.amd.com/en/support/tech-docs/amd64-technology-platform-qu= ality-service-extensions=0A= Link: https://bugzilla.kernel.org/show_bug.cgi?id=3D206537=0A= Signed-off-by: Babu Moger =0A= ---=0A= arch/x86/include/asm/cpufeatures.h | 1 +=0A= arch/x86/kernel/cpu/scattered.c | 1 +=0A= 2 files changed, 2 insertions(+)=0A= =0A= diff --git a/arch/x86/include/asm/cpufeatures.h b/arch/x86/include/asm/cpuf= eatures.h=0A= index aefd0816a333..d68b4c9c181d 100644=0A= --- a/arch/x86/include/asm/cpufeatures.h=0A= +++ b/arch/x86/include/asm/cpufeatures.h=0A= @@ -305,6 +305,7 @@=0A= #define X86_FEATURE_USE_IBPB_FW (11*32+16) /* "" Use IBPB during runtime = firmware calls */=0A= #define X86_FEATURE_RSB_VMEXIT_LITE (11*32+17) /* "" Fill RSB on VM exit w= hen EIBRS is enabled */=0A= #define X86_FEATURE_CALL_DEPTH (11*32+18) /* "" Call depth tracking for R= SB stuffing */=0A= +#define X86_FEATURE_SMBA (11*32+19) /* Slow Memory Bandwidth Allocation *= /=0A= =0A= /* Intel-defined CPU features, CPUID level 0x00000007:1 (EAX), word 12 */= =0A= #define X86_FEATURE_AVX_VNNI (12*32+ 4) /* AVX VNNI instructions */=0A= diff --git a/arch/x86/kernel/cpu/scattered.c b/arch/x86/kernel/cpu/scattere= d.c=0A= index fc01f81f6e2a..5a5f17ed69a2 100644=0A= --- a/arch/x86/kernel/cpu/scattered.c=0A= +++ b/arch/x86/kernel/cpu/scattered.c=0A= @@ -44,6 +44,7 @@ static const struct cpuid_bit cpuid_bits[] =3D {=0A= { X86_FEATURE_CPB, CPUID_EDX, 9, 0x80000007, 0 },=0A= { X86_FEATURE_PROC_FEEDBACK, CPUID_EDX, 11, 0x80000007, 0 },=0A= { X86_FEATURE_MBA, CPUID_EBX, 6, 0x80000008, 0 },=0A= + { X86_FEATURE_SMBA, CPUID_EBX, 2, 0x80000020, 0 },=0A= { X86_FEATURE_PERFMON_V2, CPUID_EAX, 0, 0x80000022, 0 },=0A= { X86_FEATURE_AMD_LBR_V2, CPUID_EAX, 1, 0x80000022, 0 },=0A= { 0, 0, 0, 0, 0 }=0A= =0A=