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From: Dave Jiang <dave.jiang@intel.com>
To: linux-cxl@vger.kernel.org
Cc: Ira Weiny <ira.weiny@intel.com>,
	Jonathan Cameron <Jonathan.Cameron@huawei.com>,
	dan.j.williams@intel.com, ira.weiny@intel.com,
	vishal.l.verma@intel.com, alison.schofield@intel.com
Subject: [PATCH 3/3] cxl: Add support for reading CXL switch CDAT table
Date: Fri, 05 May 2023 09:35:35 -0700	[thread overview]
Message-ID: <168330453501.1986478.10682875024496375027.stgit@djiang5-mobl3> (raw)
In-Reply-To: <168330433154.1986478.2238692205077357255.stgit@djiang5-mobl3>

Add read_cdat_data() call in cxl_switch_port_probe() to allow
reading of CDAT data for CXL switches. read_cdat_data() needs
to be adjusted for the retrieving of the PCIe device depending
on if the passed in port is endpoint or switch.

Reviewed-by: Ira Weiny <ira.weiny@intel.com>
Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Signed-off-by: Dave Jiang <dave.jiang@intel.com>

---
v5:
- Rebase after fix [1]. (Dan)

[1]: http://lore.kernel.org/r/168213190748.708404.16215095414060364800.stgit@dwillia2-xfh.jf.intel.com
v4:
- Remove cxl_test wrapper. (Ira)
---
 drivers/cxl/core/pci.c |   21 ++++++++++++++++-----
 drivers/cxl/port.c     |    3 +++
 2 files changed, 19 insertions(+), 5 deletions(-)

diff --git a/drivers/cxl/core/pci.c b/drivers/cxl/core/pci.c
index 046e55a9b419..9fabfe458499 100644
--- a/drivers/cxl/core/pci.c
+++ b/drivers/cxl/core/pci.c
@@ -546,18 +546,29 @@ static unsigned char cdat_checksum(void *buf, size_t size)
  */
 void read_cdat_data(struct cxl_port *port)
 {
-	struct cxl_memdev *cxlmd = to_cxl_memdev(port->uport);
-	struct device *host = cxlmd->dev.parent;
+	struct device *uport = port->uport;
 	struct device *dev = &port->dev;
 	struct pci_doe_mb *cdat_doe;
+	struct cxl_memdev *cxlmd;
+	struct pci_dev *pdev;
+	struct device *host;
 	size_t cdat_length;
 	void *cdat_table;
 	int rc;
 
-	if (!dev_is_pci(host))
+	if (is_cxl_memdev(uport)) {
+		cxlmd = to_cxl_memdev(uport);
+		host = cxlmd->dev.parent;
+		if (!dev_is_pci(host))
+			return;
+		pdev = to_pci_dev(host);
+	} else if (dev_is_pci(uport)) {
+		pdev = to_pci_dev(uport);
+	} else {
 		return;
-	cdat_doe = pci_find_doe_mailbox(to_pci_dev(host),
-					PCI_DVSEC_VENDOR_ID_CXL,
+	}
+
+	cdat_doe = pci_find_doe_mailbox(pdev, PCI_DVSEC_VENDOR_ID_CXL,
 					CXL_DOE_PROTOCOL_TABLE_ACCESS);
 	if (!cdat_doe) {
 		dev_dbg(dev, "No CDAT mailbox\n");
diff --git a/drivers/cxl/port.c b/drivers/cxl/port.c
index 22a7ab2bae7c..a49f5eb149f1 100644
--- a/drivers/cxl/port.c
+++ b/drivers/cxl/port.c
@@ -62,6 +62,9 @@ static int cxl_switch_port_probe(struct cxl_port *port)
 	struct cxl_hdm *cxlhdm;
 	int rc;
 
+	/* Cache the data early to ensure is_visible() works */
+	read_cdat_data(port);
+
 	rc = devm_cxl_port_enumerate_dports(port);
 	if (rc < 0)
 		return rc;



  parent reply	other threads:[~2023-05-05 16:35 UTC|newest]

Thread overview: 8+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2023-05-05 16:35 [PATCH 0/3] cxl: Prep for QoS class support Dave Jiang
2023-05-05 16:35 ` [PATCH 1/3] cxl: Export QTG ids from CFMWS to sysfs as qos_class attribute Dave Jiang
2023-05-05 20:55   ` Davidlohr Bueso
2023-05-05 16:35 ` [PATCH 2/3] cxl: Add checksum verification to CDAT from CXL Dave Jiang
2023-05-05 19:15   ` Davidlohr Bueso
2023-05-05 20:43     ` Dave Jiang
2023-05-05 16:35 ` Dave Jiang [this message]
2023-05-05 20:44   ` [PATCH 3/3] cxl: Add support for reading CXL switch CDAT table Davidlohr Bueso

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