From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751371AbeC0GQp (ORCPT ); Tue, 27 Mar 2018 02:16:45 -0400 Received: from szxga01-in.huawei.com ([45.249.212.187]:5909 "EHLO huawei.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1751121AbeC0GQm (ORCPT ); Tue, 27 Mar 2018 02:16:42 -0400 From: "liwei (CM)" To: "liwei (CM)" , Arnd Bergmann CC: Rob Herring , Mark Rutland , "xuwei (O)" , Catalin Marinas , Will Deacon , Vinayak Holikatti , "James E.J. Bottomley" , "Martin K. Petersen" , Kevin Hilman , Gregory CLEMENT , Thomas Petazzoni , Masahiro Yamada , Riku Voipio , Thierry Reding , Krzysztof Kozlowski , Eric Anholt , DTML , "Linux Kernel Mailing List" , Linux ARM , linux-scsi , zangleigang , Gengjianfeng , Guodong Xu , Zhangfei Gao , "Fengbaopeng (kevin, Kirin Solution Dept)" , "Yaniv Gardi" Subject: =?utf-8?B?562U5aSNOiDnrZTlpI06IOetlOWkjTogW1BBVENIIHY4IDIvNV0gZHQtYmlu?= =?utf-8?Q?dings:_scsi:_ufs:_add_document_for_hisi-ufs?= Thread-Topic: =?utf-8?B?562U5aSNOiDnrZTlpI06IFtQQVRDSCB2OCAyLzVdIGR0LWJpbmRpbmdzOiBz?= =?utf-8?Q?csi:_ufs:_add_document_for_hisi-ufs?= Thread-Index: AQHTpLNt7xq76dhVgkeSgBp0Vy2vQaOrAJgAgDJE6ZCABLCUgIAAkqZA//+FzQCAAJJzQIABEYQA Date: Tue, 27 Mar 2018 06:15:15 +0000 Message-ID: <1699CE87DE933F49876AD744B5DC140FA588AD@DGGEMM506-MBS.china.huawei.com> References: <20180213101412.5717-1-liwei213@huawei.com> <20180213101412.5717-3-liwei213@huawei.com> <1699CE87DE933F49876AD744B5DC140FA584ED@DGGEMM506-MBS.china.huawei.com> <1699CE87DE933F49876AD744B5DC140FA58798@DGGEMM506-MBS.china.huawei.com> Accept-Language: zh-CN, en-US Content-Language: zh-CN X-MS-Has-Attach: X-MS-TNEF-Correlator: x-originating-ip: [10.189.155.72] Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 X-CFilter-Loop: Reflected Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: 8bit X-MIME-Autoconverted: from base64 to 8bit by mail.home.local id w2R6GnhO029603 Hi, Arnd At present our ufs module mainly has four clocks from the outside: hclk_ufs: main clock of ufs controller ,freq is 207.5MHz cfg_phy_clk: configuration clock of MPHY, freq is 51.875MHz ref_phy_clk: reference clock of MPHY from PMU, freq is 19.2MHz ref_io_clk: reference clock for the external interface to the device, freq is 19.2MHz We control two clocks "ref_io_clk" and "cfg_phy_clk" in the driver because the other two are controlled by main clock module and pmu. for this patch, cfg_phy_clk corresponds to "phy_clk", ref_io_clk corresponds to "ref_clk". So the clks in the patch you give appear to be unsuitable for describing this .And the following clks of qcom are internal clock? We didn't describe or pay attention to the clock inside the ufs module. PHY to controller symbol synchronization clocks: "rx_lane0_sync_clk" - RX Lane 0 "rx_lane1_sync_clk" - RX Lane 1 "tx_lane0_sync_clk" - TX Lane 0 "tx_lane1_sync_clk" - TX Lane 1 -----邮件原件----- 发件人: liwei (CM) 发送时间: 2018年3月26日 20:02 收件人: 'Arnd Bergmann' 抄送: Rob Herring; Mark Rutland; xuwei (O); Catalin Marinas; Will Deacon; Vinayak Holikatti; James E.J. Bottomley; Martin K. Petersen; Kevin Hilman; Gregory CLEMENT; Thomas Petazzoni; Masahiro Yamada; Riku Voipio; Thierry Reding; Krzysztof Kozlowski; Eric Anholt; DTML; Linux Kernel Mailing List; Linux ARM; linux-scsi; zangleigang; Gengjianfeng; Guodong Xu; Zhangfei Gao; Fengbaopeng (kevin, Kirin Solution Dept); Yaniv Gardi 主题: 答复: 答复: 答复: [PATCH v8 2/5] dt-bindings: scsi: ufs: add document for hisi-ufs Hi, Arnd I'll ask our soc colleagues for help and give a detailed and accurate explanation aosp. Thanks! -----邮件原件----- 发件人: arndbergmann@gmail.com [mailto:arndbergmann@gmail.com] 代表 Arnd Bergmann 发送时间: 2018年3月26日 18:42 收件人: liwei (CM) 抄送: Rob Herring; Mark Rutland; xuwei (O); Catalin Marinas; Will Deacon; Vinayak Holikatti; James E.J. Bottomley; Martin K. Petersen; Kevin Hilman; Gregory CLEMENT; Thomas Petazzoni; Masahiro Yamada; Riku Voipio; Thierry Reding; Krzysztof Kozlowski; Eric Anholt; DTML; Linux Kernel Mailing List; Linux ARM; linux-scsi; zangleigang; Gengjianfeng; Guodong Xu; Zhangfei Gao; Fengbaopeng (kevin, Kirin Solution Dept); Yaniv Gardi 主题: Re: 答复: 答复: [PATCH v8 2/5] dt-bindings: scsi: ufs: add document for hisi-ufs On Mon, Mar 26, 2018 at 12:26 PM, liwei (CM) wrote: > 发件人: arndbergmann@gmail.com [mailto:arndbergmann@gmail.com] 代表 Arnd > Bergmann > > 主题: Re: 答复: [PATCH v8 2/5] dt-bindings: scsi: ufs: add document for > > hisi-ufs On Fri, Mar 23, 2018 at 3:22 AM, liwei (CM) wrote: > >> The clock names sound generic enough, should we have both in the generic binding? > >> > >> Do you mean that add a "phy_clk" to ufshcd-pltfrm 's bindings? > >> At present, it seems that in the implementation of generic code, > >> apart from "ref_clk" may have special processing, other clk will > >> not have special processing and simply parse and enable; Referring > >> to ufs-qcom binding, I think "phy_clk" can be named "iface_clk", > >> this "iface_clk" exists in ufshcd-pltfrm bindings;If so, "ref_clk", "iface_clk" are both in the generic binding,we will remove them here. Is that okay? > > > I'm looking at the generic binding again, and it seems we never > > quite managed to fix some minor problems with it. See below for a possible way to clarify it. > > phy_clk is actually given to the phy. But as previously mentioned , we > do not have a separate phy to configure ; The clks in the patch you > give appear to be unsuitable for describing this . > Here we can't describe phy_clk in the node "ufsphy1: ufsphy@fc597000" like qcom. > So can we put it here in our own binding like this? I think the concept of having a phy clk is generic enough that it's better to have that in the common part, others will surely have the same thing, and in this case, qcom would be the exception that does not use one. There are apparently a couple of things related to the phy that may or may not require a clk: - ref_clk: The reference clock on the mipi bus, this is what qcom have, this would be the 19.2 MHz clock signal. - one clock to drive the logic block for the PHY itself, if it is included within the same logical portion of an SoC as the ufshcd, but uses a separate clock. - Looking at the Android kernel as distributed by google/qualcomm, they have four separate clocks described as PHY to controller symbol synchronization clocks: "rx_lane0_sync_clk" - RX Lane 0 "rx_lane1_sync_clk" - RX Lane 1 "tx_lane0_sync_clk" - TX Lane 0 "tx_lane1_sync_clk" - TX Lane 1 Which of the above would your phy_clk refer to? Arnd [1] https://android.googlesource.com/kernel/msm/+/android-msm-bullhead-3.10-marshmallow-dr/Documentation/devicetree/bindings/ufs/ufshcd-pltfrm.txt?autodive=0%2F%2F%2F%2F%2F From mboxrd@z Thu Jan 1 00:00:00 1970 From: "liwei (CM)" Subject: =?utf-8?B?562U5aSNOiDnrZTlpI06IOetlOWkjTogW1BBVENIIHY4IDIvNV0gZHQtYmlu?= =?utf-8?Q?dings:_scsi:_ufs:_add_document_for_hisi-ufs?= Date: Tue, 27 Mar 2018 06:15:15 +0000 Message-ID: <1699CE87DE933F49876AD744B5DC140FA588AD@DGGEMM506-MBS.china.huawei.com> References: <20180213101412.5717-1-liwei213@huawei.com> <20180213101412.5717-3-liwei213@huawei.com> <1699CE87DE933F49876AD744B5DC140FA584ED@DGGEMM506-MBS.china.huawei.com> <1699CE87DE933F49876AD744B5DC140FA58798@DGGEMM506-MBS.china.huawei.com> Mime-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: base64 Return-path: Content-Language: zh-CN Sender: linux-kernel-owner@vger.kernel.org To: "liwei (CM)" , Arnd Bergmann Cc: Rob Herring , Mark Rutland , "xuwei (O)" , Catalin Marinas , Will Deacon , Vinayak Holikatti , "James E.J. Bottomley" , "Martin K. Petersen" , Kevin Hilman , Gregory CLEMENT , Thomas Petazzoni , Masahiro Yamada , Riku Voipio , Thierry Reding , Krzysztof Kozlowski , Eric Anholt , DTML , Linux Kernel Mailing List List-Id: devicetree@vger.kernel.org SGksIEFybmQNCg0KQXQgcHJlc2VudCBvdXIgdWZzIG1vZHVsZSBtYWlubHkgaGFzIGZvdXIgY2xv Y2tzIGZyb20gdGhlIG91dHNpZGU6DQpoY2xrX3VmczogICAgIG1haW4gY2xvY2sgb2YgdWZzIGNv bnRyb2xsZXIgLGZyZXEgaXMgMjA3LjVNSHogDQpjZmdfcGh5X2NsazogIGNvbmZpZ3VyYXRpb24g Y2xvY2sgb2YgTVBIWSwgZnJlcSBpcyA1MS44NzVNSHoNCnJlZl9waHlfY2xrOiAgcmVmZXJlbmNl IGNsb2NrIG9mIE1QSFkgZnJvbSBQTVUsIGZyZXEgaXMgMTkuMk1Ieg0KcmVmX2lvX2NsazogICAg cmVmZXJlbmNlIGNsb2NrIGZvciB0aGUgZXh0ZXJuYWwgaW50ZXJmYWNlIHRvIHRoZSBkZXZpY2Us IGZyZXEgaXMgMTkuMk1Ieg0KDQpXZSBjb250cm9sIHR3byBjbG9ja3MgInJlZl9pb19jbGsiIGFu ZCAiY2ZnX3BoeV9jbGsiIGluIHRoZSBkcml2ZXIgYmVjYXVzZSB0aGUgb3RoZXIgdHdvIGFyZSBj b250cm9sbGVkIGJ5IG1haW4gY2xvY2sgbW9kdWxlIGFuZCBwbXUuIA0KZm9yIHRoaXMgcGF0Y2gs IGNmZ19waHlfY2xrIGNvcnJlc3BvbmRzIHRvICJwaHlfY2xrIiwgcmVmX2lvX2NsayBjb3JyZXNw b25kcyB0byAicmVmX2NsayIuDQoNClNvIHRoZSBjbGtzIGluIHRoZSBwYXRjaCB5b3UgZ2l2ZSBh cHBlYXIgdG8gYmUgdW5zdWl0YWJsZSBmb3IgZGVzY3JpYmluZyB0aGlzIC5BbmQgdGhlIGZvbGxv d2luZyBjbGtzIG9mIHFjb20gYXJlIGludGVybmFsIGNsb2NrPyANCldlIGRpZG4ndCBkZXNjcmli ZSBvciBwYXkgYXR0ZW50aW9uIHRvIHRoZSBjbG9jayBpbnNpZGUgdGhlIHVmcyBtb2R1bGUuDQoN ClBIWSB0byBjb250cm9sbGVyIHN5bWJvbCBzeW5jaHJvbml6YXRpb24gY2xvY2tzOg0KICAgICAg ICAicnhfbGFuZTBfc3luY19jbGsiIC0gUlggTGFuZSAwDQogICAgICAgICJyeF9sYW5lMV9zeW5j X2NsayIgLSBSWCBMYW5lIDENCiAgICAgICAgInR4X2xhbmUwX3N5bmNfY2xrIiAtIFRYIExhbmUg MA0KICAgICAgICAidHhfbGFuZTFfc3luY19jbGsiIC0gVFggTGFuZSAxDQoNCg0KLS0tLS3pgq7k u7bljp/ku7YtLS0tLQ0K5Y+R5Lu25Lq6OiBsaXdlaSAoQ00pIA0K5Y+R6YCB5pe26Ze0OiAyMDE4 5bm0M+aciDI25pelIDIwOjAyDQrmlLbku7bkuro6ICdBcm5kIEJlcmdtYW5uJw0K5oqE6YCBOiBS b2IgSGVycmluZzsgTWFyayBSdXRsYW5kOyB4dXdlaSAoTyk7IENhdGFsaW4gTWFyaW5hczsgV2ls bCBEZWFjb247IFZpbmF5YWsgSG9saWthdHRpOyBKYW1lcyBFLkouIEJvdHRvbWxleTsgTWFydGlu IEsuIFBldGVyc2VuOyBLZXZpbiBIaWxtYW47IEdyZWdvcnkgQ0xFTUVOVDsgVGhvbWFzIFBldGF6 em9uaTsgTWFzYWhpcm8gWWFtYWRhOyBSaWt1IFZvaXBpbzsgVGhpZXJyeSBSZWRpbmc7IEtyenlz enRvZiBLb3psb3dza2k7IEVyaWMgQW5ob2x0OyBEVE1MOyBMaW51eCBLZXJuZWwgTWFpbGluZyBM aXN0OyBMaW51eCBBUk07IGxpbnV4LXNjc2k7IHphbmdsZWlnYW5nOyBHZW5namlhbmZlbmc7IEd1 b2RvbmcgWHU7IFpoYW5nZmVpIEdhbzsgRmVuZ2Jhb3BlbmcgKGtldmluLCBLaXJpbiBTb2x1dGlv biBEZXB0KTsgWWFuaXYgR2FyZGkNCuS4u+mimDog562U5aSNOiDnrZTlpI06IOetlOWkjTogW1BB VENIIHY4IDIvNV0gZHQtYmluZGluZ3M6IHNjc2k6IHVmczogYWRkIGRvY3VtZW50IGZvciBoaXNp LXVmcw0KDQpIaSwgQXJuZA0KDQpJJ2xsIGFzayBvdXIgc29jIGNvbGxlYWd1ZXMgZm9yIGhlbHAg YW5kIGdpdmUgYSBkZXRhaWxlZCBhbmQgYWNjdXJhdGUgZXhwbGFuYXRpb24gYW9zcC4NCg0KVGhh bmtzIQ0KDQoNCi0tLS0t6YKu5Lu25Y6f5Lu2LS0tLS0NCuWPkeS7tuS6ujogYXJuZGJlcmdtYW5u QGdtYWlsLmNvbSBbbWFpbHRvOmFybmRiZXJnbWFubkBnbWFpbC5jb21dIOS7o+ihqCBBcm5kIEJl cmdtYW5uDQrlj5HpgIHml7bpl7Q6IDIwMTjlubQz5pyIMjbml6UgMTg6NDINCuaUtuS7tuS6ujog bGl3ZWkgKENNKQ0K5oqE6YCBOiBSb2IgSGVycmluZzsgTWFyayBSdXRsYW5kOyB4dXdlaSAoTyk7 IENhdGFsaW4gTWFyaW5hczsgV2lsbCBEZWFjb247IFZpbmF5YWsgSG9saWthdHRpOyBKYW1lcyBF LkouIEJvdHRvbWxleTsgTWFydGluIEsuIFBldGVyc2VuOyBLZXZpbiBIaWxtYW47IEdyZWdvcnkg Q0xFTUVOVDsgVGhvbWFzIFBldGF6em9uaTsgTWFzYWhpcm8gWWFtYWRhOyBSaWt1IFZvaXBpbzsg VGhpZXJyeSBSZWRpbmc7IEtyenlzenRvZiBLb3psb3dza2k7IEVyaWMgQW5ob2x0OyBEVE1MOyBM aW51eCBLZXJuZWwgTWFpbGluZyBMaXN0OyBMaW51eCBBUk07IGxpbnV4LXNjc2k7IHphbmdsZWln YW5nOyBHZW5namlhbmZlbmc7IEd1b2RvbmcgWHU7IFpoYW5nZmVpIEdhbzsgRmVuZ2Jhb3Blbmcg KGtldmluLCBLaXJpbiBTb2x1dGlvbiBEZXB0KTsgWWFuaXYgR2FyZGkNCuS4u+mimDogUmU6IOet lOWkjTog562U5aSNOiBbUEFUQ0ggdjggMi81XSBkdC1iaW5kaW5nczogc2NzaTogdWZzOiBhZGQg ZG9jdW1lbnQgZm9yIGhpc2ktdWZzDQoNCk9uIE1vbiwgTWFyIDI2LCAyMDE4IGF0IDEyOjI2IFBN LCBsaXdlaSAoQ00pIDxsaXdlaTIxM0BodWF3ZWkuY29tPiB3cm90ZToNCj4g5Y+R5Lu25Lq6OiBh cm5kYmVyZ21hbm5AZ21haWwuY29tIFttYWlsdG86YXJuZGJlcmdtYW5uQGdtYWlsLmNvbV0g5Luj 6KGoIEFybmQgDQo+IEJlcmdtYW5uDQo+ID4g5Li76aKYOiBSZTog562U5aSNOiBbUEFUQ0ggdjgg Mi81XSBkdC1iaW5kaW5nczogc2NzaTogdWZzOiBhZGQgZG9jdW1lbnQgZm9yIA0KPiA+IGhpc2kt dWZzIE9uIEZyaSwgTWFyIDIzLCAyMDE4IGF0IDM6MjIgQU0sIGxpd2VpIChDTSkgPGxpd2VpMjEz QGh1YXdlaS5jb20+IHdyb3RlOg0KPiA+PiBUaGUgY2xvY2sgbmFtZXMgc291bmQgZ2VuZXJpYyBl bm91Z2gsIHNob3VsZCB3ZSBoYXZlIGJvdGggaW4gdGhlIGdlbmVyaWMgYmluZGluZz8NCj4gPj4N Cj4gPj4gRG8geW91IG1lYW4gdGhhdCBhZGQgYSAicGh5X2NsayIgdG8gdWZzaGNkLXBsdGZybSAn cyBiaW5kaW5ncz8NCj4gPj4gQXQgcHJlc2VudCwgaXQgc2VlbXMgdGhhdCBpbiB0aGUgaW1wbGVt ZW50YXRpb24gb2YgZ2VuZXJpYyBjb2RlLCANCj4gPj4gYXBhcnQgZnJvbSAicmVmX2NsayIgbWF5 IGhhdmUgc3BlY2lhbCBwcm9jZXNzaW5nLCBvdGhlciBjbGsgd2lsbCANCj4gPj4gbm90IGhhdmUg c3BlY2lhbCBwcm9jZXNzaW5nIGFuZCBzaW1wbHkgcGFyc2UgYW5kIGVuYWJsZTsgUmVmZXJyaW5n IA0KPiA+PiB0byB1ZnMtcWNvbSBiaW5kaW5nLCBJIHRoaW5rICJwaHlfY2xrIiBjYW4gYmUgbmFt ZWQgImlmYWNlX2NsayIsIA0KPiA+PiB0aGlzICJpZmFjZV9jbGsiIGV4aXN0cyBpbiB1ZnNoY2Qt cGx0ZnJtIGJpbmRpbmdzO0lmIHNvLCAicmVmX2NsayIsICJpZmFjZV9jbGsiIGFyZSBib3RoIGlu IHRoZSBnZW5lcmljIGJpbmRpbmcsd2Ugd2lsbCByZW1vdmUgdGhlbSBoZXJlLiBJcyB0aGF0IG9r YXk/DQo+DQo+ID4gSSdtIGxvb2tpbmcgYXQgdGhlIGdlbmVyaWMgYmluZGluZyBhZ2FpbiwgYW5k IGl0IHNlZW1zIHdlIG5ldmVyIA0KPiA+IHF1aXRlIG1hbmFnZWQgdG8gZml4IHNvbWUgbWlub3Ig cHJvYmxlbXMgd2l0aCBpdC4gU2VlIGJlbG93IGZvciBhIHBvc3NpYmxlIHdheSB0byBjbGFyaWZ5 IGl0Lg0KPg0KPiBwaHlfY2xrIGlzIGFjdHVhbGx5IGdpdmVuIHRvIHRoZSBwaHkuIEJ1dCBhcyBw cmV2aW91c2x5IG1lbnRpb25lZCAsIHdlIA0KPiBkbyBub3QgaGF2ZSBhIHNlcGFyYXRlIHBoeSB0 byBjb25maWd1cmUgOyBUaGUgY2xrcyBpbiB0aGUgcGF0Y2ggeW91IA0KPiBnaXZlIGFwcGVhciB0 byBiZSB1bnN1aXRhYmxlIGZvciBkZXNjcmliaW5nIHRoaXMgLg0KPiBIZXJlIHdlIGNhbid0IGRl c2NyaWJlIHBoeV9jbGsgaW4gdGhlIG5vZGUgInVmc3BoeTE6IHVmc3BoeUBmYzU5NzAwMCIgbGlr ZSBxY29tLg0KPiBTbyBjYW4gd2UgcHV0IGl0IGhlcmUgaW4gb3VyIG93biBiaW5kaW5nIGxpa2Ug dGhpcz8NCg0KSSB0aGluayB0aGUgY29uY2VwdCBvZiBoYXZpbmcgYSBwaHkgY2xrIGlzIGdlbmVy aWMgZW5vdWdoIHRoYXQgaXQncyBiZXR0ZXIgdG8gaGF2ZSB0aGF0IGluIHRoZSBjb21tb24gcGFy dCwgb3RoZXJzIHdpbGwgc3VyZWx5IGhhdmUgdGhlIHNhbWUgdGhpbmcsIGFuZCBpbiB0aGlzIGNh c2UsIHFjb20gd291bGQgYmUgdGhlIGV4Y2VwdGlvbiB0aGF0IGRvZXMgbm90IHVzZSBvbmUuDQoN ClRoZXJlIGFyZSBhcHBhcmVudGx5IGEgY291cGxlIG9mIHRoaW5ncyByZWxhdGVkIHRvIHRoZSBw aHkgdGhhdCBtYXkgb3IgbWF5IG5vdCByZXF1aXJlIGEgY2xrOg0KDQotIHJlZl9jbGs6IFRoZSBy ZWZlcmVuY2UgY2xvY2sgb24gdGhlIG1pcGkgYnVzLCB0aGlzIGlzIHdoYXQgcWNvbSBoYXZlLCB0 aGlzIHdvdWxkDQogIGJlIHRoZSAxOS4yIE1IeiBjbG9jayBzaWduYWwuDQotIG9uZSBjbG9jayB0 byBkcml2ZSB0aGUgbG9naWMgYmxvY2sgZm9yIHRoZSBQSFkgaXRzZWxmLCBpZiBpdCBpcyBpbmNs dWRlZCB3aXRoaW4NCiAgdGhlIHNhbWUgbG9naWNhbCBwb3J0aW9uIG9mIGFuIFNvQyBhcyB0aGUg dWZzaGNkLCBidXQgdXNlcyBhIHNlcGFyYXRlIGNsb2NrLg0KLSBMb29raW5nIGF0IHRoZSBBbmRy b2lkIGtlcm5lbCBhcyBkaXN0cmlidXRlZCBieSBnb29nbGUvcXVhbGNvbW0sIHRoZXkgaGF2ZQ0K ICBmb3VyIHNlcGFyYXRlIGNsb2NrcyBkZXNjcmliZWQgYXMNCg0KICAgIFBIWSB0byBjb250cm9s bGVyIHN5bWJvbCBzeW5jaHJvbml6YXRpb24gY2xvY2tzOg0KICAgICAgICAicnhfbGFuZTBfc3lu Y19jbGsiIC0gUlggTGFuZSAwDQogICAgICAgICJyeF9sYW5lMV9zeW5jX2NsayIgLSBSWCBMYW5l IDENCiAgICAgICAgInR4X2xhbmUwX3N5bmNfY2xrIiAtIFRYIExhbmUgMA0KICAgICAgICAidHhf bGFuZTFfc3luY19jbGsiIC0gVFggTGFuZSAxDQoNCldoaWNoIG9mIHRoZSBhYm92ZSB3b3VsZCB5 b3VyIHBoeV9jbGsgcmVmZXIgdG8/DQoNCiAgICAgICBBcm5kDQoNClsxXSBodHRwczovL2FuZHJv aWQuZ29vZ2xlc291cmNlLmNvbS9rZXJuZWwvbXNtLysvYW5kcm9pZC1tc20tYnVsbGhlYWQtMy4x MC1tYXJzaG1hbGxvdy1kci9Eb2N1bWVudGF0aW9uL2RldmljZXRyZWUvYmluZGluZ3MvdWZzL3Vm c2hjZC1wbHRmcm0udHh0P2F1dG9kaXZlPTAlMkYlMkYlMkYlMkYlMkYNCg== From mboxrd@z Thu Jan 1 00:00:00 1970 From: liwei213@huawei.com (liwei (CM)) Date: Tue, 27 Mar 2018 06:15:15 +0000 Subject: =?utf-8?B?562U5aSNOiDnrZTlpI06IOetlOWkjTogW1BBVENIIHY4IDIvNV0gZHQtYmlu?= =?utf-8?Q?dings:_scsi:_ufs:_add_document_for_hisi-ufs?= References: <20180213101412.5717-1-liwei213@huawei.com> <20180213101412.5717-3-liwei213@huawei.com> <1699CE87DE933F49876AD744B5DC140FA584ED@DGGEMM506-MBS.china.huawei.com> <1699CE87DE933F49876AD744B5DC140FA58798@DGGEMM506-MBS.china.huawei.com> Message-ID: <1699CE87DE933F49876AD744B5DC140FA588AD@DGGEMM506-MBS.china.huawei.com> To: linux-arm-kernel@lists.infradead.org List-Id: linux-arm-kernel.lists.infradead.org Hi, Arnd At present our ufs module mainly has four clocks from the outside: hclk_ufs: main clock of ufs controller ,freq is 207.5MHz cfg_phy_clk: configuration clock of MPHY, freq is 51.875MHz ref_phy_clk: reference clock of MPHY from PMU, freq is 19.2MHz ref_io_clk: reference clock for the external interface to the device, freq is 19.2MHz We control two clocks "ref_io_clk" and "cfg_phy_clk" in the driver because the other two are controlled by main clock module and pmu. for this patch, cfg_phy_clk corresponds to "phy_clk", ref_io_clk corresponds to "ref_clk". So the clks in the patch you give appear to be unsuitable for describing this .And the following clks of qcom are internal clock? We didn't describe or pay attention to the clock inside the ufs module. PHY to controller symbol synchronization clocks: "rx_lane0_sync_clk" - RX Lane 0 "rx_lane1_sync_clk" - RX Lane 1 "tx_lane0_sync_clk" - TX Lane 0 "tx_lane1_sync_clk" - TX Lane 1 -----????----- ???: liwei (CM) ????: 2018?3?26? 20:02 ???: 'Arnd Bergmann' ??: Rob Herring; Mark Rutland; xuwei (O); Catalin Marinas; Will Deacon; Vinayak Holikatti; James E.J. Bottomley; Martin K. Petersen; Kevin Hilman; Gregory CLEMENT; Thomas Petazzoni; Masahiro Yamada; Riku Voipio; Thierry Reding; Krzysztof Kozlowski; Eric Anholt; DTML; Linux Kernel Mailing List; Linux ARM; linux-scsi; zangleigang; Gengjianfeng; Guodong Xu; Zhangfei Gao; Fengbaopeng (kevin, Kirin Solution Dept); Yaniv Gardi ??: ??: ??: ??: [PATCH v8 2/5] dt-bindings: scsi: ufs: add document for hisi-ufs Hi, Arnd I'll ask our soc colleagues for help and give a detailed and accurate explanation aosp. Thanks! -----????----- ???: arndbergmann at gmail.com [mailto:arndbergmann at gmail.com] ?? Arnd Bergmann ????: 2018?3?26? 18:42 ???: liwei (CM) ??: Rob Herring; Mark Rutland; xuwei (O); Catalin Marinas; Will Deacon; Vinayak Holikatti; James E.J. Bottomley; Martin K. Petersen; Kevin Hilman; Gregory CLEMENT; Thomas Petazzoni; Masahiro Yamada; Riku Voipio; Thierry Reding; Krzysztof Kozlowski; Eric Anholt; DTML; Linux Kernel Mailing List; Linux ARM; linux-scsi; zangleigang; Gengjianfeng; Guodong Xu; Zhangfei Gao; Fengbaopeng (kevin, Kirin Solution Dept); Yaniv Gardi ??: Re: ??: ??: [PATCH v8 2/5] dt-bindings: scsi: ufs: add document for hisi-ufs On Mon, Mar 26, 2018 at 12:26 PM, liwei (CM) wrote: > ???: arndbergmann at gmail.com [mailto:arndbergmann at gmail.com] ?? Arnd > Bergmann > > ??: Re: ??: [PATCH v8 2/5] dt-bindings: scsi: ufs: add document for > > hisi-ufs On Fri, Mar 23, 2018 at 3:22 AM, liwei (CM) wrote: > >> The clock names sound generic enough, should we have both in the generic binding? > >> > >> Do you mean that add a "phy_clk" to ufshcd-pltfrm 's bindings? > >> At present, it seems that in the implementation of generic code, > >> apart from "ref_clk" may have special processing, other clk will > >> not have special processing and simply parse and enable; Referring > >> to ufs-qcom binding, I think "phy_clk" can be named "iface_clk", > >> this "iface_clk" exists in ufshcd-pltfrm bindings;If so, "ref_clk", "iface_clk" are both in the generic binding,we will remove them here. Is that okay? > > > I'm looking at the generic binding again, and it seems we never > > quite managed to fix some minor problems with it. See below for a possible way to clarify it. > > phy_clk is actually given to the phy. But as previously mentioned , we > do not have a separate phy to configure ; The clks in the patch you > give appear to be unsuitable for describing this . > Here we can't describe phy_clk in the node "ufsphy1: ufsphy at fc597000" like qcom. > So can we put it here in our own binding like this? I think the concept of having a phy clk is generic enough that it's better to have that in the common part, others will surely have the same thing, and in this case, qcom would be the exception that does not use one. There are apparently a couple of things related to the phy that may or may not require a clk: - ref_clk: The reference clock on the mipi bus, this is what qcom have, this would be the 19.2 MHz clock signal. - one clock to drive the logic block for the PHY itself, if it is included within the same logical portion of an SoC as the ufshcd, but uses a separate clock. - Looking at the Android kernel as distributed by google/qualcomm, they have four separate clocks described as PHY to controller symbol synchronization clocks: "rx_lane0_sync_clk" - RX Lane 0 "rx_lane1_sync_clk" - RX Lane 1 "tx_lane0_sync_clk" - TX Lane 0 "tx_lane1_sync_clk" - TX Lane 1 Which of the above would your phy_clk refer to? Arnd [1] https://android.googlesource.com/kernel/msm/+/android-msm-bullhead-3.10-marshmallow-dr/Documentation/devicetree/bindings/ufs/ufshcd-pltfrm.txt?autodive=0%2F%2F%2F%2F%2F