From mboxrd@z Thu Jan 1 00:00:00 1970 From: Jaeyong Yoo Subject: Re: [PATCH] ARM: cache coherence problem in guestcopy.c Date: Tue, 18 Jun 2013 12:05:47 +0000 (GMT) Message-ID: <17177098.345811371557146762.JavaMail.weblogic@epv6ml06> Reply-To: jaeyong.yoo@samsung.com Mime-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Return-path: MIME-version: 1.0 List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Sender: xen-devel-bounces@lists.xen.org Errors-To: xen-devel-bounces@lists.xen.org To: Ian Campbell Cc: Tim Deegan , "xen-devel@lists.xen.org" List-Id: xen-devel@lists.xenproject.org > > But all of the caches on this platform are PIPT (right?) so isn't it > actually: > > (consumer) (producer) > xen DomU > \ / (writing path) > \ / > \ / > (reading path) \ / > \ / > (cache) > || > || > \/ > _______________________________________ > | mfn | (physical memory) > --------------------------------------- > > > Or are you saying that the writing path is uncached? Oops my mistake. As far as I know, it is PIPT and the writing also should be cached. > > I was chatting with Tim and he suggested that the issue might be the > ReOrder Buffer, which is virtually tagged. In that case a DMB ought to > be sufficient and not a full cache flush, we think. > > We were also speculating that we probably want some DMBs in > context_switch_{from,to} as well as at return_to_guest. Actually, I just learned ReOrder Buffer, and it looks like so. Best, Jaeyong