From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-14.0 required=3.0 tests=BAYES_00,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 024FEC64E68 for ; Mon, 19 Jul 2021 15:57:39 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id E4D9F6146D for ; Mon, 19 Jul 2021 15:57:39 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1345832AbhGSPQu (ORCPT ); Mon, 19 Jul 2021 11:16:50 -0400 Received: from mail.kernel.org ([198.145.29.99]:56116 "EHLO mail.kernel.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1347272AbhGSPP4 (ORCPT ); Mon, 19 Jul 2021 11:15:56 -0400 Received: from disco-boy.misterjones.org (disco-boy.misterjones.org [51.254.78.96]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPSA id 033F6601FD; Mon, 19 Jul 2021 15:56:36 +0000 (UTC) Received: from disco-boy.misterjones.org ([51.254.78.96] helo=www.loen.fr) by disco-boy.misterjones.org with esmtpsa (TLS1.2) tls TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256 (Exim 4.94.2) (envelope-from ) id 1m5VdC-00EGXH-BP; Mon, 19 Jul 2021 16:56:34 +0100 MIME-Version: 1.0 Content-Type: text/plain; charset=US-ASCII; format=flowed Content-Transfer-Encoding: 7bit Date: Mon, 19 Jul 2021 16:56:34 +0100 From: Marc Zyngier To: Alexandru Elisei Cc: linux-arm-kernel@lists.infradead.org, kvm@vger.kernel.org, kvmarm@lists.cs.columbia.edu, James Morse , Suzuki K Poulose , Alexandre Chartre , Robin Murphy , Andrew Jones , Russell King , kernel-team@android.com, Russell King Subject: Re: [PATCH v2 1/4] KVM: arm64: Narrow PMU sysreg reset values to architectural requirements In-Reply-To: <171cca9d-2a6e-248c-8502-feba8ebbe55e@arm.com> References: <20210719123902.1493805-1-maz@kernel.org> <20210719123902.1493805-2-maz@kernel.org> <171cca9d-2a6e-248c-8502-feba8ebbe55e@arm.com> User-Agent: Roundcube Webmail/1.4.11 Message-ID: <171834f3198b898d5c2aefa0270b65f2@kernel.org> X-Sender: maz@kernel.org X-SA-Exim-Connect-IP: 51.254.78.96 X-SA-Exim-Rcpt-To: alexandru.elisei@arm.com, linux-arm-kernel@lists.infradead.org, kvm@vger.kernel.org, kvmarm@lists.cs.columbia.edu, james.morse@arm.com, suzuki.poulose@arm.com, alexandre.chartre@oracle.com, robin.murphy@arm.com, drjones@redhat.com, linux@arm.linux.org.uk, kernel-team@android.com, rmk+kernel@armlinux.org.uk X-SA-Exim-Mail-From: maz@kernel.org X-SA-Exim-Scanned: No (on disco-boy.misterjones.org); SAEximRunCond expanded to false Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org On 2021-07-19 16:55, Alexandru Elisei wrote: > Hi Marc, > > On 7/19/21 1:38 PM, Marc Zyngier wrote: >> A number of the PMU sysregs expose reset values that are not >> compliant with the architecture (set bits in the RES0 ranges, >> for example). >> >> This in turn has the effect that we need to pointlessly mask >> some register fields when using them. >> >> Let's start by making sure we don't have illegal values in the >> shadow registers at reset time. This affects all the registers >> that dedicate one bit per counter, the counters themselves, >> PMEVTYPERn_EL0 and PMSELR_EL0. >> >> Reported-by: Alexandre Chartre >> Reviewed-by: Alexandre Chartre >> Acked-by: Russell King (Oracle) >> Signed-off-by: Marc Zyngier >> --- >> arch/arm64/kvm/sys_regs.c | 43 >> ++++++++++++++++++++++++++++++++++++--- >> 1 file changed, 40 insertions(+), 3 deletions(-) >> >> diff --git a/arch/arm64/kvm/sys_regs.c b/arch/arm64/kvm/sys_regs.c >> index f6f126eb6ac1..96bdfa0e68b2 100644 >> --- a/arch/arm64/kvm/sys_regs.c >> +++ b/arch/arm64/kvm/sys_regs.c >> @@ -603,6 +603,41 @@ static unsigned int pmu_visibility(const struct >> kvm_vcpu *vcpu, >> return REG_HIDDEN; >> } >> >> +static void reset_pmu_reg(struct kvm_vcpu *vcpu, const struct >> sys_reg_desc *r) >> +{ >> + u64 n, mask = BIT(ARMV8_PMU_CYCLE_IDX); >> + >> + /* No PMU available, any PMU reg may UNDEF... */ >> + if (!kvm_arm_support_pmu_v3()) >> + return; >> + >> + n = read_sysreg(pmcr_el0) >> ARMV8_PMU_PMCR_N_SHIFT; >> + n &= ARMV8_PMU_PMCR_N_MASK; >> + if (n) >> + mask |= GENMASK(n - 1, 0); > > Hm... seems to be missing the cycle counter. Check the declaration for 'mask'... :-) M. -- Jazz is not dead. It just smells funny... From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-14.0 required=3.0 tests=BAYES_00,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id A54DBC07E95 for ; Mon, 19 Jul 2021 15:56:43 +0000 (UTC) Received: from mm01.cs.columbia.edu (mm01.cs.columbia.edu [128.59.11.253]) by mail.kernel.org (Postfix) with ESMTP id 13FC560FDA for ; Mon, 19 Jul 2021 15:56:42 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 13FC560FDA Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=kernel.org Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=kvmarm-bounces@lists.cs.columbia.edu Received: from localhost (localhost [127.0.0.1]) by mm01.cs.columbia.edu (Postfix) with ESMTP id 9A11E4A126; Mon, 19 Jul 2021 11:56:42 -0400 (EDT) X-Virus-Scanned: at lists.cs.columbia.edu Received: from mm01.cs.columbia.edu ([127.0.0.1]) by localhost (mm01.cs.columbia.edu [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id V-jrQbOgK44i; Mon, 19 Jul 2021 11:56:40 -0400 (EDT) Received: from mm01.cs.columbia.edu (localhost [127.0.0.1]) by mm01.cs.columbia.edu (Postfix) with ESMTP id 3107C49F8F; Mon, 19 Jul 2021 11:56:40 -0400 (EDT) Received: from localhost (localhost [127.0.0.1]) by mm01.cs.columbia.edu (Postfix) with ESMTP id 47A0249F8F for ; Mon, 19 Jul 2021 11:56:39 -0400 (EDT) X-Virus-Scanned: at lists.cs.columbia.edu Received: from mm01.cs.columbia.edu ([127.0.0.1]) by localhost (mm01.cs.columbia.edu [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id 7TAU+nVkwMAB for ; Mon, 19 Jul 2021 11:56:37 -0400 (EDT) Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by mm01.cs.columbia.edu (Postfix) with ESMTPS id 4EB6540895 for ; Mon, 19 Jul 2021 11:56:37 -0400 (EDT) Received: from disco-boy.misterjones.org (disco-boy.misterjones.org [51.254.78.96]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPSA id 033F6601FD; Mon, 19 Jul 2021 15:56:36 +0000 (UTC) Received: from disco-boy.misterjones.org ([51.254.78.96] helo=www.loen.fr) by disco-boy.misterjones.org with esmtpsa (TLS1.2) tls TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256 (Exim 4.94.2) (envelope-from ) id 1m5VdC-00EGXH-BP; Mon, 19 Jul 2021 16:56:34 +0100 MIME-Version: 1.0 Date: Mon, 19 Jul 2021 16:56:34 +0100 From: Marc Zyngier To: Alexandru Elisei Subject: Re: [PATCH v2 1/4] KVM: arm64: Narrow PMU sysreg reset values to architectural requirements In-Reply-To: <171cca9d-2a6e-248c-8502-feba8ebbe55e@arm.com> References: <20210719123902.1493805-1-maz@kernel.org> <20210719123902.1493805-2-maz@kernel.org> <171cca9d-2a6e-248c-8502-feba8ebbe55e@arm.com> User-Agent: Roundcube Webmail/1.4.11 Message-ID: <171834f3198b898d5c2aefa0270b65f2@kernel.org> X-Sender: maz@kernel.org X-SA-Exim-Connect-IP: 51.254.78.96 X-SA-Exim-Rcpt-To: alexandru.elisei@arm.com, linux-arm-kernel@lists.infradead.org, kvm@vger.kernel.org, kvmarm@lists.cs.columbia.edu, james.morse@arm.com, suzuki.poulose@arm.com, alexandre.chartre@oracle.com, robin.murphy@arm.com, drjones@redhat.com, linux@arm.linux.org.uk, kernel-team@android.com, rmk+kernel@armlinux.org.uk X-SA-Exim-Mail-From: maz@kernel.org X-SA-Exim-Scanned: No (on disco-boy.misterjones.org); SAEximRunCond expanded to false Cc: kvm@vger.kernel.org, kernel-team@android.com, Russell King , Russell King , Robin Murphy , kvmarm@lists.cs.columbia.edu, linux-arm-kernel@lists.infradead.org X-BeenThere: kvmarm@lists.cs.columbia.edu X-Mailman-Version: 2.1.14 Precedence: list List-Id: Where KVM/ARM decisions are made List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Transfer-Encoding: 7bit Content-Type: text/plain; charset="us-ascii"; Format="flowed" Errors-To: kvmarm-bounces@lists.cs.columbia.edu Sender: kvmarm-bounces@lists.cs.columbia.edu On 2021-07-19 16:55, Alexandru Elisei wrote: > Hi Marc, > > On 7/19/21 1:38 PM, Marc Zyngier wrote: >> A number of the PMU sysregs expose reset values that are not >> compliant with the architecture (set bits in the RES0 ranges, >> for example). >> >> This in turn has the effect that we need to pointlessly mask >> some register fields when using them. >> >> Let's start by making sure we don't have illegal values in the >> shadow registers at reset time. This affects all the registers >> that dedicate one bit per counter, the counters themselves, >> PMEVTYPERn_EL0 and PMSELR_EL0. >> >> Reported-by: Alexandre Chartre >> Reviewed-by: Alexandre Chartre >> Acked-by: Russell King (Oracle) >> Signed-off-by: Marc Zyngier >> --- >> arch/arm64/kvm/sys_regs.c | 43 >> ++++++++++++++++++++++++++++++++++++--- >> 1 file changed, 40 insertions(+), 3 deletions(-) >> >> diff --git a/arch/arm64/kvm/sys_regs.c b/arch/arm64/kvm/sys_regs.c >> index f6f126eb6ac1..96bdfa0e68b2 100644 >> --- a/arch/arm64/kvm/sys_regs.c >> +++ b/arch/arm64/kvm/sys_regs.c >> @@ -603,6 +603,41 @@ static unsigned int pmu_visibility(const struct >> kvm_vcpu *vcpu, >> return REG_HIDDEN; >> } >> >> +static void reset_pmu_reg(struct kvm_vcpu *vcpu, const struct >> sys_reg_desc *r) >> +{ >> + u64 n, mask = BIT(ARMV8_PMU_CYCLE_IDX); >> + >> + /* No PMU available, any PMU reg may UNDEF... */ >> + if (!kvm_arm_support_pmu_v3()) >> + return; >> + >> + n = read_sysreg(pmcr_el0) >> ARMV8_PMU_PMCR_N_SHIFT; >> + n &= ARMV8_PMU_PMCR_N_MASK; >> + if (n) >> + mask |= GENMASK(n - 1, 0); > > Hm... seems to be missing the cycle counter. Check the declaration for 'mask'... :-) M. -- Jazz is not dead. It just smells funny... _______________________________________________ kvmarm mailing list kvmarm@lists.cs.columbia.edu https://lists.cs.columbia.edu/mailman/listinfo/kvmarm From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-15.5 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,INCLUDES_CR_TRAILER,INCLUDES_PATCH,MAILING_LIST_MULTI, SPF_HELO_NONE,SPF_PASS autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id A9081C12002 for ; Mon, 19 Jul 2021 15:58:19 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 7B33261419 for ; Mon, 19 Jul 2021 15:58:19 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 7B33261419 Authentication-Results: mail.kernel.org; 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SAEximRunCond expanded to false X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20210719_085636_450465_E7E80E8F X-CRM114-Status: GOOD ( 19.00 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Transfer-Encoding: 7bit Content-Type: text/plain; charset="us-ascii"; Format="flowed" Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On 2021-07-19 16:55, Alexandru Elisei wrote: > Hi Marc, > > On 7/19/21 1:38 PM, Marc Zyngier wrote: >> A number of the PMU sysregs expose reset values that are not >> compliant with the architecture (set bits in the RES0 ranges, >> for example). >> >> This in turn has the effect that we need to pointlessly mask >> some register fields when using them. >> >> Let's start by making sure we don't have illegal values in the >> shadow registers at reset time. This affects all the registers >> that dedicate one bit per counter, the counters themselves, >> PMEVTYPERn_EL0 and PMSELR_EL0. >> >> Reported-by: Alexandre Chartre >> Reviewed-by: Alexandre Chartre >> Acked-by: Russell King (Oracle) >> Signed-off-by: Marc Zyngier >> --- >> arch/arm64/kvm/sys_regs.c | 43 >> ++++++++++++++++++++++++++++++++++++--- >> 1 file changed, 40 insertions(+), 3 deletions(-) >> >> diff --git a/arch/arm64/kvm/sys_regs.c b/arch/arm64/kvm/sys_regs.c >> index f6f126eb6ac1..96bdfa0e68b2 100644 >> --- a/arch/arm64/kvm/sys_regs.c >> +++ b/arch/arm64/kvm/sys_regs.c >> @@ -603,6 +603,41 @@ static unsigned int pmu_visibility(const struct >> kvm_vcpu *vcpu, >> return REG_HIDDEN; >> } >> >> +static void reset_pmu_reg(struct kvm_vcpu *vcpu, const struct >> sys_reg_desc *r) >> +{ >> + u64 n, mask = BIT(ARMV8_PMU_CYCLE_IDX); >> + >> + /* No PMU available, any PMU reg may UNDEF... */ >> + if (!kvm_arm_support_pmu_v3()) >> + return; >> + >> + n = read_sysreg(pmcr_el0) >> ARMV8_PMU_PMCR_N_SHIFT; >> + n &= ARMV8_PMU_PMCR_N_MASK; >> + if (n) >> + mask |= GENMASK(n - 1, 0); > > Hm... seems to be missing the cycle counter. Check the declaration for 'mask'... :-) M. -- Jazz is not dead. It just smells funny... _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel