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From: Alistair Francis <alistair.francis@wdc.com>
To: qemu-devel@nongnu.org
Cc: alistair.francis@wdc.com, alistair23@gmail.com, mjc@sifive.com
Subject: [Qemu-devel] [PATCH v3 6/7] hw/riscv/sifive_u: Move the uart device tree node under /soc/
Date: Mon, 14 May 2018 17:08:00 -0700	[thread overview]
Message-ID: <17849c31b5b8e57e2ae61852edae8791f672801c.1526342674.git.alistair.francis@wdc.com> (raw)
In-Reply-To: <cover.1526342674.git.alistair.francis@wdc.com>

Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Michael Clark <mjc@sifive.com>
---
 hw/riscv/sifive_u.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c
index f71527eaff..46459cd368 100644
--- a/hw/riscv/sifive_u.c
+++ b/hw/riscv/sifive_u.c
@@ -194,7 +194,7 @@ static void create_fdt(SiFiveUState *s, const struct MemmapEntry *memmap,
     g_free(cells);
     g_free(nodename);
 
-    nodename = g_strdup_printf("/uart@%lx",
+    nodename = g_strdup_printf("/soc/uart@%lx",
         (long)memmap[SIFIVE_U_UART0].base);
     qemu_fdt_add_subnode(fdt, nodename);
     qemu_fdt_setprop_string(fdt, nodename, "compatible", "sifive,uart0");
-- 
2.17.0

  parent reply	other threads:[~2018-05-15  0:08 UTC|newest]

Thread overview: 11+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2018-05-15  0:06 [Qemu-devel] [PATCH v3 0/7] RISC-V: SoCify SiFive boards and connect GEM Alistair Francis
2018-05-15  0:06 ` [Qemu-devel] [PATCH v3 1/7] hw/riscv/sifive_u: Create a SiFive U SoC object Alistair Francis
2018-05-15  0:07 ` [Qemu-devel] [PATCH v3 2/7] hw/riscv/sifive_e: Create a SiFive E " Alistair Francis
2018-05-18  2:12   ` Michael Clark
2018-05-15  0:07 ` [Qemu-devel] [PATCH v3 3/7] hw/riscv/sifive_plic: Use gpios instead of irqs Alistair Francis
2018-05-15  0:07 ` [Qemu-devel] [PATCH v3 4/7] hw/riscv/sifive_u: Set the soc device tree node as a simple-bus Alistair Francis
2018-05-18  2:12   ` Michael Clark
2018-05-18 16:49     ` Alistair Francis
2018-05-15  0:07 ` [Qemu-devel] [PATCH v3 5/7] hw/riscv/sifive_u: Set the interrupt controler number of interrupts Alistair Francis
2018-05-15  0:08 ` Alistair Francis [this message]
2018-05-15  0:08 ` [Qemu-devel] [PATCH v3 7/7] hw/riscv/sifive_u: Connect the Cadence GEM Ethernet device Alistair Francis

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