From mboxrd@z Thu Jan 1 00:00:00 1970 From: Thomas Monjalon Subject: Re: [PATCH] eal/ppc: remove fix of memory barrier for IBM POWER Date: Wed, 27 Mar 2019 10:19:03 +0100 Message-ID: <1793899.zbSyOp9Bm4@xps> References: <1552913893-43407-1-git-send-email-dekelp@mellanox.com> Mime-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7Bit Cc: dev@dpdk.org, Dekel Peled , Shahaf Shuler , "bruce.richardson@intel.com" , David Christensen , "honnappa.nagarahalli@arm.com" , "konstantin.ananyev@intel.com" , "ola.liljedahl@arm.com" , Ori Kam , David Wilder , Yongseok Koh , Idan Werpoler , Olga Shern To: "pradeep@us.ibm.com" , Chao Zhu Return-path: Received: from out3-smtp.messagingengine.com (out3-smtp.messagingengine.com [66.111.4.27]) by dpdk.org (Postfix) with ESMTP id 7E6D04F90 for ; Wed, 27 Mar 2019 10:19:08 +0100 (CET) In-Reply-To: List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" Pradeep, Chao, Do we have more news? We must merge this patch for DPDK 19.05-rc1. I understand you want to try improving performance by using lightweight sync for SMP barrier, and this change can be done later. First priority is to fix the bug of the general barrier. That's why I should push this patch before the end of the week. > Shahaf Shuler > wrote on 03/23/2019 11:37:42 PM: > > From: Shahaf Shuler > > > Pradeep Satyanarayana wrote on Saturday, March 23, 2019 12:58 AM > > >Thomas Monjalon > wrote on 03/22/2019 10:51:17 AM: > > >> 22/03/2019 16:30, Pradeep Satyanarayana: > > >> > Thomas Monjalon > wrote on 03/22/2019 01:49:03 AM: > > >> > > 22/03/2019 02:40, Pradeep Satyanarayana: > > >> > > > - rte_[rw]mb (general memory barrier) --> should be lwsync > > >> > > > > >> > > This is what may be discussed. > > >> > > The assumption is that the general memory barrier should cover > > >> > > all cases (CPU caches, SMP and I/O). > > >> > > That's why we think it should "sync" for Power. > > >> > > > >> > In that case, at a minimum we must de-link rte_smp_[rw]mb from rte_[rw]mb > > >> > and retain it as lwsync. Agreed? > > >> > > >> I have no clue about what is needed for SMP barrier in Power. > > >> As long as it works as expected, no problem. > > >> > > > > > >We will try that out and report back here, later next week > > > > Till then, i think there are 2 orthogonal issues: > > 1. ppc rte_wmb is incorrect > > 2. ppc rte_smp_[rw]mb may be improved. > > > > for #1 the current patch from Dekel seems to be OK. do you agree? > > for #2 i guess you will check and come back w/ patch/answer? > > That has been the line of thinking. However, we need to do some extensive testing > to confirm that it all holds up.