From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:54551) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1WzOaZ-0005tR-Nr for qemu-devel@nongnu.org; Tue, 24 Jun 2014 07:08:41 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1WzOaU-00061U-1k for qemu-devel@nongnu.org; Tue, 24 Jun 2014 07:08:35 -0400 Received: from edge10.ethz.ch ([82.130.75.186]:48363) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1WzOaT-00061M-Nr for qemu-devel@nongnu.org; Tue, 24 Jun 2014 07:08:29 -0400 From: "Aggeler Fabian" Date: Tue, 24 Jun 2014 11:08:27 +0000 Message-ID: <17A34EA1-CB3A-446F-B31F-41073BF5681B@ethz.ch> References: <1402444514-19658-1-git-send-email-aggelerf@ethz.ch> <1402444514-19658-33-git-send-email-aggelerf@ethz.ch> In-Reply-To: Content-Language: en-US Content-Type: text/plain; charset="us-ascii" Content-ID: Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Subject: Re: [Qemu-devel] [PATCH v3 32/32] target-arm: make c13 cp regs banked (FCSEIDR, ...) List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Greg Bellows Cc: Peter Maydell , Peter Crosthwaite , QEMU Developers , Sergey Fedorov , "Edgar E. Iglesias" , Christoffer Dall On 23 Jun 2014, at 23:40, Greg Bellows > wrote: On 10 June 2014 18:55, Fabian Aggeler > wrote: When EL3 is running in Aarch32 (or ARMv7 with Security Extensions) FCSEIDR, CONTEXTIDR, TPIDRURW, TPIDRURO and TPIDRPRW have a secure and a non-secure instance. Signed-off-by: Fabian Aggeler > --- target-arm/cpu.h | 45 ++++++++++++++++++++++++++++++++++++++++----- target-arm/helper.c | 27 +++++++++++++++++---------- 2 files changed, 57 insertions(+), 15 deletions(-) diff --git a/target-arm/cpu.h b/target-arm/cpu.h index c7d606e..13fa966 100644 --- a/target-arm/cpu.h +++ b/target-arm/cpu.h @@ -329,11 +329,46 @@ typedef struct CPUARMState { }; uint64_t vbar_el2; uint64_t mvbar; /* (monitor) vector base address register */ - uint32_t c13_fcse; /* FCSE PID. */ - uint64_t contextidr_el1; /* Context ID. */ - uint64_t tpidr_el0; /* User RW Thread register. */ - uint64_t tpidrro_el0; /* User RO Thread register. */ - uint64_t tpidr_el1; /* Privileged Thread register. */ + struct { /* FCSE PID. */ + uint32_t c13_fcseidr_ns; + uint32_t c13_fcseidr_s; + }; + union { /* Context ID. */ + struct { + uint64_t contextidr_ns; + uint64_t contextidr_s; + }; + struct { + uint64_t contextidr_el1; + }; + }; + union { /* User RW Thread register. */ + struct { + uint64_t tpidrurw_ns; + uint64_t tpidrurw_s; + }; + struct { + uint64_t tpidr_el0; + }; + }; + union { /* User RO Thread register. */ + struct { + uint64_t tpidruro_ns; + uint64_t tpidruro_s; + }; + struct { + uint64_t tpidrro_el0; + }; + }; + union { /* Privileged Thread register. */ + struct { + uint64_t tpidrprw_ns; + uint64_t tpidrprw_s; + }; + struct { + uint64_t tpidr_el1; + }; + }; uint64_t c14_cntfrq; /* Counter Frequency register */ uint64_t c14_cntkctl; /* Timer Control register */ ARMGenericTimer c14_timer[NUM_GTIMERS]; diff --git a/target-arm/helper.c b/target-arm/helper.c index 2d085aa..aebcc62 100644 --- a/target-arm/helper.c +++ b/target-arm/helper.c @@ -396,12 +396,15 @@ static const ARMCPRegInfo cp_reginfo[] =3D { { .name =3D "DBGDIDR", .cp =3D 14, .crn =3D 0, .crm =3D 0, .opc1 =3D 0= , .opc2 =3D 0, .access =3D PL0_R, .type =3D ARM_CP_CONST, .resetvalue =3D 0 }, { .name =3D "FCSEIDR", .cp =3D 15, .crn =3D 13, .crm =3D 0, .opc1 =3D = 0, .opc2 =3D 0, - .access =3D PL1_RW, .fieldoffset =3D offsetof(CPUARMState, cp15.c13_= fcse), + .access =3D PL1_RW, + .bank_fieldoffsets =3D { offsetof(CPUARMState, cp15.c13_fcseidr_s), + offsetof(CPUARMState, cp15.c13_fcseidr_ns) }, .resetvalue =3D 0, .writefn =3D fcse_write, .raw_writefn =3D raw_wri= te, }, { .name =3D "CONTEXTIDR", .state =3D ARM_CP_STATE_BOTH, .opc0 =3D 3, .opc1 =3D 0, .crn =3D 13, .crm =3D 0, .opc2 =3D 1, .access =3D PL1_RW, - .fieldoffset =3D offsetof(CPUARMState, cp15.contextidr_el1), + .bank_fieldoffsets =3D { offsetof(CPUARMState, cp15.contextidr_s), + offsetof(CPUARMState, cp15.contextidr_ns) }, .resetvalue =3D 0, .writefn =3D contextidr_write, .raw_writefn =3D r= aw_write, }, REGINFO_SENTINEL }; @@ -889,21 +892,25 @@ static const ARMCPRegInfo v6k_cp_reginfo[] =3D { .access =3D PL0_RW, .fieldoffset =3D offsetof(CPUARMState, cp15.tpidr_el0), .resetvalue = =3D 0 }, { .name =3D "TPIDRURW", .cp =3D 15, .crn =3D 13, .crm =3D 0, .opc1 =3D= 0, .opc2 =3D 2, - .access =3D PL0_RW, - .fieldoffset =3D offsetoflow32(CPUARMState, cp15.tpidr_el0), - .resetfn =3D arm_cp_reset_ignore }, + .access =3D PL0_RW, .resetfn =3D arm_cp_reset_ignore, + .bank_fieldoffsets =3D { offsetoflow32(CPUARMState, cp15.tpidrurw_s)= , + offsetoflow32(CPUARMState, cp15.tpidrurw_ns) = } }, { .name =3D "TPIDRRO_EL0", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 3, .opc1 =3D 3, .opc2 =3D 3, .crn =3D 13, .crm =3D 0, .access =3D PL0_R|PL1_W, .fieldoffset =3D offsetof(CPUARMState, cp15.tpidrro_el0), .resetvalu= e =3D 0 }, { .name =3D "TPIDRURO", .cp =3D 15, .crn =3D 13, .crm =3D 0, .opc1 =3D= 0, .opc2 =3D 3, - .access =3D PL0_R|PL1_W, - .fieldoffset =3D offsetoflow32(CPUARMState, cp15.tpidrro_el0), - .resetfn =3D arm_cp_reset_ignore }, - { .name =3D "TPIDR_EL1", .state =3D ARM_CP_STATE_BOTH, + .access =3D PL0_R|PL1_W, .resetfn =3D arm_cp_reset_ignore, + .bank_fieldoffsets =3D { offsetoflow32(CPUARMState, cp15.tpidruro_s)= , + offsetoflow32(CPUARMState, cp15.tpidruro_ns) = } }, + { .name =3D "TPIDR_EL1", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 3, .opc1 =3D 0, .opc2 =3D 4, .crn =3D 13, .crm =3D 0, .access =3D PL1_RW, .fieldoffset =3D offsetof(CPUARMState, cp15.tpidr_el1), .resetvalue = =3D 0 }, + { .name =3D "TPIDRPRW", .cp =3D 15, .crn =3D 13, .crm =3D 0, .opc1 =3D= 0, .opc2 =3D 4, + .access =3D PL1_RW, .resetfn =3D arm_cp_reset_ignore, + .bank_fieldoffsets =3D { offsetoflow32(CPUARMState, cp15.tpidruro_s)= , + offsetoflow32(CPUARMState, cp15.tpidruro_ns) = } }, Just discovered that TPIDRPRW is mapped to the wrong storage (tpidruro). S= hould be mapped to tpidrprw. Indeed, should be tpidrprw_s/ns. Good catch! REGINFO_SENTINEL }; @@ -4566,7 +4573,7 @@ static inline int get_phys_addr(CPUARMState *env, tar= get_ulong address, /* Fast Context Switch Extension. */ if (address < 0x02000000) - address +=3D env->cp15.c13_fcse; + address +=3D A32_BANKED_CURRENT_REG_GET(env, c13_fcseidr); if ((sctlr & SCTLR_M) =3D=3D 0) { /* MMU/MPU disabled. */ -- 1.8.3.2