From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 7D7FAC433F5 for ; Fri, 29 Oct 2021 08:49:21 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 46AD061157 for ; Fri, 29 Oct 2021 08:49:21 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.4.1 mail.kernel.org 46AD061157 Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=cqplus1.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-Id:Date:Subject:Cc:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=udC7WCVT4l6yCtEI1fmiPxx1KpXIHz5pjwY4oylRkps=; b=rMz6uJ1GhU1C52 8fLNkU21u5iPuxy45yATEa1OLeN12IBj6Cd0EZeR35K4gHfb4NwT+IKfwb36Lv8GvNl5BiSYe0nvH zZnazNoM88QXHF+jyhckY6apC6ORKVc0mC0PaUlyUcN8FXuSRLZBAaO7pcmnw3ofnPv7MAmYqg9fd TKYec9hOsOpwjPmuIyREpJI9Azzpr0G7XwuNDkkG689G315/pW6hL5Ca38UseyOi40Igg2C0HtlWU 6EUeyNp8RVmw3TyK14BS0TBVCe6JVzVJK73MjJugXwMbSS5WHY/DG/SdaII7+hxl2edHCvOM6S3n1 az3ZCzTC7AIJrGJgLPYA==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1mgNYH-00ALIP-MG; Fri, 29 Oct 2021 08:47:53 +0000 Received: from [113.204.237.245] (helo=test.cqplus1.com) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1mgNX5-00AKs5-W0 for linux-arm-kernel@lists.infradead.org; Fri, 29 Oct 2021 08:46:43 +0000 X-MailGates: (flag:4,DYNAMIC,BADHELO,RELAY,NOHOST:PASS)(compute_score:DE LIVER,40,3) Received: from 172.28.114.216 by cqmailgates with MailGates ESMTP Server V5.0(10981:0:AUTH_RELAY) (envelope-from ); Fri, 29 Oct 2021 16:46:00 +0800 (CST) From: Qin Jian To: robh+dt@kernel.org Cc: mturquette@baylibre.com, sboyd@kernel.org, tglx@linutronix.de, maz@kernel.org, p.zabel@pengutronix.de, broonie@kernel.org, linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, wells.lu@sunplus.com, Qin Jian Subject: [PATCH v2 5/8] dt-bindings: clock: Add bindings for SP7021 clock driver Date: Fri, 29 Oct 2021 16:44:31 +0800 Message-Id: <188ff538d83266930bbba0e056106e285437da5b.1635496594.git.qinjian@cqplus1.com> X-Mailer: git-send-email 2.33.1 In-Reply-To: References: MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20211029_014640_460766_A2DE34D3 X-CRM114-Status: GOOD ( 13.35 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Add documentation to describe Sunplus SP7021 clock driver bindings. Signed-off-by: Qin Jian --- .../bindings/clock/sunplus,sp7021-clkc.yaml | 38 ++++++ MAINTAINERS | 2 + include/dt-bindings/clock/sp-sp7021.h | 112 ++++++++++++++++++ 3 files changed, 152 insertions(+) create mode 100644 Documentation/devicetree/bindings/clock/sunplus,sp7021-clkc.yaml create mode 100644 include/dt-bindings/clock/sp-sp7021.h diff --git a/Documentation/devicetree/bindings/clock/sunplus,sp7021-clkc.yaml b/Documentation/devicetree/bindings/clock/sunplus,sp7021-clkc.yaml new file mode 100644 index 000000000..1ce7e41d8 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/sunplus,sp7021-clkc.yaml @@ -0,0 +1,38 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +# Copyright (C) Sunplus Co., Ltd. 2021 +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/sunplus,sp7021-clkc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Sunplus SP7021 SoC Clock Controller Binding + +maintainers: + - Qin Jian + +properties: + compatible: + const: sunplus,sp7021-clkc + + "#clock-cells": + const: 1 + + reg: + maxItems: 1 + +required: + - compatible + - "#clock-cells" + - reg + +additionalProperties: false + +examples: + - | + clkc: clkc@9c000000 { + compatible = "sunplus,sp7021-clkc"; + #clock-cells = <1>; + reg = <0x9c000000 0x280>; + }; + +... diff --git a/MAINTAINERS b/MAINTAINERS index 6caffd6d0..90ebb823f 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -2661,8 +2661,10 @@ L: linux-arm-kernel@lists.infradead.org (moderated for mon-subscribers) S: Maintained W: https://sunplus-tibbo.atlassian.net/wiki/spaces/doc/overview F: Documentation/devicetree/bindings/arm/sunplus,sp7021.yaml +F: Documentation/devicetree/bindings/clock/sunplus,sp7021-clkc.yaml F: Documentation/devicetree/bindings/reset/sunplus,reset.yaml F: drivers/reset/reset-sunplus.c +F: include/dt-bindings/clock/sp-sp7021.h F: include/dt-bindings/reset/sp-sp7021.h ARM/Synaptics SoC support diff --git a/include/dt-bindings/clock/sp-sp7021.h b/include/dt-bindings/clock/sp-sp7021.h new file mode 100644 index 000000000..1ae9c4083 --- /dev/null +++ b/include/dt-bindings/clock/sp-sp7021.h @@ -0,0 +1,112 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +/* + * Copyright (C) Sunplus Technology Co., Ltd. + * All rights reserved. + */ +#ifndef _DT_BINDINGS_CLOCK_SUNPLUS_SP7021_H +#define _DT_BINDINGS_CLOCK_SUNPLUS_Sp7021_H + +#define XTAL 27000000 + +/* plls */ +#define PLL_A 0 +#define PLL_E 1 +#define PLL_E_2P5 2 +#define PLL_E_25 3 +#define PLL_E_112P5 4 +#define PLL_F 5 +#define PLL_TV 6 +#define PLL_TV_A 7 +#define PLL_SYS 8 + +/* gates: mo_clken0 ~ mo_clken9 */ +#define SYSTEM 0x10 +#define RTC 0x12 +#define IOCTL 0x13 +#define IOP 0x14 +#define OTPRX 0x15 +#define NOC 0x16 +#define BR 0x17 +#define RBUS_L00 0x18 +#define SPIFL 0x19 +#define SDCTRL0 0x1a +#define PERI0 0x1b +#define A926 0x1d +#define UMCTL2 0x1e +#define PERI1 0x1f + +#define DDR_PHY0 0x20 +#define ACHIP 0x22 +#define STC0 0x24 +#define STC_AV0 0x25 +#define STC_AV1 0x26 +#define STC_AV2 0x27 +#define UA0 0x28 +#define UA1 0x29 +#define UA2 0x2a +#define UA3 0x2b +#define UA4 0x2c +#define HWUA 0x2d +#define DDC0 0x2e +#define UADMA 0x2f + +#define CBDMA0 0x30 +#define CBDMA1 0x31 +#define SPI_COMBO_0 0x32 +#define SPI_COMBO_1 0x33 +#define SPI_COMBO_2 0x34 +#define SPI_COMBO_3 0x35 +#define AUD 0x36 +#define USBC0 0x3a +#define USBC1 0x3b +#define UPHY0 0x3d +#define UPHY1 0x3e + +#define I2CM0 0x40 +#define I2CM1 0x41 +#define I2CM2 0x42 +#define I2CM3 0x43 +#define PMC 0x4d +#define CARD_CTL0 0x4e +#define CARD_CTL1 0x4f + +#define CARD_CTL4 0x52 +#define BCH 0x54 +#define DDFCH 0x5b +#define CSIIW0 0x5c +#define CSIIW1 0x5d +#define MIPICSI0 0x5e +#define MIPICSI1 0x5f + +#define HDMI_TX 0x60 +#define VPOST 0x65 + +#define TGEN 0x70 +#define DMIX 0x71 +#define TCON 0x7a +#define INTERRUPT 0x7f + +#define RGST 0x80 +#define GPIO 0x83 +#define RBUS_TOP 0x84 + +#define MAILBOX 0x96 +#define SPIND 0x9a +#define I2C2CBUS 0x9b +#define SEC 0x9d +#define DVE 0x9e +#define GPOST0 0x9f + +#define OSD0 0xa0 +#define DISP_PWM 0xa2 +#define UADBG 0xa3 +#define DUMMY_MASTER 0xa4 +#define FIO_CTL 0xa5 +#define FPGA 0xa6 +#define L2SW 0xa7 +#define ICM 0xa8 +#define AXI_GLOBAL 0xa9 + +#define CLK_MAX 0xb0 + +#endif -- 2.33.1 _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 0E57AC433F5 for ; Fri, 29 Oct 2021 09:11:39 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id E4F4960F0F for ; Fri, 29 Oct 2021 09:11:38 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231566AbhJ2JOB (ORCPT ); Fri, 29 Oct 2021 05:14:01 -0400 Received: from [113.204.237.245] ([113.204.237.245]:55520 "EHLO test.cqplus1.com" rhost-flags-FAIL-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S231411AbhJ2JNE (ORCPT ); Fri, 29 Oct 2021 05:13:04 -0400 X-MailGates: (compute_score:DELIVER,40,3) Received: from 172.28.114.216 by cqmailgates with MailGates ESMTP Server V5.0(10981:0:AUTH_RELAY) (envelope-from ); Fri, 29 Oct 2021 16:46:00 +0800 (CST) From: Qin Jian To: robh+dt@kernel.org Cc: mturquette@baylibre.com, sboyd@kernel.org, tglx@linutronix.de, maz@kernel.org, p.zabel@pengutronix.de, broonie@kernel.org, linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, wells.lu@sunplus.com, Qin Jian Subject: [PATCH v2 5/8] dt-bindings: clock: Add bindings for SP7021 clock driver Date: Fri, 29 Oct 2021 16:44:31 +0800 Message-Id: <188ff538d83266930bbba0e056106e285437da5b.1635496594.git.qinjian@cqplus1.com> X-Mailer: git-send-email 2.33.1 In-Reply-To: References: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Add documentation to describe Sunplus SP7021 clock driver bindings. Signed-off-by: Qin Jian --- .../bindings/clock/sunplus,sp7021-clkc.yaml | 38 ++++++ MAINTAINERS | 2 + include/dt-bindings/clock/sp-sp7021.h | 112 ++++++++++++++++++ 3 files changed, 152 insertions(+) create mode 100644 Documentation/devicetree/bindings/clock/sunplus,sp7021-clkc.yaml create mode 100644 include/dt-bindings/clock/sp-sp7021.h diff --git a/Documentation/devicetree/bindings/clock/sunplus,sp7021-clkc.yaml b/Documentation/devicetree/bindings/clock/sunplus,sp7021-clkc.yaml new file mode 100644 index 000000000..1ce7e41d8 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/sunplus,sp7021-clkc.yaml @@ -0,0 +1,38 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +# Copyright (C) Sunplus Co., Ltd. 2021 +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/sunplus,sp7021-clkc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Sunplus SP7021 SoC Clock Controller Binding + +maintainers: + - Qin Jian + +properties: + compatible: + const: sunplus,sp7021-clkc + + "#clock-cells": + const: 1 + + reg: + maxItems: 1 + +required: + - compatible + - "#clock-cells" + - reg + +additionalProperties: false + +examples: + - | + clkc: clkc@9c000000 { + compatible = "sunplus,sp7021-clkc"; + #clock-cells = <1>; + reg = <0x9c000000 0x280>; + }; + +... diff --git a/MAINTAINERS b/MAINTAINERS index 6caffd6d0..90ebb823f 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -2661,8 +2661,10 @@ L: linux-arm-kernel@lists.infradead.org (moderated for mon-subscribers) S: Maintained W: https://sunplus-tibbo.atlassian.net/wiki/spaces/doc/overview F: Documentation/devicetree/bindings/arm/sunplus,sp7021.yaml +F: Documentation/devicetree/bindings/clock/sunplus,sp7021-clkc.yaml F: Documentation/devicetree/bindings/reset/sunplus,reset.yaml F: drivers/reset/reset-sunplus.c +F: include/dt-bindings/clock/sp-sp7021.h F: include/dt-bindings/reset/sp-sp7021.h ARM/Synaptics SoC support diff --git a/include/dt-bindings/clock/sp-sp7021.h b/include/dt-bindings/clock/sp-sp7021.h new file mode 100644 index 000000000..1ae9c4083 --- /dev/null +++ b/include/dt-bindings/clock/sp-sp7021.h @@ -0,0 +1,112 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +/* + * Copyright (C) Sunplus Technology Co., Ltd. + * All rights reserved. + */ +#ifndef _DT_BINDINGS_CLOCK_SUNPLUS_SP7021_H +#define _DT_BINDINGS_CLOCK_SUNPLUS_Sp7021_H + +#define XTAL 27000000 + +/* plls */ +#define PLL_A 0 +#define PLL_E 1 +#define PLL_E_2P5 2 +#define PLL_E_25 3 +#define PLL_E_112P5 4 +#define PLL_F 5 +#define PLL_TV 6 +#define PLL_TV_A 7 +#define PLL_SYS 8 + +/* gates: mo_clken0 ~ mo_clken9 */ +#define SYSTEM 0x10 +#define RTC 0x12 +#define IOCTL 0x13 +#define IOP 0x14 +#define OTPRX 0x15 +#define NOC 0x16 +#define BR 0x17 +#define RBUS_L00 0x18 +#define SPIFL 0x19 +#define SDCTRL0 0x1a +#define PERI0 0x1b +#define A926 0x1d +#define UMCTL2 0x1e +#define PERI1 0x1f + +#define DDR_PHY0 0x20 +#define ACHIP 0x22 +#define STC0 0x24 +#define STC_AV0 0x25 +#define STC_AV1 0x26 +#define STC_AV2 0x27 +#define UA0 0x28 +#define UA1 0x29 +#define UA2 0x2a +#define UA3 0x2b +#define UA4 0x2c +#define HWUA 0x2d +#define DDC0 0x2e +#define UADMA 0x2f + +#define CBDMA0 0x30 +#define CBDMA1 0x31 +#define SPI_COMBO_0 0x32 +#define SPI_COMBO_1 0x33 +#define SPI_COMBO_2 0x34 +#define SPI_COMBO_3 0x35 +#define AUD 0x36 +#define USBC0 0x3a +#define USBC1 0x3b +#define UPHY0 0x3d +#define UPHY1 0x3e + +#define I2CM0 0x40 +#define I2CM1 0x41 +#define I2CM2 0x42 +#define I2CM3 0x43 +#define PMC 0x4d +#define CARD_CTL0 0x4e +#define CARD_CTL1 0x4f + +#define CARD_CTL4 0x52 +#define BCH 0x54 +#define DDFCH 0x5b +#define CSIIW0 0x5c +#define CSIIW1 0x5d +#define MIPICSI0 0x5e +#define MIPICSI1 0x5f + +#define HDMI_TX 0x60 +#define VPOST 0x65 + +#define TGEN 0x70 +#define DMIX 0x71 +#define TCON 0x7a +#define INTERRUPT 0x7f + +#define RGST 0x80 +#define GPIO 0x83 +#define RBUS_TOP 0x84 + +#define MAILBOX 0x96 +#define SPIND 0x9a +#define I2C2CBUS 0x9b +#define SEC 0x9d +#define DVE 0x9e +#define GPOST0 0x9f + +#define OSD0 0xa0 +#define DISP_PWM 0xa2 +#define UADBG 0xa3 +#define DUMMY_MASTER 0xa4 +#define FIO_CTL 0xa5 +#define FPGA 0xa6 +#define L2SW 0xa7 +#define ICM 0xa8 +#define AXI_GLOBAL 0xa9 + +#define CLK_MAX 0xb0 + +#endif -- 2.33.1