From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1754218AbbL3JHU (ORCPT ); Wed, 30 Dec 2015 04:07:20 -0500 Received: from mout.kundenserver.de ([212.227.126.130]:50239 "EHLO mout.kundenserver.de" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752038AbbL3JHN (ORCPT ); Wed, 30 Dec 2015 04:07:13 -0500 From: Arnd Bergmann To: Rongrong Zou Cc: catalin.marinas@arm.com, will.deacon@arm.com, benh@kernel.crashing.org, lijianhua@huawei.com, lixiancai@huawei.com, linuxarm@huawei.com, linux-kernel@vger.kernel.org, minyard@acm.org, gregkh@linuxfoundation.org Subject: Re: [PATCH v1 3/3] ARM64 LPC: update binding doc Date: Wed, 30 Dec 2015 10:06:54 +0100 Message-ID: <1899302.RWIn6Bg3Dr@wuerfel> User-Agent: KMail/4.11.5 (Linux/3.16.0-10-generic; KDE/4.11.5; x86_64; ; ) In-Reply-To: <1451396032-23708-4-git-send-email-zourongrong@gmail.com> References: <1451396032-23708-1-git-send-email-zourongrong@gmail.com> <1451396032-23708-4-git-send-email-zourongrong@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: 7Bit Content-Type: text/plain; charset="us-ascii" X-Provags-ID: V03:K0:W174/iNjvX7dPvTtBcEBavAQFnye4mY3dN+KV1OzM9UbT6KIfav jvE7zCd9bxozk5sY2KZLcWZ62mQSHzOoMGILXmjfETcQVq6wR3PHkWH+P9bRS1U0ERbOqcT r0VeLSJBwogDDjzrb2Ei83XScwpy41tbowYRAdsfrUwYI6uPAziu5K7IXUr867/5ZktA+wV fdmK63Bl2P24BAt10MSVw== X-UI-Out-Filterresults: notjunk:1;V01:K0:HvYV2bq2RmM=:Y+IkLgSDhEP95l8RVQNnGE 6h/xyTo5Ky9dsATE5s9CPOilkCNULS8EPpwTY1bExlaTR42otQvl0gUm4YWAyG/+KUt30D3L+ 2McEkMNuI2gA5TZ/GFjzXxdN/ZdEH5lhBwAR1bRCQSAEET8SoUS9lI2cFpeJQP0r1qTDfURBR F7ZpopL0P1yGb5BBae1o/OxVoVZ6do0sTi0fD57DmqpojZBkvvAti0dS5b9h7xhf0azyS6O5/ i0vX60H+vYSiGRDMMmrcpfosq7GJNCfAmVUyW4QphSWDkVJ0LvCVVt2EritR4bpo0TfGcFZox SfXcexCn6bzADly7iOjdhFdyjd8DzgTSIEt3wX451+5qmsE/SbdiJ5T325+RghAWYzJ2hc7IK qDSA7pBbOH7NfOcNzVPNHrs9iHHQAmGQ8UDD9GOwLiM1rzlTPUNe9NQD7q0F7MPPuuF1JrNsM FOTvHm5WpyOzOCB1zjNebC4Mw5dZwTWILE24F6M0QkAc8Z92OSwpELbej/AfvztnZxG2AMQU0 UAg4XtcCSaPkU9oA17VmaXCxT2ErkrUmAAJCeZwvNFK6j6g2g/k8lOJoLEuDnTynRGsg1ZfeP 1QIu5xc3OfEPiLMJDM994GwSxUlUMHzDouwffTR9h3CIvF2fTAno4bY5UlIu1g4GXNVw6qrfn qVc3z2G886GbwYGX9qMKALzPwdqinvre/KVHd6ocFWiYOjtEu7/IphIb2hmw7kyNJIRwPlR7L 2/q5mrmfRStVTMot Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Tuesday 29 December 2015 21:33:52 Rongrong Zou wrote: > Signed-off-by: Rongrong Zou > --- > .../devicetree/bindings/arm64/low-pin-count.txt | 20 ++++++++++++++++++++ > 1 file changed, 20 insertions(+) > create mode 100644 Documentation/devicetree/bindings/arm64/low-pin-count.txt > > diff --git a/Documentation/devicetree/bindings/arm64/low-pin-count.txt b/Documentation/devicetree/bindings/arm64/low-pin-count.txt > new file mode 100644 > index 0000000..215f2c4 > --- /dev/null > +++ b/Documentation/devicetree/bindings/arm64/low-pin-count.txt > @@ -0,0 +1,20 @@ > +Low Pin Count bus driver > + > +Usually LPC controller is part of PCI host bridge, so the legacy ISA > +port locate on LPC bus can be accessed directly. But some SoC have > +independent LPC controller, and we can access the legacy port by specifying > +LPC address cycle. Thus, LPC driver is introduced. > + > +Required properties: > +- compatible: "low-pin-count" > +- reg: specifies low pin count address range > + > + > +Example: > + > + lpc_0: lpc@a01b0000 { > + #address-cells = <1>; > + #size-cells = <1>; > + compatible = "low-pin-count"; > + reg = <0x0 0xa01b0000 0x0 0x10000>; > + }; One more thought: please try to stick as closely as possible to the existing ISA binding that is documented at http://www.firmware.org/1275/bindings/isa/isa0_4d.ps In particular, this should cover the possibility of describing both memory and I/O spaces in child devices. Arnd