From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([208.118.235.92]:46014) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1TQCIa-0004BN-RG for qemu-devel@nongnu.org; Mon, 22 Oct 2012 03:19:45 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1TQCIW-0000D8-A7 for qemu-devel@nongnu.org; Mon, 22 Oct 2012 03:19:44 -0400 Received: from mail-da0-f45.google.com ([209.85.210.45]:36391) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1TQCIW-0008T1-3O for qemu-devel@nongnu.org; Mon, 22 Oct 2012 03:19:40 -0400 Received: by mail-da0-f45.google.com with SMTP id n15so1183435dad.4 for ; Mon, 22 Oct 2012 00:19:39 -0700 (PDT) Sender: Peter Crosthwaite From: Peter Crosthwaite Date: Mon, 22 Oct 2012 17:19:03 +1000 Message-Id: <194bc92fae8a539ef01da90bf4dafe573d34468e.1350889929.git.peter.crosthwaite@xilinx.com> In-Reply-To: References: In-Reply-To: References: Subject: [Qemu-devel] [PATCH v2 5/6] xilinx_zynq: add pl353 List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: vineshp@xilinx.com, peter.maydell@linaro.org, Peter Crosthwaite , john.williams@xilinx.com, pbonzini@redhat.com, edgar.iglesias@gmail.com Add the pl353 memory controller with both NAND and parallel flashes attached. Signed-off-by: Peter Crosthwaite --- changed from v1: fixed property names (see patch 3) hw/xilinx_zynq.c | 50 ++++++++++++++++++++++++++++++++++++++++++-------- 1 files changed, 42 insertions(+), 8 deletions(-) diff --git a/hw/xilinx_zynq.c b/hw/xilinx_zynq.c index c55dafb..7261693 100644 --- a/hw/xilinx_zynq.c +++ b/hw/xilinx_zynq.c @@ -123,14 +123,48 @@ static void zynq_init(QEMUMachineInitArgs *args) vmstate_register_ram_global(ocm_ram); memory_region_add_subregion(address_space_mem, 0xFFFC0000, ocm_ram); - DriveInfo *dinfo = drive_get(IF_PFLASH, 0, 0); - - /* AMD */ - pflash_cfi02_register(0xe2000000, NULL, "zynq.pflash", FLASH_SIZE, - dinfo ? dinfo->bdrv : NULL, FLASH_SECTOR_SIZE, - FLASH_SIZE/FLASH_SECTOR_SIZE, 1, - 1, 0x0066, 0x0022, 0x0000, 0x0000, 0x0555, 0x2aa, - 0); + /* pl353 */ + dev = qdev_create(NULL, "arm.pl35x"); + /* FIXME: handle this somewhere central */ + object_property_add_child(container_get(qdev_get_machine(), "/unattached"), + "pl353", OBJECT(dev), NULL); + qdev_prop_set_uint8(dev, "x", 3); + { + DriveInfo *dinfo = drive_get_next(IF_PFLASH); + BlockDriverState *bs = dinfo ? dinfo->bdrv : NULL; + DeviceState *att_dev = qdev_create(NULL, "cfi.pflash02"); + Error *errp = NULL; + + if (bs && qdev_prop_set_drive(att_dev, "drive", bs)) { + abort(); + } + qdev_prop_set_uint32(att_dev, "num-blocks", + FLASH_SIZE/FLASH_SECTOR_SIZE); + qdev_prop_set_uint32(att_dev, "sector-length", FLASH_SECTOR_SIZE); + qdev_prop_set_uint8(att_dev, "width", 1); + qdev_prop_set_uint8(att_dev, "mappings", 1); + qdev_prop_set_uint8(att_dev, "big-endian", 0); + qdev_prop_set_uint16(att_dev, "id0", 0x0066); + qdev_prop_set_uint16(att_dev, "id1", 0x0022); + qdev_prop_set_uint16(att_dev, "id2", 0x0000); + qdev_prop_set_uint16(att_dev, "id3", 0x0000); + qdev_prop_set_uint16(att_dev, "unlock-addr0", 0x0aaa); + qdev_prop_set_uint16(att_dev, "unlock-addr1", 0x0555); + qdev_prop_set_string(att_dev, "name", "pl353.pflash"); + qdev_init_nofail(att_dev); + object_property_set_link(OBJECT(dev), OBJECT(att_dev), "dev0", &errp); + assert_no_error(errp); + + dinfo = drive_get_next(IF_PFLASH); + att_dev = nand_init(dinfo ? dinfo->bdrv : NULL, NAND_MFR_STMICRO, 0xaa); + object_property_set_link(OBJECT(dev), OBJECT(att_dev), "dev1", &errp); + assert_no_error(errp); + } + qdev_init_nofail(dev); + busdev = sysbus_from_qdev(dev); + sysbus_mmio_map(busdev, 0, 0xe000e000); + sysbus_mmio_map(busdev, 1, 0xe2000000); + sysbus_mmio_map(busdev, 2, 0xe1000000); dev = qdev_create(NULL, "xilinx,zynq_slcr"); qdev_init_nofail(dev); -- 1.7.0.4