* [PATCH 1/2] target/mips: Remove pointless gen_msa()
2021-06-17 17:46 [PATCH 0/2] target/mips: Simplify MSA decodetree Philippe Mathieu-Daudé
@ 2021-06-17 17:46 ` Philippe Mathieu-Daudé
2021-06-18 14:56 ` Richard Henderson
2021-06-17 17:46 ` [PATCH 2/2] target/mips: Merge msa32/msa64 decodetree definitions Philippe Mathieu-Daudé
2021-06-19 18:02 ` [PATCH 0/2] target/mips: Simplify MSA decodetree Philippe Mathieu-Daudé
2 siblings, 1 reply; 6+ messages in thread
From: Philippe Mathieu-Daudé @ 2021-06-17 17:46 UTC (permalink / raw)
To: qemu-devel
Cc: Aleksandar Rikalo, Richard Henderson, Aurelien Jarno,
Philippe Mathieu-Daudé
Only trans_MSA() calls gen_msa(), inline it to simplify.
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
---
target/mips/tcg/msa_translate.c | 7 +------
1 file changed, 1 insertion(+), 6 deletions(-)
diff --git a/target/mips/tcg/msa_translate.c b/target/mips/tcg/msa_translate.c
index a2f7d6a1e08..429039cc7c9 100644
--- a/target/mips/tcg/msa_translate.c
+++ b/target/mips/tcg/msa_translate.c
@@ -2162,7 +2162,7 @@ static void gen_msa_vec(DisasContext *ctx)
}
}
-static void gen_msa(DisasContext *ctx)
+static bool trans_MSA(DisasContext *ctx, arg_MSA *a)
{
uint32_t opcode = ctx->opcode;
@@ -2258,11 +2258,6 @@ static void gen_msa(DisasContext *ctx)
gen_reserved_instruction(ctx);
break;
}
-}
-
-static bool trans_MSA(DisasContext *ctx, arg_MSA *a)
-{
- gen_msa(ctx);
return true;
}
--
2.31.1
^ permalink raw reply related [flat|nested] 6+ messages in thread* [PATCH 2/2] target/mips: Merge msa32/msa64 decodetree definitions
2021-06-17 17:46 [PATCH 0/2] target/mips: Simplify MSA decodetree Philippe Mathieu-Daudé
2021-06-17 17:46 ` [PATCH 1/2] target/mips: Remove pointless gen_msa() Philippe Mathieu-Daudé
@ 2021-06-17 17:46 ` Philippe Mathieu-Daudé
2021-06-18 15:03 ` Richard Henderson
2021-06-19 18:02 ` [PATCH 0/2] target/mips: Simplify MSA decodetree Philippe Mathieu-Daudé
2 siblings, 1 reply; 6+ messages in thread
From: Philippe Mathieu-Daudé @ 2021-06-17 17:46 UTC (permalink / raw)
To: qemu-devel
Cc: Aleksandar Rikalo, Richard Henderson, Aurelien Jarno,
Philippe Mathieu-Daudé
We don't need to maintain 2 sets of decodetree definitions.
Merge them into a single file.
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
---
target/mips/tcg/{msa32.decode => msa.decode} | 8 +++++---
target/mips/tcg/msa64.decode | 17 -----------------
target/mips/tcg/msa_translate.c | 14 ++++----------
target/mips/tcg/meson.build | 3 +--
4 files changed, 10 insertions(+), 32 deletions(-)
rename target/mips/tcg/{msa32.decode => msa.decode} (74%)
delete mode 100644 target/mips/tcg/msa64.decode
diff --git a/target/mips/tcg/msa32.decode b/target/mips/tcg/msa.decode
similarity index 74%
rename from target/mips/tcg/msa32.decode
rename to target/mips/tcg/msa.decode
index ca200e373b1..bf132e36b9b 100644
--- a/target/mips/tcg/msa32.decode
+++ b/target/mips/tcg/msa.decode
@@ -6,9 +6,10 @@
#
# Reference:
# MIPS Architecture for Programmers Volume IV-j
-# The MIPS32 SIMD Architecture Module, Revision 1.12
-# (Document Number: MD00866-2B-MSA32-AFP-01.12)
-#
+# - The MIPS32 SIMD Architecture Module, Revision 1.12
+# (Document Number: MD00866-2B-MSA32-AFP-01.12)
+# - The MIPS64 SIMD Architecture Module, Revision 1.12
+# (Document Number: MD00868-1D-MSA64-AFP-01.12)
&rtype rs rt rd sa
@@ -19,6 +20,7 @@
@bz_df ...... ... df:2 wt:5 s16:16 &msa_bz
LSA 000000 ..... ..... ..... 000 .. 000101 @lsa
+DLSA 000000 ..... ..... ..... 000 .. 010101 @lsa
BZ_V 010001 01011 ..... ................ @bz
BNZ_V 010001 01111 ..... ................ @bz
diff --git a/target/mips/tcg/msa64.decode b/target/mips/tcg/msa64.decode
deleted file mode 100644
index d2442474d0b..00000000000
--- a/target/mips/tcg/msa64.decode
+++ /dev/null
@@ -1,17 +0,0 @@
-# MIPS SIMD Architecture Module instruction set
-#
-# Copyright (C) 2020 Philippe Mathieu-Daudé
-#
-# SPDX-License-Identifier: LGPL-2.1-or-later
-#
-# Reference:
-# MIPS Architecture for Programmers Volume IV-j
-# The MIPS64 SIMD Architecture Module, Revision 1.12
-# (Document Number: MD00868-1D-MSA64-AFP-01.12)
-#
-
-&rtype rs rt rd sa !extern
-
-@lsa ...... rs:5 rt:5 rd:5 ... sa:2 ...... &rtype
-
-DLSA 000000 ..... ..... ..... 000 .. 010101 @lsa
diff --git a/target/mips/tcg/msa_translate.c b/target/mips/tcg/msa_translate.c
index 429039cc7c9..1ce0d87168c 100644
--- a/target/mips/tcg/msa_translate.c
+++ b/target/mips/tcg/msa_translate.c
@@ -18,8 +18,7 @@
#include "internal.h"
/* Include the auto-generated decoder. */
-#include "decode-msa32.c.inc"
-#include "decode-msa64.c.inc"
+#include "decode-msa.c.inc"
#define OPC_MSA (0x1E << 26)
@@ -2269,13 +2268,8 @@ static bool trans_LSA(DisasContext *ctx, arg_rtype *a)
static bool trans_DLSA(DisasContext *ctx, arg_rtype *a)
{
+ if (TARGET_LONG_BITS != 64) {
+ return false;
+ }
return gen_dlsa(ctx, a->rd, a->rt, a->rs, a->sa);
}
-
-bool decode_ase_msa(DisasContext *ctx, uint32_t insn)
-{
- if (TARGET_LONG_BITS == 64 && decode_msa64(ctx, insn)) {
- return true;
- }
- return decode_msa32(ctx, insn);
-}
diff --git a/target/mips/tcg/meson.build b/target/mips/tcg/meson.build
index 5d8acbaf0d3..bf4001e5741 100644
--- a/target/mips/tcg/meson.build
+++ b/target/mips/tcg/meson.build
@@ -1,8 +1,7 @@
gen = [
decodetree.process('mips32r6.decode', extra_args: '--static-decode=decode_mips32r6'),
decodetree.process('mips64r6.decode', extra_args: '--static-decode=decode_mips64r6'),
- decodetree.process('msa32.decode', extra_args: '--static-decode=decode_msa32'),
- decodetree.process('msa64.decode', extra_args: '--static-decode=decode_msa64'),
+ decodetree.process('msa.decode', extra_args: '--decode=decode_ase_msa'),
decodetree.process('tx79.decode', extra_args: '--static-decode=decode_tx79'),
]
--
2.31.1
^ permalink raw reply related [flat|nested] 6+ messages in thread