From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-6.8 required=3.0 tests=HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH,MAILING_LIST_MULTI,SIGNED_OFF_BY,SPF_PASS,URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id EFCD1C65C1B for ; Sun, 7 Oct 2018 18:47:43 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id A1FA220834 for ; Sun, 7 Oct 2018 18:47:43 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org A1FA220834 Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=v3.sk Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728265AbeJHBzy (ORCPT ); Sun, 7 Oct 2018 21:55:54 -0400 Received: from shell.v3.sk ([90.176.6.54]:40689 "EHLO shell.v3.sk" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726233AbeJHBzx (ORCPT ); Sun, 7 Oct 2018 21:55:53 -0400 Received: from localhost (localhost [127.0.0.1]) by zimbra.v3.sk (Postfix) with ESMTP id 4590EB78B0; Sun, 7 Oct 2018 20:47:35 +0200 (CEST) Received: from shell.v3.sk ([127.0.0.1]) by localhost (zimbra.v3.sk [127.0.0.1]) (amavisd-new, port 10032) with ESMTP id rn99dKEQRIL4; Sun, 7 Oct 2018 20:47:29 +0200 (CEST) Received: from localhost (localhost [127.0.0.1]) by zimbra.v3.sk (Postfix) with ESMTP id 9AC47BCAB7; Sun, 7 Oct 2018 20:47:29 +0200 (CEST) X-Virus-Scanned: amavisd-new at zimbra.v3.sk Received: from shell.v3.sk ([127.0.0.1]) by localhost (zimbra.v3.sk [127.0.0.1]) (amavisd-new, port 10026) with ESMTP id QBMr0aG0d39P; Sun, 7 Oct 2018 20:47:29 +0200 (CEST) Received: from belphegor.lan (ip-89-102-31-34.net.upcbroadband.cz [89.102.31.34]) by zimbra.v3.sk (Postfix) with ESMTPSA id 9EEB2B78B0; Sun, 7 Oct 2018 20:47:28 +0200 (CEST) Message-ID: <1981ce54ce960d21976ce71b08a8779bfeb13be4.camel@v3.sk> Subject: Re: [PATCH 01/14] phy: phy-pxa-usb: add a new driver From: Lubomir Rintel To: Kishon Vijay Abraham I , linux-kernel@vger.kernel.org, Greg Kroah-Hartman Cc: linux-usb@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Rob Herring , Mark Rutland , Eric Miao , Haojian Zhuang , Alan Stern Date: Sun, 07 Oct 2018 20:47:28 +0200 In-Reply-To: References: <20180822204307.13251-1-lkundrak@v3.sk> <20180822204307.13251-2-lkundrak@v3.sk> Content-Type: text/plain; charset="UTF-8" User-Agent: Evolution 3.30.1 (3.30.1-1.fc29) Mime-Version: 1.0 Content-Transfer-Encoding: 7bit Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Tue, 2018-09-25 at 10:53 +0530, Kishon Vijay Abraham I wrote: > > On Thursday 23 August 2018 02:12 AM, Lubomir Rintel wrote: > > Turned from arch/arm/mach-mmp/devices.c into a proper PHY driver, > > so > > that in can be instantiated from a DT. > > > > Signed-off-by: Lubomir Rintel > > Acked-by: Kishon Vijay Abraham I > > If this has to be merged via linux-phy tree, please let me know. Yes, either linux-phy or the usb tree. The EHCI patches have already been pulled into the usb tree, presumably because they got an Ack from Alan Stern. That includes "USB: EHCI: ehci-mv: use phy-pxa-usb" that depends on this. Perhaps the rest of the patches can go via the same tree? I haven't submitted a patchset that would have dependencies spanning across different subsystems before. I don't know what's usually done in such cases. Advice welcome. Greg? > Thanks > Kishon Thank you Lubo > > > --- > > drivers/phy/marvell/Kconfig | 11 + > > drivers/phy/marvell/Makefile | 1 + > > drivers/phy/marvell/phy-pxa-usb.c | 345 > > ++++++++++++++++++++++++++++++ > > 3 files changed, 357 insertions(+) > > create mode 100644 drivers/phy/marvell/phy-pxa-usb.c > > > > diff --git a/drivers/phy/marvell/Kconfig > > b/drivers/phy/marvell/Kconfig > > index 68e321225400..6fb4b56e4c14 100644 > > --- a/drivers/phy/marvell/Kconfig > > +++ b/drivers/phy/marvell/Kconfig > > @@ -59,3 +59,14 @@ config PHY_PXA_28NM_USB2 > > The PHY driver will be used by Marvell udc/ehci/otg driver. > > > > To compile this driver as a module, choose M here. > > + > > +config PHY_PXA_USB > > + tristate "Marvell PXA USB PHY Driver" > > + depends on ARCH_PXA || ARCH_MMP > > + select GENERIC_PHY > > + help > > + Enable this to support Marvell PXA USB PHY driver for Marvell > > + SoC. This driver will do the PHY initialization and shutdown. > > + The PHY driver will be used by Marvell udc/ehci/otg driver. > > + > > + To compile this driver as a module, choose M here. > > diff --git a/drivers/phy/marvell/Makefile > > b/drivers/phy/marvell/Makefile > > index 5c3ec5d10e0d..3975b144f8ec 100644 > > --- a/drivers/phy/marvell/Makefile > > +++ b/drivers/phy/marvell/Makefile > > @@ -6,3 +6,4 @@ obj-$(CONFIG_PHY_MVEBU_CP110_COMPHY) += phy- > > mvebu-cp110-comphy.o > > obj-$(CONFIG_PHY_MVEBU_SATA) += phy-mvebu-sata.o > > obj-$(CONFIG_PHY_PXA_28NM_HSIC) += phy-pxa-28nm-hsic.o > > obj-$(CONFIG_PHY_PXA_28NM_USB2) += phy-pxa-28nm-usb2.o > > +obj-$(CONFIG_PHY_PXA_USB) += phy-pxa-usb.o > > diff --git a/drivers/phy/marvell/phy-pxa-usb.c > > b/drivers/phy/marvell/phy-pxa-usb.c > > new file mode 100644 > > index 000000000000..87ff7550b912 > > --- /dev/null > > +++ b/drivers/phy/marvell/phy-pxa-usb.c > > @@ -0,0 +1,345 @@ > > +// SPDX-License-Identifier: GPL-2.0 > > +/* > > + * Copyright (C) 2011 Marvell International Ltd. All rights > > reserved. > > + * Copyright (C) 2018 Lubomir Rintel > > + */ > > + > > +#include > > +#include > > +#include > > +#include > > +#include > > +#include > > +#include > > +#include > > + > > +/* phy regs */ > > +#define UTMI_REVISION 0x0 > > +#define UTMI_CTRL 0x4 > > +#define UTMI_PLL 0x8 > > +#define UTMI_TX 0xc > > +#define UTMI_RX 0x10 > > +#define UTMI_IVREF 0x14 > > +#define UTMI_T0 0x18 > > +#define UTMI_T1 0x1c > > +#define UTMI_T2 0x20 > > +#define UTMI_T3 0x24 > > +#define UTMI_T4 0x28 > > +#define UTMI_T5 0x2c > > +#define UTMI_RESERVE 0x30 > > +#define UTMI_USB_INT 0x34 > > +#define UTMI_DBG_CTL 0x38 > > +#define UTMI_OTG_ADDON 0x3c > > + > > +/* For UTMICTRL Register */ > > +#define UTMI_CTRL_USB_CLK_EN (1 << 31) > > +/* pxa168 */ > > +#define UTMI_CTRL_SUSPEND_SET1 (1 << 30) > > +#define UTMI_CTRL_SUSPEND_SET2 (1 << 29) > > +#define UTMI_CTRL_RXBUF_PDWN (1 << 24) > > +#define UTMI_CTRL_TXBUF_PDWN (1 << 11) > > + > > +#define UTMI_CTRL_INPKT_DELAY_SHIFT 30 > > +#define UTMI_CTRL_INPKT_DELAY_SOF_SHIFT 28 > > +#define UTMI_CTRL_PU_REF_SHIFT 20 > > +#define UTMI_CTRL_ARC_PULLDN_SHIFT 12 > > +#define UTMI_CTRL_PLL_PWR_UP_SHIFT 1 > > +#define UTMI_CTRL_PWR_UP_SHIFT 0 > > + > > +/* For UTMI_PLL Register */ > > +#define UTMI_PLL_PLLCALI12_SHIFT 29 > > +#define UTMI_PLL_PLLCALI12_MASK (0x3 << 29) > > + > > +#define UTMI_PLL_PLLVDD18_SHIFT 27 > > +#define UTMI_PLL_PLLVDD18_MASK (0x3 << 27) > > + > > +#define UTMI_PLL_PLLVDD12_SHIFT 25 > > +#define UTMI_PLL_PLLVDD12_MASK (0x3 << 25) > > + > > +#define UTMI_PLL_CLK_BLK_EN_SHIFT 24 > > +#define CLK_BLK_EN (0x1 << 24) > > +#define PLL_READY (0x1 << 23) > > +#define KVCO_EXT (0x1 << 22) > > +#define VCOCAL_START (0x1 << 21) > > + > > +#define UTMI_PLL_KVCO_SHIFT 15 > > +#define UTMI_PLL_KVCO_MASK (0x7 << 15) > > + > > +#define UTMI_PLL_ICP_SHIFT 12 > > +#define UTMI_PLL_ICP_MASK (0x7 << 12) > > + > > +#define UTMI_PLL_FBDIV_SHIFT 4 > > +#define UTMI_PLL_FBDIV_MASK (0xFF << 4) > > + > > +#define UTMI_PLL_REFDIV_SHIFT 0 > > +#define UTMI_PLL_REFDIV_MASK (0xF << 0) > > + > > +/* For UTMI_TX Register */ > > +#define UTMI_TX_REG_EXT_FS_RCAL_SHIFT 27 > > +#define UTMI_TX_REG_EXT_FS_RCAL_MASK (0xf << 27) > > + > > +#define UTMI_TX_REG_EXT_FS_RCAL_EN_SHIFT 26 > > +#define UTMI_TX_REG_EXT_FS_RCAL_EN_MASK (0x1 << 26) > > + > > +#define UTMI_TX_TXVDD12_SHIFT 22 > > +#define UTMI_TX_TXVDD12_MASK (0x3 << 22) > > + > > +#define UTMI_TX_CK60_PHSEL_SHIFT 17 > > +#define UTMI_TX_CK60_PHSEL_MASK (0xf << 17) > > + > > +#define UTMI_TX_IMPCAL_VTH_SHIFT 14 > > +#define UTMI_TX_IMPCAL_VTH_MASK (0x7 << 14) > > + > > +#define REG_RCAL_START (0x1 << 12) > > + > > +#define UTMI_TX_LOW_VDD_EN_SHIFT 11 > > + > > +#define UTMI_TX_AMP_SHIFT 0 > > +#define UTMI_TX_AMP_MASK (0x7 << 0) > > + > > +/* For UTMI_RX Register */ > > +#define UTMI_REG_SQ_LENGTH_SHIFT 15 > > +#define UTMI_REG_SQ_LENGTH_MASK (0x3 << 15) > > + > > +#define UTMI_RX_SQ_THRESH_SHIFT 4 > > +#define UTMI_RX_SQ_THRESH_MASK (0xf << 4) > > + > > +#define UTMI_OTG_ADDON_OTG_ON (1 << 0) > > + > > +enum pxa_usb_phy_version { > > + PXA_USB_PHY_MMP2, > > + PXA_USB_PHY_PXA910, > > + PXA_USB_PHY_PXA168, > > +}; > > + > > +struct pxa_usb_phy { > > + struct phy *phy; > > + void __iomem *base; > > + enum pxa_usb_phy_version version; > > +}; > > + > > +/***************************************************************** > > ************ > > + * The registers read/write routines > > + > > ******************************************************************* > > **********/ > > + > > +static unsigned int u2o_get(void __iomem *base, unsigned int > > offset) > > +{ > > + return readl_relaxed(base + offset); > > +} > > + > > +static void u2o_set(void __iomem *base, unsigned int offset, > > + unsigned int value) > > +{ > > + u32 reg; > > + > > + reg = readl_relaxed(base + offset); > > + reg |= value; > > + writel_relaxed(reg, base + offset); > > + readl_relaxed(base + offset); > > +} > > + > > +static void u2o_clear(void __iomem *base, unsigned int offset, > > + unsigned int value) > > +{ > > + u32 reg; > > + > > + reg = readl_relaxed(base + offset); > > + reg &= ~value; > > + writel_relaxed(reg, base + offset); > > + readl_relaxed(base + offset); > > +} > > + > > +static void u2o_write(void __iomem *base, unsigned int offset, > > + unsigned int value) > > +{ > > + writel_relaxed(value, base + offset); > > + readl_relaxed(base + offset); > > +} > > + > > +static int pxa_usb_phy_init(struct phy *phy) > > +{ > > + struct pxa_usb_phy *pxa_usb_phy = phy_get_drvdata(phy); > > + void __iomem *base = pxa_usb_phy->base; > > + int loops; > > + > > + dev_info(&phy->dev, "initializing Marvell PXA USB PHY"); > > + > > + /* Initialize the USB PHY power */ > > + if (pxa_usb_phy->version == PXA_USB_PHY_PXA910) { > > + u2o_set(base, UTMI_CTRL, > > (1< > + | (1< > + } > > + > > + u2o_set(base, UTMI_CTRL, 1< > + u2o_set(base, UTMI_CTRL, 1< > + > > + /* UTMI_PLL settings */ > > + u2o_clear(base, UTMI_PLL, UTMI_PLL_PLLVDD18_MASK > > + | UTMI_PLL_PLLVDD12_MASK | UTMI_PLL_PLLCALI12_MASK > > + | UTMI_PLL_FBDIV_MASK | UTMI_PLL_REFDIV_MASK > > + | UTMI_PLL_ICP_MASK | UTMI_PLL_KVCO_MASK); > > + > > + u2o_set(base, UTMI_PLL, 0xee< > + | 0xb< > 3< > + | 3< > 3< > + | 1< > + > > + /* UTMI_TX */ > > + u2o_clear(base, UTMI_TX, UTMI_TX_REG_EXT_FS_RCAL_EN_MASK > > + | UTMI_TX_TXVDD12_MASK | UTMI_TX_CK60_PHSEL_MASK > > + | UTMI_TX_IMPCAL_VTH_MASK | > > UTMI_TX_REG_EXT_FS_RCAL_MASK > > + | UTMI_TX_AMP_MASK); > > + u2o_set(base, UTMI_TX, 3< > + | 4< > 4< > + | 8< > 3< > + > > + /* UTMI_RX */ > > + u2o_clear(base, UTMI_RX, UTMI_RX_SQ_THRESH_MASK > > + | UTMI_REG_SQ_LENGTH_MASK); > > + u2o_set(base, UTMI_RX, 7< > + | 2< > + > > + /* UTMI_IVREF */ > > + if (pxa_usb_phy->version == PXA_USB_PHY_PXA168) { > > + /* > > + * fixing Microsoft Altair board interface with NEC hub > > issue - > > + * Set UTMI_IVREF from 0x4a3 to 0x4bf > > + */ > > + u2o_write(base, UTMI_IVREF, 0x4bf); > > + } > > + > > + /* toggle VCOCAL_START bit of UTMI_PLL */ > > + udelay(200); > > + u2o_set(base, UTMI_PLL, VCOCAL_START); > > + udelay(40); > > + u2o_clear(base, UTMI_PLL, VCOCAL_START); > > + > > + /* toggle REG_RCAL_START bit of UTMI_TX */ > > + udelay(400); > > + u2o_set(base, UTMI_TX, REG_RCAL_START); > > + udelay(40); > > + u2o_clear(base, UTMI_TX, REG_RCAL_START); > > + udelay(400); > > + > > + /* Make sure PHY PLL is ready */ > > + loops = 0; > > + while ((u2o_get(base, UTMI_PLL) & PLL_READY) == 0) { > > + mdelay(1); > > + loops++; > > + if (loops > 100) { > > + dev_warn(&phy->dev, "calibrate timeout, > > UTMI_PLL %x\n", > > + u2o_get(base, > > UTMI_PLL)); > > + break; > > + } > > + } > > + > > + if (pxa_usb_phy->version == PXA_USB_PHY_PXA168) { > > + u2o_set(base, UTMI_RESERVE, 1 << 5); > > + /* Turn on UTMI PHY OTG extension */ > > + u2o_write(base, UTMI_OTG_ADDON, 1); > > + } > > + > > + return 0; > > + > > +} > > + > > +static int pxa_usb_phy_exit(struct phy *phy) > > +{ > > + struct pxa_usb_phy *pxa_usb_phy = phy_get_drvdata(phy); > > + void __iomem *base = pxa_usb_phy->base; > > + > > + dev_info(&phy->dev, "deinitializing Marvell PXA USB PHY"); > > + > > + if (pxa_usb_phy->version == PXA_USB_PHY_PXA168) > > + u2o_clear(base, UTMI_OTG_ADDON, UTMI_OTG_ADDON_OTG_ON); > > + > > + u2o_clear(base, UTMI_CTRL, UTMI_CTRL_RXBUF_PDWN); > > + u2o_clear(base, UTMI_CTRL, UTMI_CTRL_TXBUF_PDWN); > > + u2o_clear(base, UTMI_CTRL, UTMI_CTRL_USB_CLK_EN); > > + u2o_clear(base, UTMI_CTRL, 1< > + u2o_clear(base, UTMI_CTRL, 1< > + > > + return 0; > > +} > > + > > +static const struct phy_ops pxa_usb_phy_ops = { > > + .init = pxa_usb_phy_init, > > + .exit = pxa_usb_phy_exit, > > + .owner = THIS_MODULE, > > +}; > > + > > +static const struct of_device_id pxa_usb_phy_of_match[] = { > > + { > > + .compatible = "marvell,mmp2-usb-phy", > > + .data = (void *)PXA_USB_PHY_MMP2, > > + }, { > > + .compatible = "marvell,pxa910-usb-phy", > > + .data = (void *)PXA_USB_PHY_PXA910, > > + }, { > > + .compatible = "marvell,pxa168-usb-phy", > > + .data = (void *)PXA_USB_PHY_PXA168, > > + }, > > + { }, > > +}; > > +MODULE_DEVICE_TABLE(of, pxa_usb_phy_of_match); > > + > > +static int pxa_usb_phy_probe(struct platform_device *pdev) > > +{ > > + struct device *dev = &pdev->dev; > > + struct resource *resource; > > + struct pxa_usb_phy *pxa_usb_phy; > > + struct phy_provider *provider; > > + const struct of_device_id *of_id; > > + > > + pxa_usb_phy = devm_kzalloc(dev, sizeof(struct pxa_usb_phy), > > GFP_KERNEL); > > + if (!pxa_usb_phy) > > + return -ENOMEM; > > + > > + of_id = of_match_node(pxa_usb_phy_of_match, dev->of_node); > > + if (of_id) > > + pxa_usb_phy->version = (enum pxa_usb_phy_version)of_id- > > >data; > > + else > > + pxa_usb_phy->version = PXA_USB_PHY_MMP2; > > + > > + resource = platform_get_resource(pdev, IORESOURCE_MEM, 0); > > + pxa_usb_phy->base = devm_ioremap_resource(dev, resource); > > + if (IS_ERR(pxa_usb_phy->base)) { > > + dev_err(dev, "failed to remap PHY regs\n"); > > + return PTR_ERR(pxa_usb_phy->base); > > + } > > + > > + pxa_usb_phy->phy = devm_phy_create(dev, NULL, > > &pxa_usb_phy_ops); > > + if (IS_ERR(pxa_usb_phy->phy)) { > > + dev_err(dev, "failed to create PHY\n"); > > + return PTR_ERR(pxa_usb_phy->phy); > > + } > > + > > + phy_set_drvdata(pxa_usb_phy->phy, pxa_usb_phy); > > + provider = devm_of_phy_provider_register(dev, > > of_phy_simple_xlate); > > + if (IS_ERR(provider)) { > > + dev_err(dev, "failed to register PHY provider\n"); > > + return PTR_ERR(provider); > > + } > > + > > + if (!dev->of_node) { > > + phy_create_lookup(pxa_usb_phy->phy, "usb", "mv-udc"); > > + phy_create_lookup(pxa_usb_phy->phy, "usb", "pxa- > > u2oehci"); > > + phy_create_lookup(pxa_usb_phy->phy, "usb", "mv-otg"); > > + } > > + > > + dev_info(dev, "Marvell PXA USB PHY"); > > + return 0; > > +} > > + > > +static struct platform_driver pxa_usb_phy_driver = { > > + .probe = pxa_usb_phy_probe, > > + .driver = { > > + .name = "pxa-usb-phy", > > + .of_match_table = pxa_usb_phy_of_match, > > + }, > > +}; > > +module_platform_driver(pxa_usb_phy_driver); > > + > > +MODULE_AUTHOR("Lubomir Rintel "); > > +MODULE_DESCRIPTION("Marvell PXA USB PHY Driver"); > > +MODULE_LICENSE("GPL v2"); > > From mboxrd@z Thu Jan 1 00:00:00 1970 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: base64 Subject: [01/14] phy: phy-pxa-usb: add a new driver From: Lubomir Rintel Message-Id: <1981ce54ce960d21976ce71b08a8779bfeb13be4.camel@v3.sk> Date: Sun, 07 Oct 2018 20:47:28 +0200 To: Kishon Vijay Abraham I , linux-kernel@vger.kernel.org, Greg Kroah-Hartman Cc: linux-usb@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Rob Herring , Mark Rutland , Eric Miao , Haojian Zhuang , Alan Stern List-ID: T24gVHVlLCAyMDE4LTA5LTI1IGF0IDEwOjUzICswNTMwLCBLaXNob24gVmlqYXkgQWJyYWhhbSBJ IHdyb3RlOgo+IAo+IE9uIFRodXJzZGF5IDIzIEF1Z3VzdCAyMDE4IDAyOjEyIEFNLCBMdWJvbWly IFJpbnRlbCB3cm90ZToKPiA+IFR1cm5lZCBmcm9tIGFyY2gvYXJtL21hY2gtbW1wL2RldmljZXMu YyBpbnRvIGEgcHJvcGVyIFBIWSBkcml2ZXIsCj4gPiBzbwo+ID4gdGhhdCBpbiBjYW4gYmUgaW5z dGFudGlhdGVkIGZyb20gYSBEVC4KPiA+IAo+ID4gU2lnbmVkLW9mZi1ieTogTHVib21pciBSaW50 ZWwgPGxrdW5kcmFrQHYzLnNrPgo+IAo+IEFja2VkLWJ5OiBLaXNob24gVmlqYXkgQWJyYWhhbSBJ IDxraXNob25AdGkuY29tPgo+IAo+IElmIHRoaXMgaGFzIHRvIGJlIG1lcmdlZCB2aWEgbGludXgt cGh5IHRyZWUsIHBsZWFzZSBsZXQgbWUga25vdy4KClllcywgZWl0aGVyIGxpbnV4LXBoeSBvciB0 aGUgdXNiIHRyZWUuCgpUaGUgRUhDSSBwYXRjaGVzIGhhdmUgYWxyZWFkeSBiZWVuIHB1bGxlZCBp bnRvIHRoZSB1c2IgdHJlZSwgcHJlc3VtYWJseQpiZWNhdXNlIHRoZXkgZ290IGFuIEFjayBmcm9t IEFsYW4gU3Rlcm4uIFRoYXQgaW5jbHVkZXMgIlVTQjogRUhDSToKZWhjaS1tdjogdXNlIHBoeS1w eGEtdXNiIiB0aGF0IGRlcGVuZHMgb24gdGhpcy4gUGVyaGFwcyB0aGUgIHJlc3Qgb2YKdGhlIHBh dGNoZXMgY2FuIGdvIHZpYSB0aGUgc2FtZSB0cmVlPwoKSSBoYXZlbid0IHN1Ym1pdHRlZCBhIHBh dGNoc2V0IHRoYXQgd291bGQgaGF2ZSBkZXBlbmRlbmNpZXMgc3Bhbm5pbmcKYWNyb3NzIGRpZmZl cmVudCBzdWJzeXN0ZW1zIGJlZm9yZS4gSSBkb24ndCBrbm93IHdoYXQncyB1c3VhbGx5IGRvbmUg aW4Kc3VjaCBjYXNlcy4gQWR2aWNlIHdlbGNvbWUuCgpHcmVnPwoKPiBUaGFua3MKPiBLaXNob24K ClRoYW5rIHlvdQpMdWJvCgo+IAo+ID4gLS0tCj4gPiAgZHJpdmVycy9waHkvbWFydmVsbC9LY29u ZmlnICAgICAgIHwgIDExICsKPiA+ICBkcml2ZXJzL3BoeS9tYXJ2ZWxsL01ha2VmaWxlICAgICAg fCAgIDEgKwo+ID4gIGRyaXZlcnMvcGh5L21hcnZlbGwvcGh5LXB4YS11c2IuYyB8IDM0NQo+ID4g KysrKysrKysrKysrKysrKysrKysrKysrKysrKysrCj4gPiAgMyBmaWxlcyBjaGFuZ2VkLCAzNTcg aW5zZXJ0aW9ucygrKQo+ID4gIGNyZWF0ZSBtb2RlIDEwMDY0NCBkcml2ZXJzL3BoeS9tYXJ2ZWxs L3BoeS1weGEtdXNiLmMKPiA+IAo+ID4gZGlmZiAtLWdpdCBhL2RyaXZlcnMvcGh5L21hcnZlbGwv S2NvbmZpZwo+ID4gYi9kcml2ZXJzL3BoeS9tYXJ2ZWxsL0tjb25maWcKPiA+IGluZGV4IDY4ZTMy MTIyNTQwMC4uNmZiNGI1NmU0YzE0IDEwMDY0NAo+ID4gLS0tIGEvZHJpdmVycy9waHkvbWFydmVs bC9LY29uZmlnCj4gPiArKysgYi9kcml2ZXJzL3BoeS9tYXJ2ZWxsL0tjb25maWcKPiA+IEBAIC01 OSwzICs1OSwxNCBAQCBjb25maWcgUEhZX1BYQV8yOE5NX1VTQjIKPiA+ICAJICBUaGUgUEhZIGRy aXZlciB3aWxsIGJlIHVzZWQgYnkgTWFydmVsbCB1ZGMvZWhjaS9vdGcgZHJpdmVyLgo+ID4gIAo+ ID4gIAkgIFRvIGNvbXBpbGUgdGhpcyBkcml2ZXIgYXMgYSBtb2R1bGUsIGNob29zZSBNIGhlcmUu Cj4gPiArCj4gPiArY29uZmlnIFBIWV9QWEFfVVNCCj4gPiArCXRyaXN0YXRlICJNYXJ2ZWxsIFBY QSBVU0IgUEhZIERyaXZlciIKPiA+ICsJZGVwZW5kcyBvbiBBUkNIX1BYQSB8fCBBUkNIX01NUAo+ ID4gKwlzZWxlY3QgR0VORVJJQ19QSFkKPiA+ICsJaGVscAo+ID4gKwkgIEVuYWJsZSB0aGlzIHRv IHN1cHBvcnQgTWFydmVsbCBQWEEgVVNCIFBIWSBkcml2ZXIgZm9yIE1hcnZlbGwKPiA+ICsJICBT b0MuIFRoaXMgZHJpdmVyIHdpbGwgZG8gdGhlIFBIWSBpbml0aWFsaXphdGlvbiBhbmQgc2h1dGRv d24uCj4gPiArCSAgVGhlIFBIWSBkcml2ZXIgd2lsbCBiZSB1c2VkIGJ5IE1hcnZlbGwgdWRjL2Vo Y2kvb3RnIGRyaXZlci4KPiA+ICsKPiA+ICsJICBUbyBjb21waWxlIHRoaXMgZHJpdmVyIGFzIGEg bW9kdWxlLCBjaG9vc2UgTSBoZXJlLgo+ID4gZGlmZiAtLWdpdCBhL2RyaXZlcnMvcGh5L21hcnZl bGwvTWFrZWZpbGUKPiA+IGIvZHJpdmVycy9waHkvbWFydmVsbC9NYWtlZmlsZQo+ID4gaW5kZXgg NWMzZWM1ZDEwZTBkLi4zOTc1YjE0NGY4ZWMgMTAwNjQ0Cj4gPiAtLS0gYS9kcml2ZXJzL3BoeS9t YXJ2ZWxsL01ha2VmaWxlCj4gPiArKysgYi9kcml2ZXJzL3BoeS9tYXJ2ZWxsL01ha2VmaWxlCj4g PiBAQCAtNiwzICs2LDQgQEAgb2JqLSQoQ09ORklHX1BIWV9NVkVCVV9DUDExMF9DT01QSFkpCSs9 IHBoeS0KPiA+IG12ZWJ1LWNwMTEwLWNvbXBoeS5vCj4gPiAgb2JqLSQoQ09ORklHX1BIWV9NVkVC VV9TQVRBKQkJKz0gcGh5LW12ZWJ1LXNhdGEubwo+ID4gIG9iai0kKENPTkZJR19QSFlfUFhBXzI4 Tk1fSFNJQykJCSs9IHBoeS1weGEtMjhubS1oc2ljLm8KPiA+ICBvYmotJChDT05GSUdfUEhZX1BY QV8yOE5NX1VTQjIpCQkrPSBwaHktcHhhLTI4bm0tdXNiMi5vCj4gPiArb2JqLSQoQ09ORklHX1BI WV9QWEFfVVNCKQkJKz0gcGh5LXB4YS11c2Iubwo+ID4gZGlmZiAtLWdpdCBhL2RyaXZlcnMvcGh5 L21hcnZlbGwvcGh5LXB4YS11c2IuYwo+ID4gYi9kcml2ZXJzL3BoeS9tYXJ2ZWxsL3BoeS1weGEt dXNiLmMKPiA+IG5ldyBmaWxlIG1vZGUgMTAwNjQ0Cj4gPiBpbmRleCAwMDAwMDAwMDAwMDAuLjg3 ZmY3NTUwYjkxMgo+ID4gLS0tIC9kZXYvbnVsbAo+ID4gKysrIGIvZHJpdmVycy9waHkvbWFydmVs bC9waHktcHhhLXVzYi5jCj4gPiBAQCAtMCwwICsxLDM0NSBAQAo+ID4gKy8vIFNQRFgtTGljZW5z ZS1JZGVudGlmaWVyOiBHUEwtMi4wCj4gPiArLyoKPiA+ICsgKiBDb3B5cmlnaHQgKEMpIDIwMTEg TWFydmVsbCBJbnRlcm5hdGlvbmFsIEx0ZC4gQWxsIHJpZ2h0cwo+ID4gcmVzZXJ2ZWQuCj4gPiAr ICogQ29weXJpZ2h0IChDKSAyMDE4IEx1Ym9taXIgUmludGVsIDxsa3VuZHJha0B2My5zaz4KPiA+ ICsgKi8KPiA+ICsKPiA+ICsjaW5jbHVkZSA8ZHQtYmluZGluZ3MvcGh5L3BoeS5oPgo+ID4gKyNp bmNsdWRlIDxsaW51eC9jbGsuaD4KPiA+ICsjaW5jbHVkZSA8bGludXgvZGVsYXkuaD4KPiA+ICsj aW5jbHVkZSA8bGludXgvaW8uaD4KPiA+ICsjaW5jbHVkZSA8bGludXgvbW9kdWxlLmg+Cj4gPiAr I2luY2x1ZGUgPGxpbnV4L29mX2FkZHJlc3MuaD4KPiA+ICsjaW5jbHVkZSA8bGludXgvcGh5L3Bo eS5oPgo+ID4gKyNpbmNsdWRlIDxsaW51eC9wbGF0Zm9ybV9kZXZpY2UuaD4KPiA+ICsKPiA+ICsv KiBwaHkgcmVncyAqLwo+ID4gKyNkZWZpbmUgVVRNSV9SRVZJU0lPTgkJMHgwCj4gPiArI2RlZmlu ZSBVVE1JX0NUUkwJCTB4NAo+ID4gKyNkZWZpbmUgVVRNSV9QTEwJCTB4OAo+ID4gKyNkZWZpbmUg VVRNSV9UWAkJCTB4Ywo+ID4gKyNkZWZpbmUgVVRNSV9SWAkJCTB4MTAKPiA+ICsjZGVmaW5lIFVU TUlfSVZSRUYJCTB4MTQKPiA+ICsjZGVmaW5lIFVUTUlfVDAJCQkweDE4Cj4gPiArI2RlZmluZSBV VE1JX1QxCQkJMHgxYwo+ID4gKyNkZWZpbmUgVVRNSV9UMgkJCTB4MjAKPiA+ICsjZGVmaW5lIFVU TUlfVDMJCQkweDI0Cj4gPiArI2RlZmluZSBVVE1JX1Q0CQkJMHgyOAo+ID4gKyNkZWZpbmUgVVRN SV9UNQkJCTB4MmMKPiA+ICsjZGVmaW5lIFVUTUlfUkVTRVJWRQkJMHgzMAo+ID4gKyNkZWZpbmUg VVRNSV9VU0JfSU5UCQkweDM0Cj4gPiArI2RlZmluZSBVVE1JX0RCR19DVEwJCTB4MzgKPiA+ICsj ZGVmaW5lIFVUTUlfT1RHX0FERE9OCQkweDNjCj4gPiArCj4gPiArLyogRm9yIFVUTUlDVFJMIFJl Z2lzdGVyICovCj4gPiArI2RlZmluZSBVVE1JX0NUUkxfVVNCX0NMS19FTiAgICAgICAgICAgICAg ICAgICAgKDEgPDwgMzEpCj4gPiArLyogcHhhMTY4ICovCj4gPiArI2RlZmluZSBVVE1JX0NUUkxf U1VTUEVORF9TRVQxICAgICAgICAgICAgICAgICAgKDEgPDwgMzApCj4gPiArI2RlZmluZSBVVE1J X0NUUkxfU1VTUEVORF9TRVQyICAgICAgICAgICAgICAgICAgKDEgPDwgMjkpCj4gPiArI2RlZmlu ZSBVVE1JX0NUUkxfUlhCVUZfUERXTiAgICAgICAgICAgICAgICAgICAgKDEgPDwgMjQpCj4gPiAr I2RlZmluZSBVVE1JX0NUUkxfVFhCVUZfUERXTiAgICAgICAgICAgICAgICAgICAgKDEgPDwgMTEp Cj4gPiArCj4gPiArI2RlZmluZSBVVE1JX0NUUkxfSU5QS1RfREVMQVlfU0hJRlQgICAgICAgICAg ICAgMzAKPiA+ICsjZGVmaW5lIFVUTUlfQ1RSTF9JTlBLVF9ERUxBWV9TT0ZfU0hJRlQJCTI4Cj4g PiArI2RlZmluZSBVVE1JX0NUUkxfUFVfUkVGX1NISUZUCQkJMjAKPiA+ICsjZGVmaW5lIFVUTUlf Q1RSTF9BUkNfUFVMTEROX1NISUZUICAgICAgICAgICAgICAxMgo+ID4gKyNkZWZpbmUgVVRNSV9D VFJMX1BMTF9QV1JfVVBfU0hJRlQgICAgICAgICAgICAgIDEKPiA+ICsjZGVmaW5lIFVUTUlfQ1RS TF9QV1JfVVBfU0hJRlQgICAgICAgICAgICAgICAgICAwCj4gPiArCj4gPiArLyogRm9yIFVUTUlf UExMIFJlZ2lzdGVyICovCj4gPiArI2RlZmluZSBVVE1JX1BMTF9QTExDQUxJMTJfU0hJRlQJCTI5 Cj4gPiArI2RlZmluZSBVVE1JX1BMTF9QTExDQUxJMTJfTUFTSwkJCSgweDMgPDwgMjkpCj4gPiAr Cj4gPiArI2RlZmluZSBVVE1JX1BMTF9QTExWREQxOF9TSElGVAkJCTI3Cj4gPiArI2RlZmluZSBV VE1JX1BMTF9QTExWREQxOF9NQVNLCQkJKDB4MyA8PCAyNykKPiA+ICsKPiA+ICsjZGVmaW5lIFVU TUlfUExMX1BMTFZERDEyX1NISUZUCQkJMjUKPiA+ICsjZGVmaW5lIFVUTUlfUExMX1BMTFZERDEy X01BU0sJCQkoMHgzIDw8IDI1KQo+ID4gKwo+ID4gKyNkZWZpbmUgVVRNSV9QTExfQ0xLX0JMS19F Tl9TSElGVCAgICAgICAgICAgICAgIDI0Cj4gPiArI2RlZmluZSBDTEtfQkxLX0VOICAgICAgICAg ICAgICAgICAgICAgICAgICAgICAgKDB4MSA8PCAyNCkKPiA+ICsjZGVmaW5lIFBMTF9SRUFEWSAg ICAgICAgICAgICAgICAgICAgICAgICAgICAgICAoMHgxIDw8IDIzKQo+ID4gKyNkZWZpbmUgS1ZD T19FWFQgICAgICAgICAgICAgICAgICAgICAgICAgICAgICAgICgweDEgPDwgMjIpCj4gPiArI2Rl ZmluZSBWQ09DQUxfU1RBUlQgICAgICAgICAgICAgICAgICAgICAgICAgICAgKDB4MSA8PCAyMSkK PiA+ICsKPiA+ICsjZGVmaW5lIFVUTUlfUExMX0tWQ09fU0hJRlQJCQkxNQo+ID4gKyNkZWZpbmUg VVRNSV9QTExfS1ZDT19NQVNLICAgICAgICAgICAgICAgICAgICAgICgweDcgPDwgMTUpCj4gPiAr Cj4gPiArI2RlZmluZSBVVE1JX1BMTF9JQ1BfU0hJRlQJCQkxMgo+ID4gKyNkZWZpbmUgVVRNSV9Q TExfSUNQX01BU0sgICAgICAgICAgICAgICAgICAgICAgICgweDcgPDwgMTIpCj4gPiArCj4gPiAr I2RlZmluZSBVVE1JX1BMTF9GQkRJVl9TSElGVCAgICAgICAgICAgICAgICAgICAgNAo+ID4gKyNk ZWZpbmUgVVRNSV9QTExfRkJESVZfTUFTSyAgICAgICAgICAgICAgICAgICAgICgweEZGIDw8IDQp Cj4gPiArCj4gPiArI2RlZmluZSBVVE1JX1BMTF9SRUZESVZfU0hJRlQgICAgICAgICAgICAgICAg ICAgMAo+ID4gKyNkZWZpbmUgVVRNSV9QTExfUkVGRElWX01BU0sgICAgICAgICAgICAgICAgICAg ICgweEYgPDwgMCkKPiA+ICsKPiA+ICsvKiBGb3IgVVRNSV9UWCBSZWdpc3RlciAqLwo+ID4gKyNk ZWZpbmUgVVRNSV9UWF9SRUdfRVhUX0ZTX1JDQUxfU0hJRlQJCTI3Cj4gPiArI2RlZmluZSBVVE1J X1RYX1JFR19FWFRfRlNfUkNBTF9NQVNLCQkoMHhmIDw8IDI3KQo+ID4gKwo+ID4gKyNkZWZpbmUg VVRNSV9UWF9SRUdfRVhUX0ZTX1JDQUxfRU5fU0hJRlQJMjYKPiA+ICsjZGVmaW5lIFVUTUlfVFhf UkVHX0VYVF9GU19SQ0FMX0VOX01BU0sJCSgweDEgPDwgMjYpCj4gPiArCj4gPiArI2RlZmluZSBV VE1JX1RYX1RYVkREMTJfU0hJRlQgICAgICAgICAgICAgICAgICAgMjIKPiA+ICsjZGVmaW5lIFVU TUlfVFhfVFhWREQxMl9NQVNLICAgICAgICAgICAgICAgICAgICAoMHgzIDw8IDIyKQo+ID4gKwo+ ID4gKyNkZWZpbmUgVVRNSV9UWF9DSzYwX1BIU0VMX1NISUZUICAgICAgICAgICAgICAgIDE3Cj4g PiArI2RlZmluZSBVVE1JX1RYX0NLNjBfUEhTRUxfTUFTSyAgICAgICAgICAgICAgICAgKDB4ZiA8 PCAxNykKPiA+ICsKPiA+ICsjZGVmaW5lIFVUTUlfVFhfSU1QQ0FMX1ZUSF9TSElGVCAgICAgICAg ICAgICAgICAxNAo+ID4gKyNkZWZpbmUgVVRNSV9UWF9JTVBDQUxfVlRIX01BU0sgICAgICAgICAg ICAgICAgICgweDcgPDwgMTQpCj4gPiArCj4gPiArI2RlZmluZSBSRUdfUkNBTF9TVEFSVCAgICAg ICAgICAgICAgICAgICAgICAgICAgKDB4MSA8PCAxMikKPiA+ICsKPiA+ICsjZGVmaW5lIFVUTUlf VFhfTE9XX1ZERF9FTl9TSElGVCAgICAgICAgICAgICAgICAxMQo+ID4gKwo+ID4gKyNkZWZpbmUg VVRNSV9UWF9BTVBfU0hJRlQJCQkwCj4gPiArI2RlZmluZSBVVE1JX1RYX0FNUF9NQVNLCQkJKDB4 NyA8PCAwKQo+ID4gKwo+ID4gKy8qIEZvciBVVE1JX1JYIFJlZ2lzdGVyICovCj4gPiArI2RlZmlu ZSBVVE1JX1JFR19TUV9MRU5HVEhfU0hJRlQgICAgICAgICAgICAgICAgMTUKPiA+ICsjZGVmaW5l IFVUTUlfUkVHX1NRX0xFTkdUSF9NQVNLICAgICAgICAgICAgICAgICAoMHgzIDw8IDE1KQo+ID4g Kwo+ID4gKyNkZWZpbmUgVVRNSV9SWF9TUV9USFJFU0hfU0hJRlQgICAgICAgICAgICAgICAgIDQK PiA+ICsjZGVmaW5lIFVUTUlfUlhfU1FfVEhSRVNIX01BU0sgICAgICAgICAgICAgICAgICAoMHhm IDw8IDQpCj4gPiArCj4gPiArI2RlZmluZSBVVE1JX09UR19BRERPTl9PVEdfT04JCQkoMSA8PCAw KQo+ID4gKwo+ID4gK2VudW0gcHhhX3VzYl9waHlfdmVyc2lvbiB7Cj4gPiArCVBYQV9VU0JfUEhZ X01NUDIsCj4gPiArCVBYQV9VU0JfUEhZX1BYQTkxMCwKPiA+ICsJUFhBX1VTQl9QSFlfUFhBMTY4 LAo+ID4gK307Cj4gPiArCj4gPiArc3RydWN0IHB4YV91c2JfcGh5IHsKPiA+ICsJc3RydWN0IHBo eSAqcGh5Owo+ID4gKwl2b2lkIF9faW9tZW0gKmJhc2U7Cj4gPiArCWVudW0gcHhhX3VzYl9waHlf dmVyc2lvbiB2ZXJzaW9uOwo+ID4gK307Cj4gPiArCj4gPiArLyoqKioqKioqKioqKioqKioqKioq KioqKioqKioqKioqKioqKioqKioqKioqKioqKioqKioqKioqKioqKioqKioqCj4gPiAqKioqKioq KioqKioKPiA+ICsgKiBUaGUgcmVnaXN0ZXJzIHJlYWQvd3JpdGUgcm91dGluZXMKPiA+ICsKPiA+ ICoqKioqKioqKioqKioqKioqKioqKioqKioqKioqKioqKioqKioqKioqKioqKioqKioqKioqKioq KioqKioqKioqKioKPiA+ICoqKioqKioqKiovCj4gPiArCj4gPiArc3RhdGljIHVuc2lnbmVkIGlu dCB1Mm9fZ2V0KHZvaWQgX19pb21lbSAqYmFzZSwgdW5zaWduZWQgaW50Cj4gPiBvZmZzZXQpCj4g PiArewo+ID4gKwlyZXR1cm4gcmVhZGxfcmVsYXhlZChiYXNlICsgb2Zmc2V0KTsKPiA+ICt9Cj4g PiArCj4gPiArc3RhdGljIHZvaWQgdTJvX3NldCh2b2lkIF9faW9tZW0gKmJhc2UsIHVuc2lnbmVk IGludCBvZmZzZXQsCj4gPiArCQl1bnNpZ25lZCBpbnQgdmFsdWUpCj4gPiArewo+ID4gKwl1MzIg cmVnOwo+ID4gKwo+ID4gKwlyZWcgPSByZWFkbF9yZWxheGVkKGJhc2UgKyBvZmZzZXQpOwo+ID4g KwlyZWcgfD0gdmFsdWU7Cj4gPiArCXdyaXRlbF9yZWxheGVkKHJlZywgYmFzZSArIG9mZnNldCk7 Cj4gPiArCXJlYWRsX3JlbGF4ZWQoYmFzZSArIG9mZnNldCk7Cj4gPiArfQo+ID4gKwo+ID4gK3N0 YXRpYyB2b2lkIHUyb19jbGVhcih2b2lkIF9faW9tZW0gKmJhc2UsIHVuc2lnbmVkIGludCBvZmZz ZXQsCj4gPiArCQl1bnNpZ25lZCBpbnQgdmFsdWUpCj4gPiArewo+ID4gKwl1MzIgcmVnOwo+ID4g Kwo+ID4gKwlyZWcgPSByZWFkbF9yZWxheGVkKGJhc2UgKyBvZmZzZXQpOwo+ID4gKwlyZWcgJj0g fnZhbHVlOwo+ID4gKwl3cml0ZWxfcmVsYXhlZChyZWcsIGJhc2UgKyBvZmZzZXQpOwo+ID4gKwly ZWFkbF9yZWxheGVkKGJhc2UgKyBvZmZzZXQpOwo+ID4gK30KPiA+ICsKPiA+ICtzdGF0aWMgdm9p ZCB1Mm9fd3JpdGUodm9pZCBfX2lvbWVtICpiYXNlLCB1bnNpZ25lZCBpbnQgb2Zmc2V0LAo+ID4g KwkJdW5zaWduZWQgaW50IHZhbHVlKQo+ID4gK3sKPiA+ICsJd3JpdGVsX3JlbGF4ZWQodmFsdWUs IGJhc2UgKyBvZmZzZXQpOwo+ID4gKwlyZWFkbF9yZWxheGVkKGJhc2UgKyBvZmZzZXQpOwo+ID4g K30KPiA+ICsKPiA+ICtzdGF0aWMgaW50IHB4YV91c2JfcGh5X2luaXQoc3RydWN0IHBoeSAqcGh5 KQo+ID4gK3sKPiA+ICsJc3RydWN0IHB4YV91c2JfcGh5ICpweGFfdXNiX3BoeSA9IHBoeV9nZXRf ZHJ2ZGF0YShwaHkpOwo+ID4gKwl2b2lkIF9faW9tZW0gKmJhc2UgPSBweGFfdXNiX3BoeS0+YmFz ZTsKPiA+ICsJaW50IGxvb3BzOwo+ID4gKwo+ID4gKwlkZXZfaW5mbygmcGh5LT5kZXYsICJpbml0 aWFsaXppbmcgTWFydmVsbCBQWEEgVVNCIFBIWSIpOwo+ID4gKwo+ID4gKwkvKiBJbml0aWFsaXpl IHRoZSBVU0IgUEhZIHBvd2VyICovCj4gPiArCWlmIChweGFfdXNiX3BoeS0+dmVyc2lvbiA9PSBQ WEFfVVNCX1BIWV9QWEE5MTApIHsKPiA+ICsJCXUyb19zZXQoYmFzZSwgVVRNSV9DVFJMLAo+ID4g KDE8PFVUTUlfQ1RSTF9JTlBLVF9ERUxBWV9TT0ZfU0hJRlQpCj4gPiArCQkJfCAoMTw8VVRNSV9D VFJMX1BVX1JFRl9TSElGVCkpOwo+ID4gKwl9Cj4gPiArCj4gPiArCXUyb19zZXQoYmFzZSwgVVRN SV9DVFJMLCAxPDxVVE1JX0NUUkxfUExMX1BXUl9VUF9TSElGVCk7Cj4gPiArCXUyb19zZXQoYmFz ZSwgVVRNSV9DVFJMLCAxPDxVVE1JX0NUUkxfUFdSX1VQX1NISUZUKTsKPiA+ICsKPiA+ICsJLyog VVRNSV9QTEwgc2V0dGluZ3MgKi8KPiA+ICsJdTJvX2NsZWFyKGJhc2UsIFVUTUlfUExMLCBVVE1J X1BMTF9QTExWREQxOF9NQVNLCj4gPiArCQl8IFVUTUlfUExMX1BMTFZERDEyX01BU0sgfCBVVE1J X1BMTF9QTExDQUxJMTJfTUFTSwo+ID4gKwkJfCBVVE1JX1BMTF9GQkRJVl9NQVNLIHwgVVRNSV9Q TExfUkVGRElWX01BU0sKPiA+ICsJCXwgVVRNSV9QTExfSUNQX01BU0sgfCBVVE1JX1BMTF9LVkNP X01BU0spOwo+ID4gKwo+ID4gKwl1Mm9fc2V0KGJhc2UsIFVUTUlfUExMLCAweGVlPDxVVE1JX1BM TF9GQkRJVl9TSElGVAo+ID4gKwkJfCAweGI8PFVUTUlfUExMX1JFRkRJVl9TSElGVCB8Cj4gPiAz PDxVVE1JX1BMTF9QTExWREQxOF9TSElGVAo+ID4gKwkJfCAzPDxVVE1JX1BMTF9QTExWREQxMl9T SElGVCB8Cj4gPiAzPDxVVE1JX1BMTF9QTExDQUxJMTJfU0hJRlQKPiA+ICsJCXwgMTw8VVRNSV9Q TExfSUNQX1NISUZUIHwgMzw8VVRNSV9QTExfS1ZDT19TSElGVCk7Cj4gPiArCj4gPiArCS8qIFVU TUlfVFggKi8KPiA+ICsJdTJvX2NsZWFyKGJhc2UsIFVUTUlfVFgsIFVUTUlfVFhfUkVHX0VYVF9G U19SQ0FMX0VOX01BU0sKPiA+ICsJCXwgVVRNSV9UWF9UWFZERDEyX01BU0sgfCBVVE1JX1RYX0NL NjBfUEhTRUxfTUFTSwo+ID4gKwkJfCBVVE1JX1RYX0lNUENBTF9WVEhfTUFTSyB8Cj4gPiBVVE1J X1RYX1JFR19FWFRfRlNfUkNBTF9NQVNLCj4gPiArCQl8IFVUTUlfVFhfQU1QX01BU0spOwo+ID4g Kwl1Mm9fc2V0KGJhc2UsIFVUTUlfVFgsIDM8PFVUTUlfVFhfVFhWREQxMl9TSElGVAo+ID4gKwkJ fCA0PDxVVE1JX1RYX0NLNjBfUEhTRUxfU0hJRlQgfAo+ID4gNDw8VVRNSV9UWF9JTVBDQUxfVlRI X1NISUZUCj4gPiArCQl8IDg8PFVUTUlfVFhfUkVHX0VYVF9GU19SQ0FMX1NISUZUIHwKPiA+IDM8 PFVUTUlfVFhfQU1QX1NISUZUKTsKPiA+ICsKPiA+ICsJLyogVVRNSV9SWCAqLwo+ID4gKwl1Mm9f Y2xlYXIoYmFzZSwgVVRNSV9SWCwgVVRNSV9SWF9TUV9USFJFU0hfTUFTSwo+ID4gKwkJfCBVVE1J X1JFR19TUV9MRU5HVEhfTUFTSyk7Cj4gPiArCXUyb19zZXQoYmFzZSwgVVRNSV9SWCwgNzw8VVRN SV9SWF9TUV9USFJFU0hfU0hJRlQKPiA+ICsJCXwgMjw8VVRNSV9SRUdfU1FfTEVOR1RIX1NISUZU KTsKPiA+ICsKPiA+ICsJLyogVVRNSV9JVlJFRiAqLwo+ID4gKwlpZiAocHhhX3VzYl9waHktPnZl cnNpb24gPT0gUFhBX1VTQl9QSFlfUFhBMTY4KSB7Cj4gPiArCQkvKgo+ID4gKwkJICogZml4aW5n IE1pY3Jvc29mdCBBbHRhaXIgYm9hcmQgaW50ZXJmYWNlIHdpdGggTkVDIGh1Ygo+ID4gaXNzdWUg LQo+ID4gKwkJICogU2V0IFVUTUlfSVZSRUYgZnJvbSAweDRhMyB0byAweDRiZgo+ID4gKwkJICov Cj4gPiArCQl1Mm9fd3JpdGUoYmFzZSwgVVRNSV9JVlJFRiwgMHg0YmYpOwo+ID4gKwl9Cj4gPiAr Cj4gPiArCS8qIHRvZ2dsZSBWQ09DQUxfU1RBUlQgYml0IG9mIFVUTUlfUExMICovCj4gPiArCXVk ZWxheSgyMDApOwo+ID4gKwl1Mm9fc2V0KGJhc2UsIFVUTUlfUExMLCBWQ09DQUxfU1RBUlQpOwo+ ID4gKwl1ZGVsYXkoNDApOwo+ID4gKwl1Mm9fY2xlYXIoYmFzZSwgVVRNSV9QTEwsIFZDT0NBTF9T VEFSVCk7Cj4gPiArCj4gPiArCS8qIHRvZ2dsZSBSRUdfUkNBTF9TVEFSVCBiaXQgb2YgVVRNSV9U WCAqLwo+ID4gKwl1ZGVsYXkoNDAwKTsKPiA+ICsJdTJvX3NldChiYXNlLCBVVE1JX1RYLCBSRUdf UkNBTF9TVEFSVCk7Cj4gPiArCXVkZWxheSg0MCk7Cj4gPiArCXUyb19jbGVhcihiYXNlLCBVVE1J X1RYLCBSRUdfUkNBTF9TVEFSVCk7Cj4gPiArCXVkZWxheSg0MDApOwo+ID4gKwo+ID4gKwkvKiBN YWtlIHN1cmUgUEhZIFBMTCBpcyByZWFkeSAqLwo+ID4gKwlsb29wcyA9IDA7Cj4gPiArCXdoaWxl ICgodTJvX2dldChiYXNlLCBVVE1JX1BMTCkgJiBQTExfUkVBRFkpID09IDApIHsKPiA+ICsJCW1k ZWxheSgxKTsKPiA+ICsJCWxvb3BzKys7Cj4gPiArCQlpZiAobG9vcHMgPiAxMDApIHsKPiA+ICsJ CQlkZXZfd2FybigmcGh5LT5kZXYsICJjYWxpYnJhdGUgdGltZW91dCwKPiA+IFVUTUlfUExMICV4 XG4iLAo+ID4gKwkJCQkJCXUyb19nZXQoYmFzZSwKPiA+IFVUTUlfUExMKSk7Cj4gPiArCQkJYnJl YWs7Cj4gPiArCQl9Cj4gPiArCX0KPiA+ICsKPiA+ICsJaWYgKHB4YV91c2JfcGh5LT52ZXJzaW9u ID09IFBYQV9VU0JfUEhZX1BYQTE2OCkgewo+ID4gKwkJdTJvX3NldChiYXNlLCBVVE1JX1JFU0VS VkUsIDEgPDwgNSk7Cj4gPiArCQkvKiBUdXJuIG9uIFVUTUkgUEhZIE9URyBleHRlbnNpb24gKi8K PiA+ICsJCXUyb193cml0ZShiYXNlLCBVVE1JX09UR19BRERPTiwgMSk7Cj4gPiArCX0KPiA+ICsK PiA+ICsJcmV0dXJuIDA7Cj4gPiArCj4gPiArfQo+ID4gKwo+ID4gK3N0YXRpYyBpbnQgcHhhX3Vz Yl9waHlfZXhpdChzdHJ1Y3QgcGh5ICpwaHkpCj4gPiArewo+ID4gKwlzdHJ1Y3QgcHhhX3VzYl9w aHkgKnB4YV91c2JfcGh5ID0gcGh5X2dldF9kcnZkYXRhKHBoeSk7Cj4gPiArCXZvaWQgX19pb21l bSAqYmFzZSA9IHB4YV91c2JfcGh5LT5iYXNlOwo+ID4gKwo+ID4gKwlkZXZfaW5mbygmcGh5LT5k ZXYsICJkZWluaXRpYWxpemluZyBNYXJ2ZWxsIFBYQSBVU0IgUEhZIik7Cj4gPiArCj4gPiArCWlm IChweGFfdXNiX3BoeS0+dmVyc2lvbiA9PSBQWEFfVVNCX1BIWV9QWEExNjgpCj4gPiArCQl1Mm9f Y2xlYXIoYmFzZSwgVVRNSV9PVEdfQURET04sIFVUTUlfT1RHX0FERE9OX09UR19PTik7Cj4gPiAr Cj4gPiArCXUyb19jbGVhcihiYXNlLCBVVE1JX0NUUkwsIFVUTUlfQ1RSTF9SWEJVRl9QRFdOKTsK PiA+ICsJdTJvX2NsZWFyKGJhc2UsIFVUTUlfQ1RSTCwgVVRNSV9DVFJMX1RYQlVGX1BEV04pOwo+ ID4gKwl1Mm9fY2xlYXIoYmFzZSwgVVRNSV9DVFJMLCBVVE1JX0NUUkxfVVNCX0NMS19FTik7Cj4g PiArCXUyb19jbGVhcihiYXNlLCBVVE1JX0NUUkwsIDE8PFVUTUlfQ1RSTF9QV1JfVVBfU0hJRlQp Owo+ID4gKwl1Mm9fY2xlYXIoYmFzZSwgVVRNSV9DVFJMLCAxPDxVVE1JX0NUUkxfUExMX1BXUl9V UF9TSElGVCk7Cj4gPiArCj4gPiArCXJldHVybiAwOwo+ID4gK30KPiA+ICsKPiA+ICtzdGF0aWMg Y29uc3Qgc3RydWN0IHBoeV9vcHMgcHhhX3VzYl9waHlfb3BzID0gewo+ID4gKwkuaW5pdAk9IHB4 YV91c2JfcGh5X2luaXQsCj4gPiArCS5leGl0CT0gcHhhX3VzYl9waHlfZXhpdCwKPiA+ICsJLm93 bmVyCT0gVEhJU19NT0RVTEUsCj4gPiArfTsKPiA+ICsKPiA+ICtzdGF0aWMgY29uc3Qgc3RydWN0 IG9mX2RldmljZV9pZCBweGFfdXNiX3BoeV9vZl9tYXRjaFtdID0gewo+ID4gKwl7Cj4gPiArCQku Y29tcGF0aWJsZSA9ICJtYXJ2ZWxsLG1tcDItdXNiLXBoeSIsCj4gPiArCQkuZGF0YSA9ICh2b2lk ICopUFhBX1VTQl9QSFlfTU1QMiwKPiA+ICsJfSwgewo+ID4gKwkJLmNvbXBhdGlibGUgPSAibWFy dmVsbCxweGE5MTAtdXNiLXBoeSIsCj4gPiArCQkuZGF0YSA9ICh2b2lkICopUFhBX1VTQl9QSFlf UFhBOTEwLAo+ID4gKwl9LCB7Cj4gPiArCQkuY29tcGF0aWJsZSA9ICJtYXJ2ZWxsLHB4YTE2OC11 c2ItcGh5IiwKPiA+ICsJCS5kYXRhID0gKHZvaWQgKilQWEFfVVNCX1BIWV9QWEExNjgsCj4gPiAr CX0sCj4gPiArCXsgfSwKPiA+ICt9Owo+ID4gK01PRFVMRV9ERVZJQ0VfVEFCTEUob2YsIHB4YV91 c2JfcGh5X29mX21hdGNoKTsKPiA+ICsKPiA+ICtzdGF0aWMgaW50IHB4YV91c2JfcGh5X3Byb2Jl KHN0cnVjdCBwbGF0Zm9ybV9kZXZpY2UgKnBkZXYpCj4gPiArewo+ID4gKwlzdHJ1Y3QgZGV2aWNl ICpkZXYgPSAmcGRldi0+ZGV2Owo+ID4gKwlzdHJ1Y3QgcmVzb3VyY2UgKnJlc291cmNlOwo+ID4g KwlzdHJ1Y3QgcHhhX3VzYl9waHkgKnB4YV91c2JfcGh5Owo+ID4gKwlzdHJ1Y3QgcGh5X3Byb3Zp ZGVyICpwcm92aWRlcjsKPiA+ICsJY29uc3Qgc3RydWN0IG9mX2RldmljZV9pZCAqb2ZfaWQ7Cj4g PiArCj4gPiArCXB4YV91c2JfcGh5ID0gZGV2bV9remFsbG9jKGRldiwgc2l6ZW9mKHN0cnVjdCBw eGFfdXNiX3BoeSksCj4gPiBHRlBfS0VSTkVMKTsKPiA+ICsJaWYgKCFweGFfdXNiX3BoeSkKPiA+ ICsJCXJldHVybiAtRU5PTUVNOwo+ID4gKwo+ID4gKwlvZl9pZCA9IG9mX21hdGNoX25vZGUocHhh X3VzYl9waHlfb2ZfbWF0Y2gsIGRldi0+b2Zfbm9kZSk7Cj4gPiArCWlmIChvZl9pZCkKPiA+ICsJ CXB4YV91c2JfcGh5LT52ZXJzaW9uID0gKGVudW0gcHhhX3VzYl9waHlfdmVyc2lvbilvZl9pZC0K PiA+ID5kYXRhOwo+ID4gKwllbHNlCj4gPiArCQlweGFfdXNiX3BoeS0+dmVyc2lvbiA9IFBYQV9V U0JfUEhZX01NUDI7Cj4gPiArCj4gPiArCXJlc291cmNlID0gcGxhdGZvcm1fZ2V0X3Jlc291cmNl KHBkZXYsIElPUkVTT1VSQ0VfTUVNLCAwKTsKPiA+ICsJcHhhX3VzYl9waHktPmJhc2UgPSBkZXZt X2lvcmVtYXBfcmVzb3VyY2UoZGV2LCByZXNvdXJjZSk7Cj4gPiArCWlmIChJU19FUlIocHhhX3Vz Yl9waHktPmJhc2UpKSB7Cj4gPiArCQlkZXZfZXJyKGRldiwgImZhaWxlZCB0byByZW1hcCBQSFkg cmVnc1xuIik7Cj4gPiArCQlyZXR1cm4gUFRSX0VSUihweGFfdXNiX3BoeS0+YmFzZSk7Cj4gPiAr CX0KPiA+ICsKPiA+ICsJcHhhX3VzYl9waHktPnBoeSA9IGRldm1fcGh5X2NyZWF0ZShkZXYsIE5V TEwsCj4gPiAmcHhhX3VzYl9waHlfb3BzKTsKPiA+ICsJaWYgKElTX0VSUihweGFfdXNiX3BoeS0+ cGh5KSkgewo+ID4gKwkJZGV2X2VycihkZXYsICJmYWlsZWQgdG8gY3JlYXRlIFBIWVxuIik7Cj4g PiArCQlyZXR1cm4gUFRSX0VSUihweGFfdXNiX3BoeS0+cGh5KTsKPiA+ICsJfQo+ID4gKwo+ID4g KwlwaHlfc2V0X2RydmRhdGEocHhhX3VzYl9waHktPnBoeSwgcHhhX3VzYl9waHkpOwo+ID4gKwlw cm92aWRlciA9IGRldm1fb2ZfcGh5X3Byb3ZpZGVyX3JlZ2lzdGVyKGRldiwKPiA+IG9mX3BoeV9z aW1wbGVfeGxhdGUpOwo+ID4gKwlpZiAoSVNfRVJSKHByb3ZpZGVyKSkgewo+ID4gKwkJZGV2X2Vy cihkZXYsICJmYWlsZWQgdG8gcmVnaXN0ZXIgUEhZIHByb3ZpZGVyXG4iKTsKPiA+ICsJCXJldHVy biBQVFJfRVJSKHByb3ZpZGVyKTsKPiA+ICsJfQo+ID4gKwo+ID4gKwlpZiAoIWRldi0+b2Zfbm9k ZSkgewo+ID4gKwkJcGh5X2NyZWF0ZV9sb29rdXAocHhhX3VzYl9waHktPnBoeSwgInVzYiIsICJt di11ZGMiKTsKPiA+ICsJCXBoeV9jcmVhdGVfbG9va3VwKHB4YV91c2JfcGh5LT5waHksICJ1c2Ii LCAicHhhLQo+ID4gdTJvZWhjaSIpOwo+ID4gKwkJcGh5X2NyZWF0ZV9sb29rdXAocHhhX3VzYl9w aHktPnBoeSwgInVzYiIsICJtdi1vdGciKTsKPiA+ICsJfQo+ID4gKwo+ID4gKwlkZXZfaW5mbyhk ZXYsICJNYXJ2ZWxsIFBYQSBVU0IgUEhZIik7Cj4gPiArCXJldHVybiAwOwo+ID4gK30KPiA+ICsK PiA+ICtzdGF0aWMgc3RydWN0IHBsYXRmb3JtX2RyaXZlciBweGFfdXNiX3BoeV9kcml2ZXIgPSB7 Cj4gPiArCS5wcm9iZQkJPSBweGFfdXNiX3BoeV9wcm9iZSwKPiA+ICsJLmRyaXZlcgkJPSB7Cj4g PiArCQkubmFtZQk9ICJweGEtdXNiLXBoeSIsCj4gPiArCQkub2ZfbWF0Y2hfdGFibGUgPSBweGFf dXNiX3BoeV9vZl9tYXRjaCwKPiA+ICsJfSwKPiA+ICt9Owo+ID4gK21vZHVsZV9wbGF0Zm9ybV9k cml2ZXIocHhhX3VzYl9waHlfZHJpdmVyKTsKPiA+ICsKPiA+ICtNT0RVTEVfQVVUSE9SKCJMdWJv bWlyIFJpbnRlbCA8bGt1bmRyYWtAdjMuc2s+Iik7Cj4gPiArTU9EVUxFX0RFU0NSSVBUSU9OKCJN YXJ2ZWxsIFBYQSBVU0IgUEhZIERyaXZlciIpOwo+ID4gK01PRFVMRV9MSUNFTlNFKCJHUEwgdjIi KTsKPiA+Cg== From mboxrd@z Thu Jan 1 00:00:00 1970 From: lkundrak@v3.sk (Lubomir Rintel) Date: Sun, 07 Oct 2018 20:47:28 +0200 Subject: [PATCH 01/14] phy: phy-pxa-usb: add a new driver In-Reply-To: References: <20180822204307.13251-1-lkundrak@v3.sk> <20180822204307.13251-2-lkundrak@v3.sk> Message-ID: <1981ce54ce960d21976ce71b08a8779bfeb13be4.camel@v3.sk> To: linux-arm-kernel@lists.infradead.org List-Id: linux-arm-kernel.lists.infradead.org On Tue, 2018-09-25 at 10:53 +0530, Kishon Vijay Abraham I wrote: > > On Thursday 23 August 2018 02:12 AM, Lubomir Rintel wrote: > > Turned from arch/arm/mach-mmp/devices.c into a proper PHY driver, > > so > > that in can be instantiated from a DT. > > > > Signed-off-by: Lubomir Rintel > > Acked-by: Kishon Vijay Abraham I > > If this has to be merged via linux-phy tree, please let me know. Yes, either linux-phy or the usb tree. The EHCI patches have already been pulled into the usb tree, presumably because they got an Ack from Alan Stern. That includes "USB: EHCI: ehci-mv: use phy-pxa-usb" that depends on this. Perhaps the rest of the patches can go via the same tree? I haven't submitted a patchset that would have dependencies spanning across different subsystems before. I don't know what's usually done in such cases. Advice welcome. Greg? > Thanks > Kishon Thank you Lubo > > > --- > > drivers/phy/marvell/Kconfig | 11 + > > drivers/phy/marvell/Makefile | 1 + > > drivers/phy/marvell/phy-pxa-usb.c | 345 > > ++++++++++++++++++++++++++++++ > > 3 files changed, 357 insertions(+) > > create mode 100644 drivers/phy/marvell/phy-pxa-usb.c > > > > diff --git a/drivers/phy/marvell/Kconfig > > b/drivers/phy/marvell/Kconfig > > index 68e321225400..6fb4b56e4c14 100644 > > --- a/drivers/phy/marvell/Kconfig > > +++ b/drivers/phy/marvell/Kconfig > > @@ -59,3 +59,14 @@ config PHY_PXA_28NM_USB2 > > The PHY driver will be used by Marvell udc/ehci/otg driver. > > > > To compile this driver as a module, choose M here. > > + > > +config PHY_PXA_USB > > + tristate "Marvell PXA USB PHY Driver" > > + depends on ARCH_PXA || ARCH_MMP > > + select GENERIC_PHY > > + help > > + Enable this to support Marvell PXA USB PHY driver for Marvell > > + SoC. This driver will do the PHY initialization and shutdown. > > + The PHY driver will be used by Marvell udc/ehci/otg driver. > > + > > + To compile this driver as a module, choose M here. > > diff --git a/drivers/phy/marvell/Makefile > > b/drivers/phy/marvell/Makefile > > index 5c3ec5d10e0d..3975b144f8ec 100644 > > --- a/drivers/phy/marvell/Makefile > > +++ b/drivers/phy/marvell/Makefile > > @@ -6,3 +6,4 @@ obj-$(CONFIG_PHY_MVEBU_CP110_COMPHY) += phy- > > mvebu-cp110-comphy.o > > obj-$(CONFIG_PHY_MVEBU_SATA) += phy-mvebu-sata.o > > obj-$(CONFIG_PHY_PXA_28NM_HSIC) += phy-pxa-28nm-hsic.o > > obj-$(CONFIG_PHY_PXA_28NM_USB2) += phy-pxa-28nm-usb2.o > > +obj-$(CONFIG_PHY_PXA_USB) += phy-pxa-usb.o > > diff --git a/drivers/phy/marvell/phy-pxa-usb.c > > b/drivers/phy/marvell/phy-pxa-usb.c > > new file mode 100644 > > index 000000000000..87ff7550b912 > > --- /dev/null > > +++ b/drivers/phy/marvell/phy-pxa-usb.c > > @@ -0,0 +1,345 @@ > > +// SPDX-License-Identifier: GPL-2.0 > > +/* > > + * Copyright (C) 2011 Marvell International Ltd. All rights > > reserved. > > + * Copyright (C) 2018 Lubomir Rintel > > + */ > > + > > +#include > > +#include > > +#include > > +#include > > +#include > > +#include > > +#include > > +#include > > + > > +/* phy regs */ > > +#define UTMI_REVISION 0x0 > > +#define UTMI_CTRL 0x4 > > +#define UTMI_PLL 0x8 > > +#define UTMI_TX 0xc > > +#define UTMI_RX 0x10 > > +#define UTMI_IVREF 0x14 > > +#define UTMI_T0 0x18 > > +#define UTMI_T1 0x1c > > +#define UTMI_T2 0x20 > > +#define UTMI_T3 0x24 > > +#define UTMI_T4 0x28 > > +#define UTMI_T5 0x2c > > +#define UTMI_RESERVE 0x30 > > +#define UTMI_USB_INT 0x34 > > +#define UTMI_DBG_CTL 0x38 > > +#define UTMI_OTG_ADDON 0x3c > > + > > +/* For UTMICTRL Register */ > > +#define UTMI_CTRL_USB_CLK_EN (1 << 31) > > +/* pxa168 */ > > +#define UTMI_CTRL_SUSPEND_SET1 (1 << 30) > > +#define UTMI_CTRL_SUSPEND_SET2 (1 << 29) > > +#define UTMI_CTRL_RXBUF_PDWN (1 << 24) > > +#define UTMI_CTRL_TXBUF_PDWN (1 << 11) > > + > > +#define UTMI_CTRL_INPKT_DELAY_SHIFT 30 > > +#define UTMI_CTRL_INPKT_DELAY_SOF_SHIFT 28 > > +#define UTMI_CTRL_PU_REF_SHIFT 20 > > +#define UTMI_CTRL_ARC_PULLDN_SHIFT 12 > > +#define UTMI_CTRL_PLL_PWR_UP_SHIFT 1 > > +#define UTMI_CTRL_PWR_UP_SHIFT 0 > > + > > +/* For UTMI_PLL Register */ > > +#define UTMI_PLL_PLLCALI12_SHIFT 29 > > +#define UTMI_PLL_PLLCALI12_MASK (0x3 << 29) > > + > > +#define UTMI_PLL_PLLVDD18_SHIFT 27 > > +#define UTMI_PLL_PLLVDD18_MASK (0x3 << 27) > > + > > +#define UTMI_PLL_PLLVDD12_SHIFT 25 > > +#define UTMI_PLL_PLLVDD12_MASK (0x3 << 25) > > + > > +#define UTMI_PLL_CLK_BLK_EN_SHIFT 24 > > +#define CLK_BLK_EN (0x1 << 24) > > +#define PLL_READY (0x1 << 23) > > +#define KVCO_EXT (0x1 << 22) > > +#define VCOCAL_START (0x1 << 21) > > + > > +#define UTMI_PLL_KVCO_SHIFT 15 > > +#define UTMI_PLL_KVCO_MASK (0x7 << 15) > > + > > +#define UTMI_PLL_ICP_SHIFT 12 > > +#define UTMI_PLL_ICP_MASK (0x7 << 12) > > + > > +#define UTMI_PLL_FBDIV_SHIFT 4 > > +#define UTMI_PLL_FBDIV_MASK (0xFF << 4) > > + > > +#define UTMI_PLL_REFDIV_SHIFT 0 > > +#define UTMI_PLL_REFDIV_MASK (0xF << 0) > > + > > +/* For UTMI_TX Register */ > > +#define UTMI_TX_REG_EXT_FS_RCAL_SHIFT 27 > > +#define UTMI_TX_REG_EXT_FS_RCAL_MASK (0xf << 27) > > + > > +#define UTMI_TX_REG_EXT_FS_RCAL_EN_SHIFT 26 > > +#define UTMI_TX_REG_EXT_FS_RCAL_EN_MASK (0x1 << 26) > > + > > +#define UTMI_TX_TXVDD12_SHIFT 22 > > +#define UTMI_TX_TXVDD12_MASK (0x3 << 22) > > + > > +#define UTMI_TX_CK60_PHSEL_SHIFT 17 > > +#define UTMI_TX_CK60_PHSEL_MASK (0xf << 17) > > + > > +#define UTMI_TX_IMPCAL_VTH_SHIFT 14 > > +#define UTMI_TX_IMPCAL_VTH_MASK (0x7 << 14) > > + > > +#define REG_RCAL_START (0x1 << 12) > > + > > +#define UTMI_TX_LOW_VDD_EN_SHIFT 11 > > + > > +#define UTMI_TX_AMP_SHIFT 0 > > +#define UTMI_TX_AMP_MASK (0x7 << 0) > > + > > +/* For UTMI_RX Register */ > > +#define UTMI_REG_SQ_LENGTH_SHIFT 15 > > +#define UTMI_REG_SQ_LENGTH_MASK (0x3 << 15) > > + > > +#define UTMI_RX_SQ_THRESH_SHIFT 4 > > +#define UTMI_RX_SQ_THRESH_MASK (0xf << 4) > > + > > +#define UTMI_OTG_ADDON_OTG_ON (1 << 0) > > + > > +enum pxa_usb_phy_version { > > + PXA_USB_PHY_MMP2, > > + PXA_USB_PHY_PXA910, > > + PXA_USB_PHY_PXA168, > > +}; > > + > > +struct pxa_usb_phy { > > + struct phy *phy; > > + void __iomem *base; > > + enum pxa_usb_phy_version version; > > +}; > > + > > +/***************************************************************** > > ************ > > + * The registers read/write routines > > + > > ******************************************************************* > > **********/ > > + > > +static unsigned int u2o_get(void __iomem *base, unsigned int > > offset) > > +{ > > + return readl_relaxed(base + offset); > > +} > > + > > +static void u2o_set(void __iomem *base, unsigned int offset, > > + unsigned int value) > > +{ > > + u32 reg; > > + > > + reg = readl_relaxed(base + offset); > > + reg |= value; > > + writel_relaxed(reg, base + offset); > > + readl_relaxed(base + offset); > > +} > > + > > +static void u2o_clear(void __iomem *base, unsigned int offset, > > + unsigned int value) > > +{ > > + u32 reg; > > + > > + reg = readl_relaxed(base + offset); > > + reg &= ~value; > > + writel_relaxed(reg, base + offset); > > + readl_relaxed(base + offset); > > +} > > + > > +static void u2o_write(void __iomem *base, unsigned int offset, > > + unsigned int value) > > +{ > > + writel_relaxed(value, base + offset); > > + readl_relaxed(base + offset); > > +} > > + > > +static int pxa_usb_phy_init(struct phy *phy) > > +{ > > + struct pxa_usb_phy *pxa_usb_phy = phy_get_drvdata(phy); > > + void __iomem *base = pxa_usb_phy->base; > > + int loops; > > + > > + dev_info(&phy->dev, "initializing Marvell PXA USB PHY"); > > + > > + /* Initialize the USB PHY power */ > > + if (pxa_usb_phy->version == PXA_USB_PHY_PXA910) { > > + u2o_set(base, UTMI_CTRL, > > (1< > + | (1< > + } > > + > > + u2o_set(base, UTMI_CTRL, 1< > + u2o_set(base, UTMI_CTRL, 1< > + > > + /* UTMI_PLL settings */ > > + u2o_clear(base, UTMI_PLL, UTMI_PLL_PLLVDD18_MASK > > + | UTMI_PLL_PLLVDD12_MASK | UTMI_PLL_PLLCALI12_MASK > > + | UTMI_PLL_FBDIV_MASK | UTMI_PLL_REFDIV_MASK > > + | UTMI_PLL_ICP_MASK | UTMI_PLL_KVCO_MASK); > > + > > + u2o_set(base, UTMI_PLL, 0xee< > + | 0xb< > 3< > + | 3< > 3< > + | 1< > + > > + /* UTMI_TX */ > > + u2o_clear(base, UTMI_TX, UTMI_TX_REG_EXT_FS_RCAL_EN_MASK > > + | UTMI_TX_TXVDD12_MASK | UTMI_TX_CK60_PHSEL_MASK > > + | UTMI_TX_IMPCAL_VTH_MASK | > > UTMI_TX_REG_EXT_FS_RCAL_MASK > > + | UTMI_TX_AMP_MASK); > > + u2o_set(base, UTMI_TX, 3< > + | 4< > 4< > + | 8< > 3< > + > > + /* UTMI_RX */ > > + u2o_clear(base, UTMI_RX, UTMI_RX_SQ_THRESH_MASK > > + | UTMI_REG_SQ_LENGTH_MASK); > > + u2o_set(base, UTMI_RX, 7< > + | 2< > + > > + /* UTMI_IVREF */ > > + if (pxa_usb_phy->version == PXA_USB_PHY_PXA168) { > > + /* > > + * fixing Microsoft Altair board interface with NEC hub > > issue - > > + * Set UTMI_IVREF from 0x4a3 to 0x4bf > > + */ > > + u2o_write(base, UTMI_IVREF, 0x4bf); > > + } > > + > > + /* toggle VCOCAL_START bit of UTMI_PLL */ > > + udelay(200); > > + u2o_set(base, UTMI_PLL, VCOCAL_START); > > + udelay(40); > > + u2o_clear(base, UTMI_PLL, VCOCAL_START); > > + > > + /* toggle REG_RCAL_START bit of UTMI_TX */ > > + udelay(400); > > + u2o_set(base, UTMI_TX, REG_RCAL_START); > > + udelay(40); > > + u2o_clear(base, UTMI_TX, REG_RCAL_START); > > + udelay(400); > > + > > + /* Make sure PHY PLL is ready */ > > + loops = 0; > > + while ((u2o_get(base, UTMI_PLL) & PLL_READY) == 0) { > > + mdelay(1); > > + loops++; > > + if (loops > 100) { > > + dev_warn(&phy->dev, "calibrate timeout, > > UTMI_PLL %x\n", > > + u2o_get(base, > > UTMI_PLL)); > > + break; > > + } > > + } > > + > > + if (pxa_usb_phy->version == PXA_USB_PHY_PXA168) { > > + u2o_set(base, UTMI_RESERVE, 1 << 5); > > + /* Turn on UTMI PHY OTG extension */ > > + u2o_write(base, UTMI_OTG_ADDON, 1); > > + } > > + > > + return 0; > > + > > +} > > + > > +static int pxa_usb_phy_exit(struct phy *phy) > > +{ > > + struct pxa_usb_phy *pxa_usb_phy = phy_get_drvdata(phy); > > + void __iomem *base = pxa_usb_phy->base; > > + > > + dev_info(&phy->dev, "deinitializing Marvell PXA USB PHY"); > > + > > + if (pxa_usb_phy->version == PXA_USB_PHY_PXA168) > > + u2o_clear(base, UTMI_OTG_ADDON, UTMI_OTG_ADDON_OTG_ON); > > + > > + u2o_clear(base, UTMI_CTRL, UTMI_CTRL_RXBUF_PDWN); > > + u2o_clear(base, UTMI_CTRL, UTMI_CTRL_TXBUF_PDWN); > > + u2o_clear(base, UTMI_CTRL, UTMI_CTRL_USB_CLK_EN); > > + u2o_clear(base, UTMI_CTRL, 1< > + u2o_clear(base, UTMI_CTRL, 1< > + > > + return 0; > > +} > > + > > +static const struct phy_ops pxa_usb_phy_ops = { > > + .init = pxa_usb_phy_init, > > + .exit = pxa_usb_phy_exit, > > + .owner = THIS_MODULE, > > +}; > > + > > +static const struct of_device_id pxa_usb_phy_of_match[] = { > > + { > > + .compatible = "marvell,mmp2-usb-phy", > > + .data = (void *)PXA_USB_PHY_MMP2, > > + }, { > > + .compatible = "marvell,pxa910-usb-phy", > > + .data = (void *)PXA_USB_PHY_PXA910, > > + }, { > > + .compatible = "marvell,pxa168-usb-phy", > > + .data = (void *)PXA_USB_PHY_PXA168, > > + }, > > + { }, > > +}; > > +MODULE_DEVICE_TABLE(of, pxa_usb_phy_of_match); > > + > > +static int pxa_usb_phy_probe(struct platform_device *pdev) > > +{ > > + struct device *dev = &pdev->dev; > > + struct resource *resource; > > + struct pxa_usb_phy *pxa_usb_phy; > > + struct phy_provider *provider; > > + const struct of_device_id *of_id; > > + > > + pxa_usb_phy = devm_kzalloc(dev, sizeof(struct pxa_usb_phy), > > GFP_KERNEL); > > + if (!pxa_usb_phy) > > + return -ENOMEM; > > + > > + of_id = of_match_node(pxa_usb_phy_of_match, dev->of_node); > > + if (of_id) > > + pxa_usb_phy->version = (enum pxa_usb_phy_version)of_id- > > >data; > > + else > > + pxa_usb_phy->version = PXA_USB_PHY_MMP2; > > + > > + resource = platform_get_resource(pdev, IORESOURCE_MEM, 0); > > + pxa_usb_phy->base = devm_ioremap_resource(dev, resource); > > + if (IS_ERR(pxa_usb_phy->base)) { > > + dev_err(dev, "failed to remap PHY regs\n"); > > + return PTR_ERR(pxa_usb_phy->base); > > + } > > + > > + pxa_usb_phy->phy = devm_phy_create(dev, NULL, > > &pxa_usb_phy_ops); > > + if (IS_ERR(pxa_usb_phy->phy)) { > > + dev_err(dev, "failed to create PHY\n"); > > + return PTR_ERR(pxa_usb_phy->phy); > > + } > > + > > + phy_set_drvdata(pxa_usb_phy->phy, pxa_usb_phy); > > + provider = devm_of_phy_provider_register(dev, > > of_phy_simple_xlate); > > + if (IS_ERR(provider)) { > > + dev_err(dev, "failed to register PHY provider\n"); > > + return PTR_ERR(provider); > > + } > > + > > + if (!dev->of_node) { > > + phy_create_lookup(pxa_usb_phy->phy, "usb", "mv-udc"); > > + phy_create_lookup(pxa_usb_phy->phy, "usb", "pxa- > > u2oehci"); > > + phy_create_lookup(pxa_usb_phy->phy, "usb", "mv-otg"); > > + } > > + > > + dev_info(dev, "Marvell PXA USB PHY"); > > + return 0; > > +} > > + > > +static struct platform_driver pxa_usb_phy_driver = { > > + .probe = pxa_usb_phy_probe, > > + .driver = { > > + .name = "pxa-usb-phy", > > + .of_match_table = pxa_usb_phy_of_match, > > + }, > > +}; > > +module_platform_driver(pxa_usb_phy_driver); > > + > > +MODULE_AUTHOR("Lubomir Rintel "); > > +MODULE_DESCRIPTION("Marvell PXA USB PHY Driver"); > > +MODULE_LICENSE("GPL v2"); > >