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[174.21.143.238]) by smtp.gmail.com with ESMTPSA id q6sm23143723pff.79.2020.06.25.10.42.54 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Thu, 25 Jun 2020 10:42:54 -0700 (PDT) Subject: Re: [PATCH v3 2/8] target/ppc: add byte-reverse br[dwh] instructions To: Lijun Pan , qemu-ppc@nongnu.org, qemu-devel@nongnu.org References: <20200625170018.64265-1-ljp@linux.ibm.com> <20200625170018.64265-3-ljp@linux.ibm.com> From: Richard Henderson Message-ID: <199eadcf-9d05-ce25-8b7a-6a0e1a01c1a1@linaro.org> Date: Thu, 25 Jun 2020 10:42:52 -0700 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:68.0) Gecko/20100101 Thunderbird/68.8.0 MIME-Version: 1.0 In-Reply-To: <20200625170018.64265-3-ljp@linux.ibm.com> Content-Type: text/plain; charset=utf-8 Content-Language: en-US Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2607:f8b0:4864:20::642; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x642.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=_AUTOLEARN X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: david@gibson.dropbear.id.au Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" On 6/25/20 10:00 AM, Lijun Pan wrote: > +static void gen_brh(DisasContext *ctx) > +{ > + TCGv_i64 t0 = tcg_temp_new_i64(); > + TCGv_i64 t1 = tcg_temp_new_i64(); > + TCGv_i64 t2 = tcg_temp_new_i64(); > + > + tcg_gen_movi_i64(t0, 0x00ff00ff00ff00ffull); > + tcg_gen_shri_i64(t1, cpu_gpr[rS(ctx->opcode)], 8); > + tcg_gen_and_i64(t2, t1, t0); > + tcg_gen_and_i64(t1, cpu_gpr[rS(ctx->opcode)], t0); > + tcg_gen_shli_i64(t1, t1, 8); > + tcg_gen_or_i64(cpu_gpr[rA(ctx->opcode)], t1, t2); > + > + tcg_temp_free_i64(t0); > + tcg_temp_free_i64(t1); > + tcg_temp_free_i64(t2); > +} > + > static opcode_t opcodes[] = { > +#if defined(TARGET_PPC64) > +GEN_HANDLER_E(brd, 0x1F, 0x1B, 0x05, 0x0000F801, PPC_NONE, PPC2_ISA310), > +GEN_HANDLER_E(brw, 0x1F, 0x1B, 0x04, 0x0000F801, PPC_NONE, PPC2_ISA310), > +GEN_HANDLER_E(brh, 0x1F, 0x1B, 0x06, 0x0000F801, PPC_NONE, PPC2_ISA310), > +#endif No. You haven't even tested this -- it doesn't compile. > CC ppc-softmmu/target/ppc/translate.o > /home/rth/qemu/qemu/target/ppc/translate.c: In function ‘gen_brd’: > /home/rth/qemu/qemu/target/ppc/translate.c:6980:32: error: passing argument 1 of ‘tcg_gen_bswap64_i64’ from incompatible pointer type [-Werror=incompatible-pointer-types] > 6980 | tcg_gen_bswap64_i64(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]); > | ~~~~~~~^~~~~~~~~~~~~~~~~ > | | > | TCGv_i32 {aka struct TCGv_i32_d *} > In file included from /home/rth/qemu/qemu/target/ppc/translate.c:26: > /home/rth/qemu/qemu/include/tcg/tcg-op.h:533:35: note: expected ‘TCGv_i64’ {aka ‘struct TCGv_i64_d *’} but argument is of type ‘TCGv_i32’ {aka ‘struct TCGv_i32_d *’} > 533 | void tcg_gen_bswap64_i64(TCGv_i64 ret, TCGv_i64 arg); > | ~~~~~~~~~^~~ > /home/rth/qemu/qemu/target/ppc/translate.c:6980:58: error: passing argument 2 of ‘tcg_gen_bswap64_i64’ from incompatible pointer type [-Werror=incompatible-pointer-types] > 6980 | tcg_gen_bswap64_i64(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]); > | ~~~~~~~^~~~~~~~~~~~~~~~~ > | | > | TCGv_i32 {aka struct TCGv_i32_d *} and so forth. I warned you before about this. Why are you still building only a restricted set of targets? r~