From mboxrd@z Thu Jan 1 00:00:00 1970 From: "Dong, Eddie" Subject: RE: [PATCH 06/16] vmx: nest: handling VMX instruction exits Date: Wed, 15 Sep 2010 17:08:20 +0800 Message-ID: <1A42CE6F5F474C41B63392A5F80372B22A8C22C9@shsmsx501.ccr.corp.intel.com> References: <201009151015.20193.Christoph.Egger@amd.com> Mime-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable Return-path: In-Reply-To: Content-Language: en-US List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Sender: xen-devel-bounces@lists.xensource.com Errors-To: xen-devel-bounces@lists.xensource.com To: Keir Fraser , Christoph Egger , "xen-devel@lists.xensource.com" Cc: Tim Deegan , "Dong, Eddie" , "He, Qing" List-Id: xen-devel@lists.xenproject.org Keir Fraser wrote: > On 15/09/2010 09:15, "Christoph Egger" > wrote:=20 >=20 >>> The main trick with x86_emulate extensions is determining the >>> correct neat small set of callback hooks to add, which is somewhat >>> driven by deciding what should be emulated within x86_emulate and >>> what should be left without for implementation in the caller's >>> context.=20 >>=20 >> There is a case where the host must emulate an instruction of the l2 >> guest when the l1 guest doesn't intercept it. >>=20 >> When the vcpu is in guest mode, the fields in struct hvm_vcpu and >> guest_cpu_user_regs() represent the l2 guest state in my patch >> series.=20 >>=20 >> That way the instruction emulator works out-of-the box. >=20 > Well in this specific case, all VMX-related instructions executed by > an L2 guest would properly cause vmexit to the L1 guest for emulation > there. We wouldn't want to emulate in Xen. Yes, in nested VMX side, we L0 VMM won't emulate L2 VMX instruction. >=20 > But yes I can see that emulation of L2 guest instructions is needed > in some other cases. Like instructions performing I/O in areas which > L1 thinks it has given L2 direct unmediated access to, but which Xen > is actually filtering or emulating. That may be an issue in plan when we support virtual VT-d for nested I/O pe= rformance. But not now :) I suggest we leave that to future at least for nested VMX side where L0 VMM= doesn't directly emulate L0 VMM instruction. We can see if there are other needs for that kind of case. Thx, Eddie=