From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-0.6 required=3.0 tests=DKIM_INVALID,DKIM_SIGNED, HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS autolearn=no autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id DA338C5518C for ; Wed, 22 Apr 2020 07:11:12 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id B7F522076E for ; Wed, 22 Apr 2020 07:11:12 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=fail reason="signature verification failed" (2048-bit key) header.d=goldelico.com header.i=@goldelico.com header.b="Yp8bxIcS" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726445AbgDVHLM (ORCPT ); Wed, 22 Apr 2020 03:11:12 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:33968 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S1725907AbgDVHLL (ORCPT ); Wed, 22 Apr 2020 03:11:11 -0400 Received: from mo6-p02-ob.smtp.rzone.de (mo6-p02-ob.smtp.rzone.de [IPv6:2a01:238:20a:202:5302::7]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 1ED86C03C1A6; Wed, 22 Apr 2020 00:11:09 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; t=1587539467; s=strato-dkim-0002; d=goldelico.com; h=To:References:Message-Id:Cc:Date:In-Reply-To:From:Subject: X-RZG-CLASS-ID:X-RZG-AUTH:From:Subject:Sender; bh=x9g4xzih9SHZrw00RWoUucyKrGmw7cFSE/C08UHHhbo=; b=Yp8bxIcS44j849A4MQvicvK+yl4C/uCwDApU0g29MmNVcsvsvTuHIxW7Wto7j197z5 L/kKtTxuuE6CG2/5RL0QZALxSiwemqThf8bOHNIz2OelEWuYlKXdwItCeKamyLUEhUKu aXNEUs4mRpVdtGsS/GqYALWb7M5mUrqPCCyusa48oz/SoYsR0a3FmBZxcgXBPOqrqxVS hCJMkxsZXJcTtXwyTqkQQHtp3CB9zTUo1AbAJa98QSgeyHi6M3S0SRVYUMqJ1L1+t5T5 YykSgrFeiE3kQ8VN5618m3/R4uS5M0DC065X+0zrl1hZJOpevb71xhVx/zyr09+VGDGv dBdw== X-RZG-AUTH: ":JGIXVUS7cutRB/49FwqZ7WcJeFKiMgPgp8VKxflSZ1P34KBp5hRw/qOxWRk4dCym3NRQH2PRBNS67Wq1XcMUsV9wfG0LbuNrxINn" X-RZG-CLASS-ID: mo00 Received: from [IPv6:2001:16b8:263a:4100:a53d:b96b:debd:cf9d] by smtp.strato.de (RZmta 46.6.1 AUTH) with ESMTPSA id e09987w3M7Ao19A (using TLSv1 with cipher ECDHE-RSA-AES256-SHA (curve X9_62_prime256v1 with 256 ECDH bits, eq. 3072 bits RSA)) (Client did not present a certificate); Wed, 22 Apr 2020 09:10:50 +0200 (CEST) Subject: Re: [PATCH v6 00/12] ARM/MIPS: DTS: add child nodes describing the PVRSGX GPU present in some OMAP SoC and JZ4780 (and many more) Mime-Version: 1.0 (Mac OS X Mail 9.3 \(3124\)) Content-Type: text/plain; charset=us-ascii From: "H. Nikolaus Schaller" In-Reply-To: <20200422065859.quy6ane5v7vsy5tf@gilmour.lan> Date: Wed, 22 Apr 2020 09:10:57 +0200 Cc: Tony Lindgren , Philipp Rossak , Jonathan Bakker , David Airlie , Daniel Vetter , Rob Herring , Mark Rutland , =?utf-8?Q?Beno=C3=AEt_Cousson?= , Paul Cercueil , Ralf Baechle , Paul Burton , James Hogan , Kukjin Kim , Krzysztof Kozlowski , Chen-Yu Tsai , Thomas Bogendoerfer , "open list:DRM PANEL DRIVERS" , "open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS" , Linux Kernel Mailing List , linux-omap , OpenPVRSGX Linux Driver Group , Discussions about the Letux Kernel , kernel@pyra-handheld.com, linux-mips@vger.kernel.org, arm-soc , linux-samsung-soc@vger.kernel.org Content-Transfer-Encoding: quoted-printable Message-Id: <1AA57A0C-48E6-49BB-BB9A-2AAFFB371BCD@goldelico.com> References: <20200415101008.zxzxca2vlfsefpdv@gilmour.lan> <2E3401F1-A106-4396-8FE6-51CAB72926A4@goldelico.com> <20200415130233.rgn7xrtwqicptke2@gilmour.lan> <10969e64-fe1f-d692-4984-4ba916bd2161@gmail.com> <20200420073842.nx4xb3zqvu23arkc@gilmour.lan> <20200421112129.zjmkmzo3aftksgka@gilmour.lan> <20200421141543.GU37466@atomide.com> <20200422065859.quy6ane5v7vsy5tf@gilmour.lan> To: Maxime Ripard X-Mailer: Apple Mail (2.3124) Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Hi Maxime, > Am 22.04.2020 um 08:58 schrieb Maxime Ripard : >=20 > On Tue, Apr 21, 2020 at 07:29:32PM +0200, H. Nikolaus Schaller wrote: >>=20 >>> Am 21.04.2020 um 16:15 schrieb Tony Lindgren : >>>=20 >>> * Maxime Ripard [200421 11:22]: >>>> On Tue, Apr 21, 2020 at 11:57:33AM +0200, Philipp Rossak wrote: >>>>> I had a look on genpd and I'm not really sure if that fits. >>>>>=20 >>>>> It is basically some bit that verify that the clocks should be = enabled or >>>>> disabled. >>>>=20 >>>> No, it can do much more than that. It's a framework to control the = SoCs power >>>> domains, so clocks might be a part of it, but most of the time it's = going to be >>>> about powering up a particular device. >>>=20 >>> Note that on omaps there are actually SoC module specific registers. >>=20 >> Ah, I see. This is of course a difference that the TI glue logic has >> its own registers in the same address range as the sgx and this can't >> be easily handled by a common sgx driver. >>=20 >> This indeed seems to be unique with omap. >>=20 >>> And there can be multiple devices within a single target module on >>> omaps. So the extra dts node and device is justified there. >>>=20 >>> For other SoCs, the SGX clocks are probably best handled directly >>> in pvr-drv.c PM runtime functions unless a custom hardware wrapper >>> with SoC specific registers exists. >>=20 >> That is why we need to evaluate what the better strategy is. >>=20 >> So we have >> a) omap which has a custom wrapper around the sgx >> b) others without, i.e. an empty (or pass-through) wrapper >>=20 >> Which one do we make the "standard" and which one the "exception"? >> What are good reasons for either one? >>=20 >>=20 >> I am currently in strong favour of a) being standard because it >> makes the pvr-drv.c simpler and really generic (independent of >> wrapping into any SoC). >>=20 >> This will likely avoid problems if we find more SoC with yet another >> scheme how the SGX clocks are wrapped. >>=20 >> It also allows to handle different number of clocks (A31 seems to >> need 4, Samsung, A83 and JZ4780 one) without changing the sgx = bindings >> or making big lists of conditionals. This variance would be handled >> outside the sgx core bindings and driver. >=20 > I disagree. Every other GPU binding and driver is handling that just = fine, and > the SGX is not special in any case here. Can you please better explain this? With example or a description or a proposal? I simply do not have your experience with "every other GPU" as you have. And I admit that I can't read from your statement what we should do to bring this topic forward. So please make a proposal how it should be in your view. BR and thanks, Nikolaus From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-0.8 required=3.0 tests=DKIMWL_WL_HIGH,DKIM_SIGNED, DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI,SPF_HELO_NONE, SPF_PASS,URIBL_BLOCKED autolearn=no autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id F0675C5518A for ; Wed, 22 Apr 2020 07:12:06 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id BFB2C206CD for ; Wed, 22 Apr 2020 07:12:06 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=lists.infradead.org header.i=@lists.infradead.org header.b="sTih8Sqa"; dkim=fail reason="signature verification failed" (2048-bit key) header.d=goldelico.com header.i=@goldelico.com header.b="TOTnJfVZ" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org BFB2C206CD Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=goldelico.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=linux-arm-kernel-bounces+infradead-linux-arm-kernel=archiver.kernel.org@lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20170209; h=Sender: Content-Transfer-Encoding:Content-Type:Cc:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:To:References:Message-Id:Date: In-Reply-To:From:Mime-Version:Subject:Reply-To:Content-ID:Content-Description :Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=PP5kncqyF9K/kwbRgm9lJSyyHKxK8pHYPp4G39B7O10=; b=sTih8SqasGxGbv zfQGoIneF9DfmyjGqz6KYz76aUyxVTDJ2Z0umN+eapk8m6dJzMDrMdP3AfQxGhRT690VSIl7u5Ast azCnAwgex8nVW1XhO+wkHNG27uGu5I7GtZACEB19MiK4nQH3OSJXtpRInLSkxqfUsMKqVCMl0NJVt YCOJsSFrMiGH+fSeN02OGvRJafYoxw9jKs3jIXzaUSuawPZEJBl6TvkPLssC1cbRdBqoWibukgCcS Knwsbjm/BLPRWuchkA5jWgGsm55bIriM9qXdOKtvl1j+E/mwbmuG+RtxarRNjN6etye/OtMZ+d6oB S4xzgMXwzPPfmCcIaa1w==; Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.92.3 #3 (Red Hat Linux)) id 1jR9YA-00050r-5a; Wed, 22 Apr 2020 07:12:02 +0000 Received: from mo6-p02-ob.smtp.rzone.de ([2a01:238:20a:202:5302::1]) by bombadil.infradead.org with esmtps (Exim 4.92.3 #3 (Red Hat Linux)) id 1jR9XC-0004Q6-R1 for linux-arm-kernel@lists.infradead.org; Wed, 22 Apr 2020 07:11:05 +0000 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; t=1587539459; s=strato-dkim-0002; d=goldelico.com; h=To:References:Message-Id:Cc:Date:In-Reply-To:From:Subject: X-RZG-CLASS-ID:X-RZG-AUTH:From:Subject:Sender; bh=x9g4xzih9SHZrw00RWoUucyKrGmw7cFSE/C08UHHhbo=; b=TOTnJfVZF9bPbRIHvpbxY/ow04cTKjkqSMgWBMX3uBa/4WsfhR3gsWnxWSPJh9jZSr u5cS8W/im9ONHG5ng3jJcfAkkfRfJI0vir6FdWiQ87ngdUERfYYCFj/gvMydEwTiYo0B pAw8e2MIlql11qz070g1yXYICpe3f4ldzgkJhisvQy7YMGiYyNYXTtAtPmop62jY6e7R r6QM0NAZbdZ2WE1IalnWiteMuFuANw3ueLnqDxe1dzo8mAZBmGXAmgluKG0XWDeT4tEw 96MDAWG5KF+xGZbrb10EOk9gbK38fkZTgOC7tevjVVcizBXTtB4NaInaBXxFVwwqMn7G 3bNA== X-RZG-AUTH: ":JGIXVUS7cutRB/49FwqZ7WcJeFKiMgPgp8VKxflSZ1P34KBp5hRw/qOxWRk4dCym3NRQH2PRBNS67Wq1XcMUsV9wfG0LbuNrxINn" X-RZG-CLASS-ID: mo00 Received: from [IPv6:2001:16b8:263a:4100:a53d:b96b:debd:cf9d] by smtp.strato.de (RZmta 46.6.1 AUTH) with ESMTPSA id e09987w3M7Ao19A (using TLSv1 with cipher ECDHE-RSA-AES256-SHA (curve X9_62_prime256v1 with 256 ECDH bits, eq. 3072 bits RSA)) (Client did not present a certificate); Wed, 22 Apr 2020 09:10:50 +0200 (CEST) Subject: Re: [PATCH v6 00/12] ARM/MIPS: DTS: add child nodes describing the PVRSGX GPU present in some OMAP SoC and JZ4780 (and many more) Mime-Version: 1.0 (Mac OS X Mail 9.3 \(3124\)) From: "H. Nikolaus Schaller" In-Reply-To: <20200422065859.quy6ane5v7vsy5tf@gilmour.lan> Date: Wed, 22 Apr 2020 09:10:57 +0200 Message-Id: <1AA57A0C-48E6-49BB-BB9A-2AAFFB371BCD@goldelico.com> References: <20200415101008.zxzxca2vlfsefpdv@gilmour.lan> <2E3401F1-A106-4396-8FE6-51CAB72926A4@goldelico.com> <20200415130233.rgn7xrtwqicptke2@gilmour.lan> <10969e64-fe1f-d692-4984-4ba916bd2161@gmail.com> <20200420073842.nx4xb3zqvu23arkc@gilmour.lan> <20200421112129.zjmkmzo3aftksgka@gilmour.lan> <20200421141543.GU37466@atomide.com> <20200422065859.quy6ane5v7vsy5tf@gilmour.lan> To: Maxime Ripard X-Mailer: Apple Mail (2.3124) X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20200422_001103_490549_0189BD13 X-CRM114-Status: GOOD ( 16.09 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Mark Rutland , Tony Lindgren , James Hogan , Jonathan Bakker , "open list:DRM PANEL DRIVERS" , linux-mips@vger.kernel.org, Paul Cercueil , linux-samsung-soc@vger.kernel.org, Discussions about the Letux Kernel , Paul Burton , Krzysztof Kozlowski , David Airlie , Chen-Yu Tsai , Kukjin Kim , "open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS" , Daniel Vetter , Rob Herring , linux-omap , arm-soc , Thomas Bogendoerfer , Philipp Rossak , OpenPVRSGX Linux Driver Group , Linux Kernel Mailing List , Ralf Baechle , =?utf-8?Q?Beno=C3=AEt_Cousson?= , kernel@pyra-handheld.com Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+infradead-linux-arm-kernel=archiver.kernel.org@lists.infradead.org Hi Maxime, > Am 22.04.2020 um 08:58 schrieb Maxime Ripard : > > On Tue, Apr 21, 2020 at 07:29:32PM +0200, H. Nikolaus Schaller wrote: >> >>> Am 21.04.2020 um 16:15 schrieb Tony Lindgren : >>> >>> * Maxime Ripard [200421 11:22]: >>>> On Tue, Apr 21, 2020 at 11:57:33AM +0200, Philipp Rossak wrote: >>>>> I had a look on genpd and I'm not really sure if that fits. >>>>> >>>>> It is basically some bit that verify that the clocks should be enabled or >>>>> disabled. >>>> >>>> No, it can do much more than that. It's a framework to control the SoCs power >>>> domains, so clocks might be a part of it, but most of the time it's going to be >>>> about powering up a particular device. >>> >>> Note that on omaps there are actually SoC module specific registers. >> >> Ah, I see. This is of course a difference that the TI glue logic has >> its own registers in the same address range as the sgx and this can't >> be easily handled by a common sgx driver. >> >> This indeed seems to be unique with omap. >> >>> And there can be multiple devices within a single target module on >>> omaps. So the extra dts node and device is justified there. >>> >>> For other SoCs, the SGX clocks are probably best handled directly >>> in pvr-drv.c PM runtime functions unless a custom hardware wrapper >>> with SoC specific registers exists. >> >> That is why we need to evaluate what the better strategy is. >> >> So we have >> a) omap which has a custom wrapper around the sgx >> b) others without, i.e. an empty (or pass-through) wrapper >> >> Which one do we make the "standard" and which one the "exception"? >> What are good reasons for either one? >> >> >> I am currently in strong favour of a) being standard because it >> makes the pvr-drv.c simpler and really generic (independent of >> wrapping into any SoC). >> >> This will likely avoid problems if we find more SoC with yet another >> scheme how the SGX clocks are wrapped. >> >> It also allows to handle different number of clocks (A31 seems to >> need 4, Samsung, A83 and JZ4780 one) without changing the sgx bindings >> or making big lists of conditionals. This variance would be handled >> outside the sgx core bindings and driver. > > I disagree. Every other GPU binding and driver is handling that just fine, and > the SGX is not special in any case here. Can you please better explain this? With example or a description or a proposal? I simply do not have your experience with "every other GPU" as you have. And I admit that I can't read from your statement what we should do to bring this topic forward. So please make a proposal how it should be in your view. BR and thanks, Nikolaus _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-0.6 required=3.0 tests=DKIM_INVALID,DKIM_SIGNED, HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS autolearn=no autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 7D4F8C54FD0 for ; Thu, 23 Apr 2020 07:37:00 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 92676208E4 for ; Thu, 23 Apr 2020 07:36:59 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=fail reason="signature verification failed" (2048-bit key) header.d=goldelico.com header.i=@goldelico.com header.b="frz6YUvN" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 92676208E4 Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=goldelico.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=dri-devel-bounces@lists.freedesktop.org Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id BDCC16E1D8; Thu, 23 Apr 2020 07:36:40 +0000 (UTC) Received: from mo6-p02-ob.smtp.rzone.de (mo6-p02-ob.smtp.rzone.de [IPv6:2a01:238:20a:202:5302::6]) by gabe.freedesktop.org (Postfix) with ESMTPS id 182356E342 for ; Wed, 22 Apr 2020 07:11:12 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; t=1587539471; s=strato-dkim-0002; d=goldelico.com; h=To:References:Message-Id:Cc:Date:In-Reply-To:From:Subject: X-RZG-CLASS-ID:X-RZG-AUTH:From:Subject:Sender; bh=x9g4xzih9SHZrw00RWoUucyKrGmw7cFSE/C08UHHhbo=; b=frz6YUvNIFgehAyAc1WFWX6TSRxQFDnLE4v7iuQoUOjNgVDEYM/Jf13BLalo7TQEI+ jMVi8PYy3367sHAu8jdvFBPE1KmYmHhhGttSgC1pMuMQbpkBsS2rQyUWu10kJnskme2H me4+1TIydhLE2Y2QkKISYynG+hrPk0WTgyvCwGiL6Fdn4OSCB+BrXAEY80aIIL2ehqB+ owK9YxD8nrgsPEOtDr/KfTSP4YIBo6RAwWnyoDWCwBWRY8Io+pLppe/Y639y695voVeM OaDFvgvsr6IlydqeDCspuH0vG8ybX/UPKbfV2F2dq0/mrEZ4ZC8Ry08W/OPsHNCfVnmA 6qLA== X-RZG-AUTH: ":JGIXVUS7cutRB/49FwqZ7WcJeFKiMgPgp8VKxflSZ1P34KBp5hRw/qOxWRk4dCym3NRQH2PRBNS67Wq1XcMUsV9wfG0LbuNrxINn" X-RZG-CLASS-ID: mo00 Received: from [IPv6:2001:16b8:263a:4100:a53d:b96b:debd:cf9d] by smtp.strato.de (RZmta 46.6.1 AUTH) with ESMTPSA id e09987w3M7Ao19A (using TLSv1 with cipher ECDHE-RSA-AES256-SHA (curve X9_62_prime256v1 with 256 ECDH bits, eq. 3072 bits RSA)) (Client did not present a certificate); Wed, 22 Apr 2020 09:10:50 +0200 (CEST) Subject: Re: [PATCH v6 00/12] ARM/MIPS: DTS: add child nodes describing the PVRSGX GPU present in some OMAP SoC and JZ4780 (and many more) Mime-Version: 1.0 (Mac OS X Mail 9.3 \(3124\)) From: "H. Nikolaus Schaller" In-Reply-To: <20200422065859.quy6ane5v7vsy5tf@gilmour.lan> Date: Wed, 22 Apr 2020 09:10:57 +0200 Message-Id: <1AA57A0C-48E6-49BB-BB9A-2AAFFB371BCD@goldelico.com> References: <20200415101008.zxzxca2vlfsefpdv@gilmour.lan> <2E3401F1-A106-4396-8FE6-51CAB72926A4@goldelico.com> <20200415130233.rgn7xrtwqicptke2@gilmour.lan> <10969e64-fe1f-d692-4984-4ba916bd2161@gmail.com> <20200420073842.nx4xb3zqvu23arkc@gilmour.lan> <20200421112129.zjmkmzo3aftksgka@gilmour.lan> <20200421141543.GU37466@atomide.com> <20200422065859.quy6ane5v7vsy5tf@gilmour.lan> To: Maxime Ripard X-Mailer: Apple Mail (2.3124) X-Mailman-Approved-At: Thu, 23 Apr 2020 07:36:39 +0000 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Mark Rutland , Tony Lindgren , James Hogan , Jonathan Bakker , "open list:DRM PANEL DRIVERS" , linux-mips@vger.kernel.org, Paul Cercueil , linux-samsung-soc@vger.kernel.org, Discussions about the Letux Kernel , Paul Burton , Krzysztof Kozlowski , David Airlie , Chen-Yu Tsai , Kukjin Kim , "open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS" , Rob Herring , linux-omap , arm-soc , Thomas Bogendoerfer , Philipp Rossak , OpenPVRSGX Linux Driver Group , Linux Kernel Mailing List , Ralf Baechle , =?utf-8?Q?Beno=C3=AEt_Cousson?= , kernel@pyra-handheld.com Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" Hi Maxime, > Am 22.04.2020 um 08:58 schrieb Maxime Ripard : > > On Tue, Apr 21, 2020 at 07:29:32PM +0200, H. Nikolaus Schaller wrote: >> >>> Am 21.04.2020 um 16:15 schrieb Tony Lindgren : >>> >>> * Maxime Ripard [200421 11:22]: >>>> On Tue, Apr 21, 2020 at 11:57:33AM +0200, Philipp Rossak wrote: >>>>> I had a look on genpd and I'm not really sure if that fits. >>>>> >>>>> It is basically some bit that verify that the clocks should be enabled or >>>>> disabled. >>>> >>>> No, it can do much more than that. It's a framework to control the SoCs power >>>> domains, so clocks might be a part of it, but most of the time it's going to be >>>> about powering up a particular device. >>> >>> Note that on omaps there are actually SoC module specific registers. >> >> Ah, I see. This is of course a difference that the TI glue logic has >> its own registers in the same address range as the sgx and this can't >> be easily handled by a common sgx driver. >> >> This indeed seems to be unique with omap. >> >>> And there can be multiple devices within a single target module on >>> omaps. So the extra dts node and device is justified there. >>> >>> For other SoCs, the SGX clocks are probably best handled directly >>> in pvr-drv.c PM runtime functions unless a custom hardware wrapper >>> with SoC specific registers exists. >> >> That is why we need to evaluate what the better strategy is. >> >> So we have >> a) omap which has a custom wrapper around the sgx >> b) others without, i.e. an empty (or pass-through) wrapper >> >> Which one do we make the "standard" and which one the "exception"? >> What are good reasons for either one? >> >> >> I am currently in strong favour of a) being standard because it >> makes the pvr-drv.c simpler and really generic (independent of >> wrapping into any SoC). >> >> This will likely avoid problems if we find more SoC with yet another >> scheme how the SGX clocks are wrapped. >> >> It also allows to handle different number of clocks (A31 seems to >> need 4, Samsung, A83 and JZ4780 one) without changing the sgx bindings >> or making big lists of conditionals. This variance would be handled >> outside the sgx core bindings and driver. > > I disagree. Every other GPU binding and driver is handling that just fine, and > the SGX is not special in any case here. Can you please better explain this? With example or a description or a proposal? I simply do not have your experience with "every other GPU" as you have. And I admit that I can't read from your statement what we should do to bring this topic forward. So please make a proposal how it should be in your view. BR and thanks, Nikolaus _______________________________________________ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel