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From: "Nadathur, Sundar" <sundar.nadathur@intel.com>
To: Moritz Fischer <moritz.fischer@ettus.com>,
        Jason Gunthorpe <jgunthorpe@obsidianresearch.com>
CC: Alan Tull <delicious.quinoa@gmail.com>,
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Subject: RE: [RFC 7/8] fpga-region: add sysfs interface
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Date: Wed, 22 Feb 2017 05:46:10 +0000
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On February 21, 2017 9:39 PM, Moritz Fischer wrote:

> TLV Seems easy enough. To give an update, I played with fdt a bit to see how
> far I get in half an hour. I got bool / int / strings to work quite fast (~30mins).
> Please disregard the horrible hackyness of this ...
> [...]
> So I'm fairly convinced I can make this work, TVLs seem like it could work,
> too.
> 
> > So far the only thing we know we need is a 'bool' for encrypted and a
> > stringish guid thing for partial reconfiguration.

These things have a way of growing beyond their original anticipated needs. 

> Yeah, shouldn't be hard to implement either way.
> 
> Cheers,
> 
> Moritz

Say we upstream a metadata parser. Subsequently, an FPGA image is released with an additional metadata field that the upstreamed version does not handle. How will this be handled if the metadata were in FDT or KVP format?

Thanks,
Sundar