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From: Richard Henderson <richard.henderson@linaro.org>
To: Peter Maydell <peter.maydell@linaro.org>,
	qemu-arm@nongnu.org, qemu-devel@nongnu.org
Cc: "Philippe Mathieu-Daudé" <f4bug@amsat.org>
Subject: Re: [PATCH v2 09/12] target/arm: Optimize MVE VSHL, VSHR immediate forms
Date: Mon, 13 Sep 2021 06:56:16 -0700	[thread overview]
Message-ID: <1a0247d3-f472-546d-b838-dcacb640d282@linaro.org> (raw)
In-Reply-To: <20210913095440.13462-10-peter.maydell@linaro.org>

On 9/13/21 2:54 AM, Peter Maydell wrote:
> +static void do_gvec_shri_s(unsigned vece, uint32_t dofs, uint32_t aofs,
> +                           int64_t shift, uint32_t oprsz, uint32_t maxsz)
> +{
> +    /*
> +     * We get here with a negated shift count, and we must handle
> +     * shifts by the element size, which tcg_gen_gvec_sari() does not do.
> +     */
> +    shift = -shift;

You've already performed the negation in do_2shift_vec.

> +    if (shift == (8 << vece)) {
> +        shift--;
> +    }
> +    tcg_gen_gvec_sari(vece, dofs, aofs, shift, oprsz, maxsz);
...
> +    if (shift == (8 << vece)) {
> +        tcg_gen_gvec_dup_imm(vece, dofs, oprsz, maxsz, 0);
> +    } else {
> +        tcg_gen_gvec_shri(vece, dofs, aofs, shift, oprsz, maxsz);
> +    }


Perhaps worth placing these functions somewhere we can share code with NEON?  Tactical 
error, perhaps, open-coding these tests in trans_VSHR_S_2sh and trans_VSHR_U_2sh.

r~


  reply	other threads:[~2021-09-13 14:33 UTC|newest]

Thread overview: 28+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-09-13  9:54 [PATCH v2 00/12] target/arm: Use TCG vector ops for MVE Peter Maydell
2021-09-13  9:54 ` [PATCH v2 01/12] target/arm: Avoid goto_tb if we're trying to exit to the main loop Peter Maydell
2021-09-13 13:36   ` Richard Henderson
2021-09-13  9:54 ` [PATCH v2 02/12] target/arm: Enforce that FPDSCR.LTPSIZE is 4 on inbound migration Peter Maydell
2021-09-13 13:39   ` Richard Henderson
2021-09-13  9:54 ` [PATCH v2 03/12] target/arm: Add TB flag for "MVE insns not predicated" Peter Maydell
2021-09-13 13:44   ` Richard Henderson
2021-09-13  9:54 ` [PATCH v2 04/12] target/arm: Optimize MVE logic ops Peter Maydell
2021-09-13  9:54 ` [PATCH v2 05/12] target/arm: Optimize MVE arithmetic ops Peter Maydell
2021-09-13  9:54 ` [PATCH v2 06/12] target/arm: Optimize MVE VNEG, VABS Peter Maydell
2021-09-13  9:54 ` [PATCH v2 07/12] target/arm: Optimize MVE VDUP Peter Maydell
2021-09-13 13:46   ` Richard Henderson
2021-09-13  9:54 ` [PATCH v2 08/12] target/arm: Optimize MVE VMVN Peter Maydell
2021-09-13 13:47   ` Richard Henderson
2021-09-13  9:54 ` [PATCH v2 09/12] target/arm: Optimize MVE VSHL, VSHR immediate forms Peter Maydell
2021-09-13 13:56   ` Richard Henderson [this message]
2021-09-13 14:21     ` Peter Maydell
2021-09-13 15:53       ` Richard Henderson
2021-09-16 10:01         ` Peter Maydell
2021-09-16 14:39           ` Richard Henderson
2021-09-13  9:54 ` [PATCH v2 10/12] target/arm: Optimize MVE VSHLL and VMOVL Peter Maydell
2021-09-13 14:04   ` Richard Henderson
2021-09-13 14:22     ` Peter Maydell
2021-09-13 15:56       ` Richard Henderson
2021-09-13  9:54 ` [PATCH v2 11/12] target/arm: Optimize MVE VSLI and VSRI Peter Maydell
2021-09-13 14:04   ` Richard Henderson
2021-09-13  9:54 ` [PATCH v2 12/12] target/arm: Optimize MVE 1op-immediate insns Peter Maydell
2021-09-13 14:09   ` Richard Henderson

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