* [PATCH v2 0/7] treewide: Initial support for R-Car V4H
@ 2022-04-25 6:41 Yoshihiro Shimoda
2022-04-25 6:41 ` [PATCH v2 1/7] dt-bindings: power: Add r8a779g0 SYSC power domain definitions Yoshihiro Shimoda
` (6 more replies)
0 siblings, 7 replies; 17+ messages in thread
From: Yoshihiro Shimoda @ 2022-04-25 6:41 UTC (permalink / raw)
To: geert+renesas, magnus.damm, robh+dt, krzysztof.kozlowski+dt, gregkh
Cc: linux-renesas-soc, devicetree, linux-serial, Yoshihiro Shimoda
This patch series adds initial support for the Renesas R-Car V4H
(r8a779g0) SoC.
Changes from v1:
- Remove accepted patches from this series.
- Change the dt-binding files' license from (GPL-2.0 or MIT) to
(GPL-2.0-only OR BSD-2-Clause).
- Add some definitions in patch [2/7].
- Add "renesas,rcar-gen4-hscif" in a required property in patch [3/7].
- Modify r8a779a0-cpg-mssr.c in patch [4/7].
https://lore.kernel.org/all/20220420084255.375700-1-yoshihiro.shimoda.uh@renesas.com/
Yoshihiro Shimoda (7):
dt-bindings: power: Add r8a779g0 SYSC power domain definitions
dt-bindings: clock: Add r8a779g0 CPG Core Clock Definitions
dt-bindings: serial: renesas,hscif: Document r8a779g0 bindings
clk: renesas: rcar-gen4: Add CLK_TYPE_GEN4_PLL4
clk: renesas: cpg-mssr: Add support for R-Car V4H
arm64: dts: renesas: Add Renesas R8A779G0 SoC support
arm64: dts: renesas: Add Renesas White Hawk boards support
.../bindings/serial/renesas,hscif.yaml | 7 +
arch/arm64/boot/dts/renesas/Makefile | 2 +
.../dts/renesas/r8a779g0-white-hawk-cpu.dtsi | 45 ++++
.../boot/dts/renesas/r8a779g0-white-hawk.dts | 22 ++
arch/arm64/boot/dts/renesas/r8a779g0.dtsi | 122 ++++++++++
drivers/clk/renesas/Kconfig | 5 +
drivers/clk/renesas/Makefile | 1 +
drivers/clk/renesas/r8a779a0-cpg-mssr.c | 10 +-
drivers/clk/renesas/r8a779f0-cpg-mssr.c | 18 +-
drivers/clk/renesas/r8a779g0-cpg-mssr.c | 217 ++++++++++++++++++
drivers/clk/renesas/rcar-gen4-cpg.c | 5 +
drivers/clk/renesas/rcar-gen4-cpg.h | 3 +
drivers/clk/renesas/renesas-cpg-mssr.c | 6 +
drivers/clk/renesas/renesas-cpg-mssr.h | 1 +
include/dt-bindings/clock/r8a779g0-cpg-mssr.h | 90 ++++++++
include/dt-bindings/power/r8a779g0-sysc.h | 45 ++++
16 files changed, 585 insertions(+), 14 deletions(-)
create mode 100644 arch/arm64/boot/dts/renesas/r8a779g0-white-hawk-cpu.dtsi
create mode 100644 arch/arm64/boot/dts/renesas/r8a779g0-white-hawk.dts
create mode 100644 arch/arm64/boot/dts/renesas/r8a779g0.dtsi
create mode 100644 drivers/clk/renesas/r8a779g0-cpg-mssr.c
create mode 100644 include/dt-bindings/clock/r8a779g0-cpg-mssr.h
create mode 100644 include/dt-bindings/power/r8a779g0-sysc.h
--
2.25.1
^ permalink raw reply [flat|nested] 17+ messages in thread
* [PATCH v2 1/7] dt-bindings: power: Add r8a779g0 SYSC power domain definitions
2022-04-25 6:41 [PATCH v2 0/7] treewide: Initial support for R-Car V4H Yoshihiro Shimoda
@ 2022-04-25 6:41 ` Yoshihiro Shimoda
2022-04-25 6:41 ` [PATCH v2 2/7] dt-bindings: clock: Add r8a779g0 CPG Core Clock Definitions Yoshihiro Shimoda
` (5 subsequent siblings)
6 siblings, 0 replies; 17+ messages in thread
From: Yoshihiro Shimoda @ 2022-04-25 6:41 UTC (permalink / raw)
To: geert+renesas, magnus.damm, robh+dt, krzysztof.kozlowski+dt, gregkh
Cc: linux-renesas-soc, devicetree, linux-serial, Yoshihiro Shimoda,
Krzysztof Kozlowski
Add power domain indices for R-Car V4H (r8a779g0).
Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
---
include/dt-bindings/power/r8a779g0-sysc.h | 45 +++++++++++++++++++++++
1 file changed, 45 insertions(+)
create mode 100644 include/dt-bindings/power/r8a779g0-sysc.h
diff --git a/include/dt-bindings/power/r8a779g0-sysc.h b/include/dt-bindings/power/r8a779g0-sysc.h
new file mode 100644
index 000000000000..7daa70f1814e
--- /dev/null
+++ b/include/dt-bindings/power/r8a779g0-sysc.h
@@ -0,0 +1,45 @@
+/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
+/*
+ * Copyright (C) 2022 Renesas Electronics Corp.
+ */
+#ifndef __DT_BINDINGS_POWER_R8A779G0_SYSC_H__
+#define __DT_BINDINGS_POWER_R8A779G0_SYSC_H__
+
+/*
+ * These power domain indices match the Power Domain Register Numbers (PDR)
+ */
+
+#define R8A779G0_PD_A1E0D0C0 0
+#define R8A779G0_PD_A1E0D0C1 1
+#define R8A779G0_PD_A1E0D1C0 2
+#define R8A779G0_PD_A1E0D1C1 3
+#define R8A779G0_PD_A2E0D0 16
+#define R8A779G0_PD_A2E0D1 17
+#define R8A779G0_PD_A3E0 20
+#define R8A779G0_PD_A33DGA 24
+#define R8A779G0_PD_A23DGB 25
+#define R8A779G0_PD_A1DSP0 33
+#define R8A779G0_PD_A2IMP01 34
+#define R8A779G0_PD_A2PSC 35
+#define R8A779G0_PD_A2CV0 36
+#define R8A779G0_PD_A2CV1 37
+#define R8A779G0_PD_A1CNN0 41
+#define R8A779G0_PD_A2CN0 42
+#define R8A779G0_PD_A3IR 43
+#define R8A779G0_PD_A1DSP1 45
+#define R8A779G0_PD_A2IMP23 46
+#define R8A779G0_PD_A2DMA 47
+#define R8A779G0_PD_A2CV2 48
+#define R8A779G0_PD_A2CV3 49
+#define R8A779G0_PD_A1DSP2 53
+#define R8A779G0_PD_A1DSP3 54
+#define R8A779G0_PD_A3VIP0 56
+#define R8A779G0_PD_A3VIP1 57
+#define R8A779G0_PD_A3VIP2 58
+#define R8A779G0_PD_A3ISP0 60
+#define R8A779G0_PD_A3ISP1 61
+
+/* Always-on power area */
+#define R8A779G0_PD_ALWAYS_ON 64
+
+#endif /* __DT_BINDINGS_POWER_R8A779G0_SYSC_H__*/
--
2.25.1
^ permalink raw reply related [flat|nested] 17+ messages in thread
* [PATCH v2 2/7] dt-bindings: clock: Add r8a779g0 CPG Core Clock Definitions
2022-04-25 6:41 [PATCH v2 0/7] treewide: Initial support for R-Car V4H Yoshihiro Shimoda
2022-04-25 6:41 ` [PATCH v2 1/7] dt-bindings: power: Add r8a779g0 SYSC power domain definitions Yoshihiro Shimoda
@ 2022-04-25 6:41 ` Yoshihiro Shimoda
2022-04-25 8:26 ` Geert Uytterhoeven
2022-04-25 18:39 ` Krzysztof Kozlowski
2022-04-25 6:41 ` [PATCH v2 3/7] dt-bindings: serial: renesas,hscif: Document r8a779g0 bindings Yoshihiro Shimoda
` (4 subsequent siblings)
6 siblings, 2 replies; 17+ messages in thread
From: Yoshihiro Shimoda @ 2022-04-25 6:41 UTC (permalink / raw)
To: geert+renesas, magnus.damm, robh+dt, krzysztof.kozlowski+dt, gregkh
Cc: linux-renesas-soc, devicetree, linux-serial, Yoshihiro Shimoda
Add all Clock Pulse Generator Core Clock Outputs for the Renesas
R-Car V4H (R8A779G0) SoC.
Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
---
include/dt-bindings/clock/r8a779g0-cpg-mssr.h | 90 +++++++++++++++++++
1 file changed, 90 insertions(+)
create mode 100644 include/dt-bindings/clock/r8a779g0-cpg-mssr.h
diff --git a/include/dt-bindings/clock/r8a779g0-cpg-mssr.h b/include/dt-bindings/clock/r8a779g0-cpg-mssr.h
new file mode 100644
index 000000000000..754c54a6eb06
--- /dev/null
+++ b/include/dt-bindings/clock/r8a779g0-cpg-mssr.h
@@ -0,0 +1,90 @@
+/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
+/*
+ * Copyright (C) 2022 Renesas Electronics Corp.
+ */
+#ifndef __DT_BINDINGS_CLOCK_R8A779G0_CPG_MSSR_H__
+#define __DT_BINDINGS_CLOCK_R8A779G0_CPG_MSSR_H__
+
+#include <dt-bindings/clock/renesas-cpg-mssr.h>
+
+/* r8a779g0 CPG Core Clocks */
+
+#define R8A779G0_CLK_ZX 0
+#define R8A779G0_CLK_ZS 1
+#define R8A779G0_CLK_ZT 2
+#define R8A779G0_CLK_ZTR 3
+#define R8A779G0_CLK_S0D2 4
+#define R8A779G0_CLK_S0D3 5
+#define R8A779G0_CLK_S0D4 6
+#define R8A779G0_CLK_S0D1_VIO 7
+#define R8A779G0_CLK_S0D2_VIO 8
+#define R8A779G0_CLK_S0D4_VIO 9
+#define R8A779G0_CLK_S0D8_VIO 10
+#define R8A779G0_CLK_S0D1_VC 11
+#define R8A779G0_CLK_S0D2_VC 12
+#define R8A779G0_CLK_S0D4_VC 13
+#define R8A779G0_CLK_S0D2_MM 14
+#define R8A779G0_CLK_S0D4_MM 15
+#define R8A779G0_CLK_S0D2_U3DG 16
+#define R8A779G0_CLK_S0D4_U3DG 17
+#define R8A779G0_CLK_S0D2_RT 18
+#define R8A779G0_CLK_S0D3_RT 19
+#define R8A779G0_CLK_S0D4_RT 20
+#define R8A779G0_CLK_S0D6_RT 21
+#define R8A779G0_CLK_S0D24_RT 22
+#define R8A779G0_CLK_S0D2_PER 23
+#define R8A779G0_CLK_S0D3_PER 24
+#define R8A779G0_CLK_S0D4_PER 25
+#define R8A779G0_CLK_S0D6_PER 26
+#define R8A779G0_CLK_S0D12_PER 27
+#define R8A779G0_CLK_S0D24_PER 28
+#define R8A779G0_CLK_S0D1_HSC 29
+#define R8A779G0_CLK_S0D2_HSC 30
+#define R8A779G0_CLK_S0D4_HSC 31
+#define R8A779G0_CLK_S0D2_CC 32
+#define R8A779G0_CLK_SVD1_IR 33
+#define R8A779G0_CLK_SVD2_IR 34
+#define R8A779G0_CLK_SVD1_VIP 35
+#define R8A779G0_CLK_SVD2_VIP 36
+#define R8A779G0_CLK_CL 37
+#define R8A779G0_CLK_CL16M 38
+#define R8A779G0_CLK_CL16M_MM 39
+#define R8A779G0_CLK_CL16M_RT 40
+#define R8A779G0_CLK_CL16M_PER 41
+#define R8A779G0_CLK_CL16M_HSC 42
+#define R8A779G0_CLK_Z0 43
+#define R8A779G0_CLK_ZB3 44
+#define R8A779G0_CLK_ZB3D2 45
+#define R8A779G0_CLK_ZB3D4 46
+#define R8A779G0_CLK_ZG 47
+#define R8A779G0_CLK_SD0H 48
+#define R8A779G0_CLK_SD0 49
+#define R8A779G0_CLK_RPC 50
+#define R8A779G0_CLK_RPCD2 51
+#define R8A779G0_CLK_MSO 52
+#define R8A779G0_CLK_CANFD 53
+#define R8A779G0_CLK_CSI 54
+#define R8A779G0_CLK_FRAY 55
+#define R8A779G0_CLK_IPC 56
+#define R8A779G0_CLK_SASYNCRT 57
+#define R8A779G0_CLK_SASYNCPERD1 58
+#define R8A779G0_CLK_SASYNCPERD2 59
+#define R8A779G0_CLK_SASYNCPERD4 60
+#define R8A779G0_CLK_VIOBUS 61
+#define R8A779G0_CLK_VIOBUSD2 62
+#define R8A779G0_CLK_VCBUS 63
+#define R8A779G0_CLK_VCBUSD2 64
+#define R8A779G0_CLK_DSIEXT 65
+#define R8A779G0_CLK_DSIREF 66
+#define R8A779G0_CLK_ADGH 67
+#define R8A779G0_CLK_OSC 68
+#define R8A779G0_CLK_ZR0 69
+#define R8A779G0_CLK_ZR1 70
+#define R8A779G0_CLK_ZR2 71
+#define R8A779G0_CLK_IMPA 72
+#define R8A779G0_CLK_IMPAD4 73
+#define R8A779G0_CLK_CPEX 74
+#define R8A779G0_CLK_CBFUSA 75
+#define R8A779G0_CLK_R 76
+
+#endif /* __DT_BINDINGS_CLOCK_R8A779G0_CPG_MSSR_H__ */
--
2.25.1
^ permalink raw reply related [flat|nested] 17+ messages in thread
* [PATCH v2 3/7] dt-bindings: serial: renesas,hscif: Document r8a779g0 bindings
2022-04-25 6:41 [PATCH v2 0/7] treewide: Initial support for R-Car V4H Yoshihiro Shimoda
2022-04-25 6:41 ` [PATCH v2 1/7] dt-bindings: power: Add r8a779g0 SYSC power domain definitions Yoshihiro Shimoda
2022-04-25 6:41 ` [PATCH v2 2/7] dt-bindings: clock: Add r8a779g0 CPG Core Clock Definitions Yoshihiro Shimoda
@ 2022-04-25 6:41 ` Yoshihiro Shimoda
2022-04-25 8:13 ` Geert Uytterhoeven
2022-04-25 6:41 ` [PATCH v2 4/7] clk: renesas: rcar-gen4: Add CLK_TYPE_GEN4_PLL4 Yoshihiro Shimoda
` (3 subsequent siblings)
6 siblings, 1 reply; 17+ messages in thread
From: Yoshihiro Shimoda @ 2022-04-25 6:41 UTC (permalink / raw)
To: geert+renesas, magnus.damm, robh+dt, krzysztof.kozlowski+dt, gregkh
Cc: linux-renesas-soc, devicetree, linux-serial, Yoshihiro Shimoda,
Krzysztof Kozlowski
R-Car V4H (R8A779G0) SoC has the R-Car Gen4 compatible HSCIF ports,
so document the SoC specific bindings.
Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
---
.../devicetree/bindings/serial/renesas,hscif.yaml | 7 +++++++
1 file changed, 7 insertions(+)
diff --git a/Documentation/devicetree/bindings/serial/renesas,hscif.yaml b/Documentation/devicetree/bindings/serial/renesas,hscif.yaml
index ee9804cd49bb..d688a07a0e29 100644
--- a/Documentation/devicetree/bindings/serial/renesas,hscif.yaml
+++ b/Documentation/devicetree/bindings/serial/renesas,hscif.yaml
@@ -55,6 +55,12 @@ properties:
- const: renesas,rcar-gen3-hscif # R-Car Gen3 and RZ/G2
- const: renesas,hscif # generic HSCIF compatible UART
+ - items:
+ - enum:
+ - renesas,hscif-r8a779g0 # R-Car V4H
+ - const: renesas,rcar-gen4-hscif # R-Car Gen4
+ - const: renesas,hscif # generic HSCIF compatible UART
+
reg:
maxItems: 1
@@ -113,6 +119,7 @@ if:
enum:
- renesas,rcar-gen2-hscif
- renesas,rcar-gen3-hscif
+ - renesas,rcar-gen4-hscif
then:
required:
- resets
--
2.25.1
^ permalink raw reply related [flat|nested] 17+ messages in thread
* [PATCH v2 4/7] clk: renesas: rcar-gen4: Add CLK_TYPE_GEN4_PLL4
2022-04-25 6:41 [PATCH v2 0/7] treewide: Initial support for R-Car V4H Yoshihiro Shimoda
` (2 preceding siblings ...)
2022-04-25 6:41 ` [PATCH v2 3/7] dt-bindings: serial: renesas,hscif: Document r8a779g0 bindings Yoshihiro Shimoda
@ 2022-04-25 6:41 ` Yoshihiro Shimoda
2022-04-25 14:48 ` Geert Uytterhoeven
2022-04-25 6:41 ` [PATCH v2 5/7] clk: renesas: cpg-mssr: Add support for R-Car V4H Yoshihiro Shimoda
` (2 subsequent siblings)
6 siblings, 1 reply; 17+ messages in thread
From: Yoshihiro Shimoda @ 2022-04-25 6:41 UTC (permalink / raw)
To: geert+renesas, magnus.damm, robh+dt, krzysztof.kozlowski+dt, gregkh
Cc: linux-renesas-soc, devicetree, linux-serial, Yoshihiro Shimoda
R-Car V4H (r8a779g0) has PLL4 so that add CLK_TYPE_GEN4_PLL4.
Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
---
drivers/clk/renesas/r8a779a0-cpg-mssr.c | 10 +++++-----
drivers/clk/renesas/r8a779f0-cpg-mssr.c | 18 +++++++++---------
drivers/clk/renesas/rcar-gen4-cpg.c | 5 +++++
drivers/clk/renesas/rcar-gen4-cpg.h | 3 +++
4 files changed, 22 insertions(+), 14 deletions(-)
diff --git a/drivers/clk/renesas/r8a779a0-cpg-mssr.c b/drivers/clk/renesas/r8a779a0-cpg-mssr.c
index fb84f7b51f61..a603b255af2e 100644
--- a/drivers/clk/renesas/r8a779a0-cpg-mssr.c
+++ b/drivers/clk/renesas/r8a779a0-cpg-mssr.c
@@ -253,11 +253,11 @@ static const unsigned int r8a779a0_crit_mod_clks[] __initconst = {
#define CPG_PLL_CONFIG_INDEX(md) ((((md) & BIT(14)) >> 13) | \
(((md) & BIT(13)) >> 13))
static const struct rcar_gen4_cpg_pll_config cpg_pll_configs[4] = {
- /* EXTAL div PLL1 mult/div PLL2 mult/div PLL3 mult/div PLL5 mult/div PLL6 mult/div OSC prediv */
- { 1, 128, 1, 0, 0, 0, 0, 192, 1, 0, 0, 16, },
- { 1, 106, 1, 0, 0, 0, 0, 160, 1, 0, 0, 19, },
- { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, },
- { 2, 128, 1, 0, 0, 0, 0, 192, 1, 0, 0, 32, },
+ /* EXTAL div PLL1 mult/div PLL2 mult/div PLL3 mult/div PLL4 mult/div PLL5 mult/div PLL6 mult/div OSC prediv */
+ { 1, 128, 1, 0, 0, 0, 0, 144, 1, 192, 1, 0, 0, 16, },
+ { 1, 106, 1, 0, 0, 0, 0, 120, 1, 160, 1, 0, 0, 19, },
+ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, },
+ { 2, 128, 1, 0, 0, 0, 0, 128, 1, 192, 1, 0, 0, 32, },
};
diff --git a/drivers/clk/renesas/r8a779f0-cpg-mssr.c b/drivers/clk/renesas/r8a779f0-cpg-mssr.c
index 08e8d95ce5e7..be9dcc00d3ab 100644
--- a/drivers/clk/renesas/r8a779f0-cpg-mssr.c
+++ b/drivers/clk/renesas/r8a779f0-cpg-mssr.c
@@ -142,23 +142,23 @@ static const unsigned int r8a779f0_crit_mod_clks[] __initconst = {
* CPG Clock Data
*/
/*
- * MD EXTAL PLL1 PLL2 PLL3 PLL5 PLL6 OSC
+ * MD EXTAL PLL1 PLL2 PLL3 PLL4 PLL5 PLL6 OSC
* 14 13 (MHz)
* ----------------------------------------------------------------
- * 0 0 16 / 1 x200 x150 x200 x200 x134 /15
- * 0 1 20 / 1 x160 x120 x160 x160 x106 /19
+ * 0 0 16 / 1 x200 x150 x200 n/a x200 x134 /15
+ * 0 1 20 / 1 x160 x120 x160 n/a x160 x106 /19
* 1 0 Prohibited setting
- * 1 1 40 / 2 x160 x120 x160 x160 x106 /38
+ * 1 1 40 / 2 x160 x120 x160 n/a x160 x106 /38
*/
#define CPG_PLL_CONFIG_INDEX(md) ((((md) & BIT(14)) >> 13) | \
(((md) & BIT(13)) >> 13))
static const struct rcar_gen4_cpg_pll_config cpg_pll_configs[4] = {
- /* EXTAL div PLL1 mult/div PLL2 mult/div PLL3 mult/div PLL5 mult/div PLL6 mult/div OSC prediv */
- { 1, 200, 1, 150, 1, 200, 1, 200, 1, 134, 1, 15, },
- { 1, 160, 1, 120, 1, 160, 1, 160, 1, 106, 1, 19, },
- { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, },
- { 2, 160, 1, 120, 1, 160, 1, 160, 1, 106, 1, 38, },
+ /* EXTAL div PLL1 mult/div PLL2 mult/div PLL3 mult/div PLL4 mult/div PLL5 mult/div PLL6 mult/div OSC prediv */
+ { 1, 200, 1, 150, 1, 200, 1, 0, 0, 200, 1, 134, 1, 15, },
+ { 1, 160, 1, 120, 1, 160, 1, 0, 0, 160, 1, 106, 1, 19, },
+ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, },
+ { 2, 160, 1, 120, 1, 160, 1, 0, 0, 160, 1, 106, 1, 38, },
};
static int __init r8a779f0_cpg_mssr_init(struct device *dev)
diff --git a/drivers/clk/renesas/rcar-gen4-cpg.c b/drivers/clk/renesas/rcar-gen4-cpg.c
index 54ebf4b3c128..c7ed43d6aa67 100644
--- a/drivers/clk/renesas/rcar-gen4-cpg.c
+++ b/drivers/clk/renesas/rcar-gen4-cpg.c
@@ -215,6 +215,11 @@ struct clk * __init rcar_gen4_cpg_clk_register(struct device *dev,
div = cpg_pll_config->pll3_div;
break;
+ case CLK_TYPE_GEN4_PLL4:
+ mult = cpg_pll_config->pll4_mult;
+ div = cpg_pll_config->pll4_div;
+ break;
+
case CLK_TYPE_GEN4_PLL5:
mult = cpg_pll_config->pll5_mult;
div = cpg_pll_config->pll5_div;
diff --git a/drivers/clk/renesas/rcar-gen4-cpg.h b/drivers/clk/renesas/rcar-gen4-cpg.h
index afc8c024d538..0b15dcfdca7b 100644
--- a/drivers/clk/renesas/rcar-gen4-cpg.h
+++ b/drivers/clk/renesas/rcar-gen4-cpg.h
@@ -16,6 +16,7 @@ enum rcar_gen4_clk_types {
CLK_TYPE_GEN4_PLL2X_3X, /* r8a779a0 only */
CLK_TYPE_GEN4_PLL3,
CLK_TYPE_GEN4_PLL5,
+ CLK_TYPE_GEN4_PLL4,
CLK_TYPE_GEN4_PLL6,
CLK_TYPE_GEN4_SDSRC,
CLK_TYPE_GEN4_SDH,
@@ -56,6 +57,8 @@ struct rcar_gen4_cpg_pll_config {
u8 pll2_div;
u8 pll3_mult;
u8 pll3_div;
+ u8 pll4_mult;
+ u8 pll4_div;
u8 pll5_mult;
u8 pll5_div;
u8 pll6_mult;
--
2.25.1
^ permalink raw reply related [flat|nested] 17+ messages in thread
* [PATCH v2 5/7] clk: renesas: cpg-mssr: Add support for R-Car V4H
2022-04-25 6:41 [PATCH v2 0/7] treewide: Initial support for R-Car V4H Yoshihiro Shimoda
` (3 preceding siblings ...)
2022-04-25 6:41 ` [PATCH v2 4/7] clk: renesas: rcar-gen4: Add CLK_TYPE_GEN4_PLL4 Yoshihiro Shimoda
@ 2022-04-25 6:41 ` Yoshihiro Shimoda
2022-04-27 14:26 ` Geert Uytterhoeven
2022-04-25 6:42 ` [PATCH v2 6/7] arm64: dts: renesas: Add Renesas R8A779G0 SoC support Yoshihiro Shimoda
2022-04-25 6:42 ` [PATCH v2 7/7] arm64: dts: renesas: Add Renesas White Hawk boards support Yoshihiro Shimoda
6 siblings, 1 reply; 17+ messages in thread
From: Yoshihiro Shimoda @ 2022-04-25 6:41 UTC (permalink / raw)
To: geert+renesas, magnus.damm, robh+dt, krzysztof.kozlowski+dt, gregkh
Cc: linux-renesas-soc, devicetree, linux-serial, Yoshihiro Shimoda
Initial CPG support for R-Car V4H (r8a779g0).
Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
---
drivers/clk/renesas/Kconfig | 5 +
drivers/clk/renesas/Makefile | 1 +
drivers/clk/renesas/r8a779g0-cpg-mssr.c | 217 ++++++++++++++++++++++++
drivers/clk/renesas/renesas-cpg-mssr.c | 6 +
drivers/clk/renesas/renesas-cpg-mssr.h | 1 +
5 files changed, 230 insertions(+)
create mode 100644 drivers/clk/renesas/r8a779g0-cpg-mssr.c
diff --git a/drivers/clk/renesas/Kconfig b/drivers/clk/renesas/Kconfig
index a95ed8f310da..7e9b9a5bb5b7 100644
--- a/drivers/clk/renesas/Kconfig
+++ b/drivers/clk/renesas/Kconfig
@@ -32,6 +32,7 @@ config CLK_RENESAS
select CLK_R8A77995 if ARCH_R8A77995
select CLK_R8A779A0 if ARCH_R8A779A0
select CLK_R8A779F0 if ARCH_R8A779F0
+ select CLK_R8A779G0 if ARCH_R8A779G0
select CLK_R9A06G032 if ARCH_R9A06G032
select CLK_R9A07G043 if ARCH_R9A07G043
select CLK_R9A07G044 if ARCH_R9A07G044
@@ -158,6 +159,10 @@ config CLK_R8A779F0
bool "R-Car S4-8 clock support" if COMPILE_TEST
select CLK_RCAR_GEN4_CPG
+config CLK_R8A779G0
+ bool "R-Car V4H clock support" if COMPILE_TEST
+ select CLK_RCAR_GEN4_CPG
+
config CLK_R9A06G032
bool "RZ/N1D clock support" if COMPILE_TEST
diff --git a/drivers/clk/renesas/Makefile b/drivers/clk/renesas/Makefile
index ca3a9bbcf27a..b83062af090c 100644
--- a/drivers/clk/renesas/Makefile
+++ b/drivers/clk/renesas/Makefile
@@ -29,6 +29,7 @@ obj-$(CONFIG_CLK_R8A77990) += r8a77990-cpg-mssr.o
obj-$(CONFIG_CLK_R8A77995) += r8a77995-cpg-mssr.o
obj-$(CONFIG_CLK_R8A779A0) += r8a779a0-cpg-mssr.o
obj-$(CONFIG_CLK_R8A779F0) += r8a779f0-cpg-mssr.o
+obj-$(CONFIG_CLK_R8A779G0) += r8a779g0-cpg-mssr.o
obj-$(CONFIG_CLK_R9A06G032) += r9a06g032-clocks.o
obj-$(CONFIG_CLK_R9A07G043) += r9a07g043-cpg.o
obj-$(CONFIG_CLK_R9A07G044) += r9a07g044-cpg.o
diff --git a/drivers/clk/renesas/r8a779g0-cpg-mssr.c b/drivers/clk/renesas/r8a779g0-cpg-mssr.c
new file mode 100644
index 000000000000..c5f40b6a6af9
--- /dev/null
+++ b/drivers/clk/renesas/r8a779g0-cpg-mssr.c
@@ -0,0 +1,217 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * r8a779g0 Clock Pulse Generator / Module Standby and Software Reset
+ *
+ * Copyright (C) 2022 Renesas Electronics Corp.
+ *
+ * Based on r8a779g0-cpg-mssr.c
+ */
+
+#include <linux/bitfield.h>
+#include <linux/clk.h>
+#include <linux/clk-provider.h>
+#include <linux/device.h>
+#include <linux/err.h>
+#include <linux/kernel.h>
+#include <linux/soc/renesas/rcar-rst.h>
+
+#include <dt-bindings/clock/r8a779g0-cpg-mssr.h>
+
+#include "renesas-cpg-mssr.h"
+#include "rcar-gen4-cpg.h"
+
+enum clk_ids {
+ /* Core Clock Outputs exported to DT */
+ LAST_DT_CORE_CLK = R8A779G0_CLK_R,
+
+ /* External Input Clocks */
+ CLK_EXTAL,
+ CLK_EXTALR,
+
+ /* Internal Core Clocks */
+ CLK_MAIN,
+ CLK_PLL1,
+ CLK_PLL2,
+ CLK_PLL3,
+ CLK_PLL4,
+ CLK_PLL5,
+ CLK_PLL6,
+ CLK_PLL1_DIV2,
+ CLK_PLL2_DIV2,
+ CLK_PLL3_DIV2,
+ CLK_PLL4_DIV2,
+ CLK_PLL5_DIV2,
+ CLK_PLL5_DIV4,
+ CLK_PLL6_DIV2,
+ CLK_S0,
+ CLK_S0_VIO,
+ CLK_S0_VC,
+ CLK_S0_HSC,
+ CLK_SV_VIP,
+ CLK_SV_IR,
+ CLK_SDSRC,
+ CLK_RPCSRC,
+ CLK_VIO,
+ CLK_VC,
+ CLK_OCO,
+
+ /* Module Clocks */
+ MOD_CLK_BASE
+};
+
+static const struct cpg_core_clk r8a779g0_core_clks[] __initconst = {
+ /* External Clock Inputs */
+ DEF_INPUT("extal", CLK_EXTAL),
+ DEF_INPUT("extalr", CLK_EXTALR),
+
+ /* Internal Core Clocks */
+ DEF_BASE(".main", CLK_MAIN, CLK_TYPE_GEN4_MAIN, CLK_EXTAL),
+ DEF_BASE(".pll1", CLK_PLL1, CLK_TYPE_GEN4_PLL1, CLK_MAIN),
+ DEF_BASE(".pll2", CLK_PLL2, CLK_TYPE_GEN4_PLL2, CLK_MAIN),
+ DEF_BASE(".pll3", CLK_PLL3, CLK_TYPE_GEN4_PLL3, CLK_MAIN),
+ DEF_BASE(".pll4", CLK_PLL4, CLK_TYPE_GEN4_PLL4, CLK_MAIN),
+ DEF_BASE(".pll5", CLK_PLL5, CLK_TYPE_GEN4_PLL5, CLK_MAIN),
+ DEF_BASE(".pll6", CLK_PLL6, CLK_TYPE_GEN4_PLL6, CLK_MAIN),
+
+ DEF_FIXED(".pll1_div2", CLK_PLL1_DIV2, CLK_PLL1, 2, 1),
+ DEF_FIXED(".pll2_div2", CLK_PLL2_DIV2, CLK_PLL2, 2, 1),
+ DEF_FIXED(".pll3_div2", CLK_PLL3_DIV2, CLK_PLL3, 2, 1),
+ DEF_FIXED(".pll4_div2", CLK_PLL4_DIV2, CLK_PLL4, 2, 1),
+ DEF_FIXED(".pll5_div2", CLK_PLL5_DIV2, CLK_PLL5, 2, 1),
+ DEF_FIXED(".pll5_div4", CLK_PLL5_DIV4, CLK_PLL5_DIV2, 2, 1),
+ DEF_FIXED(".pll6_div2", CLK_PLL6_DIV2, CLK_PLL6, 2, 1),
+ DEF_FIXED(".s0", CLK_S0, CLK_PLL1_DIV2, 2, 1),
+ DEF_FIXED(".s0_vio", CLK_S0_VIO, CLK_PLL1_DIV2, 2, 1),
+ DEF_FIXED(".s0_vc", CLK_S0_VC, CLK_PLL1_DIV2, 2, 1),
+ DEF_FIXED(".s0_hsc", CLK_S0_HSC, CLK_PLL1_DIV2, 2, 1),
+ DEF_FIXED(".sv_vip", CLK_SV_VIP, CLK_PLL1_DIV2, 2, 1),
+ DEF_FIXED(".sv_ir", CLK_SV_IR, CLK_PLL1_DIV2, 2, 1),
+ DEF_BASE(".sdsrc", CLK_SDSRC, CLK_TYPE_GEN4_SDSRC, CLK_PLL5),
+ DEF_RATE(".oco", CLK_OCO, 32768),
+
+ DEF_BASE(".rpcsrc", CLK_RPCSRC, CLK_TYPE_GEN4_RPCSRC, CLK_PLL5),
+ DEF_BASE(".rpc", R8A779G0_CLK_RPC, CLK_TYPE_GEN4_RPC, CLK_RPCSRC),
+ DEF_BASE("rpcd2", R8A779G0_CLK_RPCD2, CLK_TYPE_GEN4_RPCD2, R8A779G0_CLK_RPC),
+ DEF_FIXED(".vio", CLK_VIO, CLK_PLL5_DIV2, 3, 1),
+ DEF_FIXED(".vc", CLK_VC, CLK_PLL5_DIV2, 3, 1),
+
+ /* Core Clock Outputs */
+ DEF_FIXED("s0d2", R8A779G0_CLK_S0D2, CLK_S0, 2, 1),
+ DEF_FIXED("s0d3", R8A779G0_CLK_S0D3, CLK_S0, 3, 1),
+ DEF_FIXED("s0d4", R8A779G0_CLK_S0D4, CLK_S0, 4, 1),
+ DEF_FIXED("cl16m", R8A779G0_CLK_CL16M, CLK_S0, 48, 1),
+ DEF_FIXED("s0d1_vio", R8A779G0_CLK_S0D1_VIO, CLK_S0_VIO, 1, 1),
+ DEF_FIXED("s0d2_vio", R8A779G0_CLK_S0D2_VIO, CLK_S0_VIO, 2, 1),
+ DEF_FIXED("s0d4_vio", R8A779G0_CLK_S0D4_VIO, CLK_S0_VIO, 4, 1),
+ DEF_FIXED("s0d8_vio", R8A779G0_CLK_S0D8_VIO, CLK_S0_VIO, 8, 1),
+ DEF_FIXED("s0d1_vc", R8A779G0_CLK_S0D1_VC, CLK_S0_VC, 1, 1),
+ DEF_FIXED("s0d2_vc", R8A779G0_CLK_S0D2_VC, CLK_S0_VC, 2, 1),
+ DEF_FIXED("s0d4_vc", R8A779G0_CLK_S0D4_VC, CLK_S0_VC, 4, 1),
+ DEF_FIXED("s0d2_mm", R8A779G0_CLK_S0D2_MM, CLK_S0, 2, 1),
+ DEF_FIXED("s0d4_mm", R8A779G0_CLK_S0D4_MM, CLK_S0, 4, 1),
+ DEF_FIXED("cl16m_mm", R8A779G0_CLK_CL16M_MM, CLK_S0, 48, 1),
+ DEF_FIXED("s0d2_u3dg", R8A779G0_CLK_S0D2_U3DG, CLK_S0, 2, 1),
+ DEF_FIXED("s0d4_u3dg", R8A779G0_CLK_S0D4_U3DG, CLK_S0, 4, 1),
+ DEF_FIXED("s0d2_rt", R8A779G0_CLK_S0D2_RT, CLK_S0, 2, 1),
+ DEF_FIXED("s0d3_rt", R8A779G0_CLK_S0D3_RT, CLK_S0, 3, 1),
+ DEF_FIXED("s0d4_rt", R8A779G0_CLK_S0D4_RT, CLK_S0, 4, 1),
+ DEF_FIXED("s0d6_rt", R8A779G0_CLK_S0D6_RT, CLK_S0, 6, 1),
+ DEF_FIXED("s0d24_rt", R8A779G0_CLK_S0D24_RT, CLK_S0, 24, 1),
+ DEF_FIXED("cl16m_rt", R8A779G0_CLK_CL16M_RT, CLK_S0, 48, 1),
+ DEF_FIXED("s0d2_per", R8A779G0_CLK_S0D2_PER, CLK_S0, 2, 1),
+ DEF_FIXED("s0d3_per", R8A779G0_CLK_S0D3_PER, CLK_S0, 3, 1),
+ DEF_FIXED("s0d6_per", R8A779G0_CLK_S0D6_PER, CLK_S0, 6, 1),
+ DEF_FIXED("s0d12_per", R8A779G0_CLK_S0D12_PER, CLK_S0, 12, 1),
+ DEF_FIXED("s0d24_per", R8A779G0_CLK_S0D24_PER, CLK_S0, 24, 1),
+ DEF_FIXED("cl16m_per", R8A779G0_CLK_CL16M_PER, CLK_S0, 48, 1),
+ DEF_FIXED("s0d1_hsc", R8A779G0_CLK_S0D1_HSC, CLK_S0_HSC, 1, 1),
+ DEF_FIXED("s0d2_hsc", R8A779G0_CLK_S0D2_HSC, CLK_S0_HSC, 2, 1),
+ DEF_FIXED("s0d4_hsc", R8A779G0_CLK_S0D4_HSC, CLK_S0_HSC, 4, 1),
+ DEF_FIXED("cl16m_hsc", R8A779G0_CLK_CL16M_HSC, CLK_S0_HSC, 48, 1),
+ DEF_FIXED("s0d2_cc", R8A779G0_CLK_S0D2_CC, CLK_S0, 2, 1),
+ DEF_FIXED("svd1_ir", R8A779G0_CLK_SVD1_IR, CLK_SV_IR, 1, 1),
+ DEF_FIXED("svd2_ir", R8A779G0_CLK_SVD2_IR, CLK_SV_IR, 2, 1),
+ DEF_FIXED("svd1_vip", R8A779G0_CLK_SVD1_VIP, CLK_SV_VIP, 1, 1),
+ DEF_FIXED("svd2_vip", R8A779G0_CLK_SVD2_VIP, CLK_SV_VIP, 2, 1),
+ DEF_FIXED("s0d2_cc", R8A779G0_CLK_S0D2_CC, CLK_S0, 2, 1),
+ DEF_FIXED("cbfusa", R8A779G0_CLK_CBFUSA, CLK_EXTAL, 2, 1),
+ DEF_FIXED("cpex", R8A779G0_CLK_CPEX, CLK_EXTAL, 2, 1),
+ DEF_FIXED("viobus", R8A779G0_CLK_VIOBUS, CLK_VIO, 1, 1),
+ DEF_FIXED("viobusd2", R8A779G0_CLK_VIOBUSD2, CLK_VIO, 2, 1),
+ DEF_FIXED("vcbus", R8A779G0_CLK_VCBUS, CLK_VC, 1, 1),
+ DEF_FIXED("vcbusd2", R8A779G0_CLK_VCBUSD2, CLK_VC, 2, 1),
+
+ DEF_GEN4_SD("sd0", R8A779G0_CLK_SD0, CLK_SDSRC, 0x870),
+ DEF_DIV6P1("mso", R8A779G0_CLK_MSO, CLK_PLL5_DIV4, 0x87c),
+
+ DEF_GEN4_OSC("osc", R8A779G0_CLK_OSC, CLK_EXTAL, 8),
+ DEF_GEN4_MDSEL("r", R8A779G0_CLK_R, 29, CLK_EXTALR, 1, CLK_OCO, 1),
+};
+
+static const struct mssr_mod_clk r8a779g0_mod_clks[] __initconst = {
+ DEF_MOD("hscif0", 514, R8A779G0_CLK_S0D3_PER),
+ DEF_MOD("hscif1", 515, R8A779G0_CLK_S0D3_PER),
+ DEF_MOD("hscif2", 516, R8A779G0_CLK_S0D3_PER),
+ DEF_MOD("hscif3", 517, R8A779G0_CLK_S0D3_PER),
+};
+
+/*
+ * CPG Clock Data
+ */
+/*
+ * MD EXTAL PLL1 PLL2 PLL3 PLL4 PLL5 PLL6 OSC
+ * 14 13 (MHz)
+ * ----------------------------------------------------------------
+ * 0 0 16.66 / 1 x192 x204 x192 x144 x192 x168 /8
+ * 0 1 20 / 1 x160 x170 x160 x120 x160 x140 /8
+ * 1 0 Prohibited setting
+ * 1 1 33.33 / 2 x192 x204 x192 x144 x192 x168 /8
+ */
+#define CPG_PLL_CONFIG_INDEX(md) ((((md) & BIT(14)) >> 13) | \
+ (((md) & BIT(13)) >> 13))
+
+static const struct rcar_gen4_cpg_pll_config cpg_pll_configs[4] = {
+ /* EXTAL div PLL1 mult/div PLL2 mult/div PLL3 mult/div PLL4 mult/div PLL5 mult/div PLL6 mult/div OSC prediv */
+ { 1, 192, 1, 204, 1, 192, 1, 144, 1, 192, 1, 168, 1, 8, },
+ { 1, 160, 1, 170, 1, 160, 1, 120, 1, 160, 1, 140, 1, 8, },
+ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, },
+ { 2, 192, 1, 204, 1, 192, 1, 144, 1, 192, 1, 168, 1, 8, },
+};
+
+static int __init r8a779g0_cpg_mssr_init(struct device *dev)
+{
+ const struct rcar_gen4_cpg_pll_config *cpg_pll_config;
+ u32 cpg_mode;
+ int error;
+
+ error = rcar_rst_read_mode_pins(&cpg_mode);
+ if (error)
+ return error;
+
+ cpg_pll_config = &cpg_pll_configs[CPG_PLL_CONFIG_INDEX(cpg_mode)];
+ if (!cpg_pll_config->extal_div) {
+ dev_err(dev, "Prohibited setting (cpg_mode=0x%x)\n", cpg_mode);
+ return -EINVAL;
+ }
+
+ return rcar_gen4_cpg_init(cpg_pll_config, CLK_EXTALR, cpg_mode);
+}
+
+const struct cpg_mssr_info r8a779g0_cpg_mssr_info __initconst = {
+ /* Core Clocks */
+ .core_clks = r8a779g0_core_clks,
+ .num_core_clks = ARRAY_SIZE(r8a779g0_core_clks),
+ .last_dt_core_clk = LAST_DT_CORE_CLK,
+ .num_total_core_clks = MOD_CLK_BASE,
+
+ /* Module Clocks */
+ .mod_clks = r8a779g0_mod_clks,
+ .num_mod_clks = ARRAY_SIZE(r8a779g0_mod_clks),
+ .num_hw_mod_clks = 30 * 32,
+
+ /* Callbacks */
+ .init = r8a779g0_cpg_mssr_init,
+ .cpg_clk_register = rcar_gen4_cpg_clk_register,
+
+ .reg_layout = CLK_REG_LAYOUT_RCAR_GEN4,
+};
diff --git a/drivers/clk/renesas/renesas-cpg-mssr.c b/drivers/clk/renesas/renesas-cpg-mssr.c
index 5d2c3edbaa14..1a0cdf001b2f 100644
--- a/drivers/clk/renesas/renesas-cpg-mssr.c
+++ b/drivers/clk/renesas/renesas-cpg-mssr.c
@@ -853,6 +853,12 @@ static const struct of_device_id cpg_mssr_match[] = {
.compatible = "renesas,r8a779f0-cpg-mssr",
.data = &r8a779f0_cpg_mssr_info,
},
+#endif
+#ifdef CONFIG_CLK_R8A779G0
+ {
+ .compatible = "renesas,r8a779g0-cpg-mssr",
+ .data = &r8a779g0_cpg_mssr_info,
+ },
#endif
{ /* sentinel */ }
};
diff --git a/drivers/clk/renesas/renesas-cpg-mssr.h b/drivers/clk/renesas/renesas-cpg-mssr.h
index 16810dd4e6ac..1c3c057d17f5 100644
--- a/drivers/clk/renesas/renesas-cpg-mssr.h
+++ b/drivers/clk/renesas/renesas-cpg-mssr.h
@@ -179,6 +179,7 @@ extern const struct cpg_mssr_info r8a77990_cpg_mssr_info;
extern const struct cpg_mssr_info r8a77995_cpg_mssr_info;
extern const struct cpg_mssr_info r8a779a0_cpg_mssr_info;
extern const struct cpg_mssr_info r8a779f0_cpg_mssr_info;
+extern const struct cpg_mssr_info r8a779g0_cpg_mssr_info;
void __init cpg_mssr_early_init(struct device_node *np,
const struct cpg_mssr_info *info);
--
2.25.1
^ permalink raw reply related [flat|nested] 17+ messages in thread
* [PATCH v2 6/7] arm64: dts: renesas: Add Renesas R8A779G0 SoC support
2022-04-25 6:41 [PATCH v2 0/7] treewide: Initial support for R-Car V4H Yoshihiro Shimoda
` (4 preceding siblings ...)
2022-04-25 6:41 ` [PATCH v2 5/7] clk: renesas: cpg-mssr: Add support for R-Car V4H Yoshihiro Shimoda
@ 2022-04-25 6:42 ` Yoshihiro Shimoda
2022-04-27 14:37 ` Geert Uytterhoeven
2022-04-25 6:42 ` [PATCH v2 7/7] arm64: dts: renesas: Add Renesas White Hawk boards support Yoshihiro Shimoda
6 siblings, 1 reply; 17+ messages in thread
From: Yoshihiro Shimoda @ 2022-04-25 6:42 UTC (permalink / raw)
To: geert+renesas, magnus.damm, robh+dt, krzysztof.kozlowski+dt, gregkh
Cc: linux-renesas-soc, devicetree, linux-serial, Yoshihiro Shimoda
Add initial support for the Renesas R8A779G0 (R-Car V4H) SoC.
Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
---
arch/arm64/boot/dts/renesas/r8a779g0.dtsi | 122 ++++++++++++++++++++++
1 file changed, 122 insertions(+)
create mode 100644 arch/arm64/boot/dts/renesas/r8a779g0.dtsi
diff --git a/arch/arm64/boot/dts/renesas/r8a779g0.dtsi b/arch/arm64/boot/dts/renesas/r8a779g0.dtsi
new file mode 100644
index 000000000000..aba3d00f02dd
--- /dev/null
+++ b/arch/arm64/boot/dts/renesas/r8a779g0.dtsi
@@ -0,0 +1,122 @@
+// SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause)
+/*
+ * Device Tree Source for the R-Car V4H (R8A779G0) SoC
+ *
+ * Copyright (C) 2022 Renesas Electronics Corp.
+ */
+
+#include <dt-bindings/clock/r8a779g0-cpg-mssr.h>
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/power/r8a779g0-sysc.h>
+
+/ {
+ compatible = "renesas,r8a779g0";
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ a76_0: cpu@0 {
+ compatible = "arm,cortex-a76";
+ reg = <0>;
+ device_type = "cpu";
+ power-domains = <&sysc R8A779G0_PD_A1E0D0C0>;
+ };
+ };
+
+ extal_clk: extal {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ /* This value must be overridden by the board */
+ clock-frequency = <0>;
+ };
+
+ extalr_clk: extalr {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ /* This value must be overridden by the board */
+ clock-frequency = <0>;
+ };
+
+ pmu_a76 {
+ compatible = "arm,cortex-a76-pmu";
+ interrupts-extended = <&gic GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>;
+ };
+
+ /* External SCIF clock - to be overridden by boards that provide it */
+ scif_clk: scif {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <0>;
+ };
+
+ soc: soc {
+ compatible = "simple-bus";
+ interrupt-parent = <&gic>;
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ cpg: clock-controller@e6150000 {
+ compatible = "renesas,r8a779g0-cpg-mssr";
+ reg = <0 0xe6150000 0 0x4000>;
+ clocks = <&extal_clk>, <&extalr_clk>;
+ clock-names = "extal", "extalr";
+ #clock-cells = <2>;
+ #power-domain-cells = <0>;
+ #reset-cells = <1>;
+ };
+
+ rst: reset-controller@e6160000 {
+ compatible = "renesas,r8a779g0-rst";
+ reg = <0 0xe6160000 0 0x4000>;
+ };
+
+ sysc: system-controller@e6180000 {
+ compatible = "renesas,r8a779g0-sysc";
+ reg = <0 0xe6180000 0 0x4000>;
+ #power-domain-cells = <1>;
+ };
+
+ hscif0: serial@e6540000 {
+ compatible = "renesas,hscif-r8a779g0",
+ "renesas,rcar-gen4-hscif",
+ "renesas,hscif";
+ reg = <0 0xe6540000 0 96>;
+ interrupts = <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 514>,
+ <&cpg CPG_CORE R8A779G0_CLK_S0D3_PER>,
+ <&scif_clk>;
+ clock-names = "fck", "brg_int", "scif_clk";
+ power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>;
+ resets = <&cpg 514>;
+ status = "disabled";
+ };
+
+ gic: interrupt-controller@f1000000 {
+ compatible = "arm,gic-v3";
+ #interrupt-cells = <3>;
+ #address-cells = <0>;
+ interrupt-controller;
+ reg = <0x0 0xf1000000 0 0x20000>,
+ <0x0 0xf1060000 0 0x110000>;
+ interrupts = <GIC_PPI 9
+ (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_HIGH)>;
+ };
+
+ prr: chipid@fff00044 {
+ compatible = "renesas,prr";
+ reg = <0 0xfff00044 0 4>;
+ };
+ };
+
+ timer {
+ compatible = "arm,armv8-timer";
+ interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
+ <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
+ <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
+ <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>;
+ };
+};
--
2.25.1
^ permalink raw reply related [flat|nested] 17+ messages in thread
* [PATCH v2 7/7] arm64: dts: renesas: Add Renesas White Hawk boards support
2022-04-25 6:41 [PATCH v2 0/7] treewide: Initial support for R-Car V4H Yoshihiro Shimoda
` (5 preceding siblings ...)
2022-04-25 6:42 ` [PATCH v2 6/7] arm64: dts: renesas: Add Renesas R8A779G0 SoC support Yoshihiro Shimoda
@ 2022-04-25 6:42 ` Yoshihiro Shimoda
2022-04-27 14:52 ` Geert Uytterhoeven
6 siblings, 1 reply; 17+ messages in thread
From: Yoshihiro Shimoda @ 2022-04-25 6:42 UTC (permalink / raw)
To: geert+renesas, magnus.damm, robh+dt, krzysztof.kozlowski+dt, gregkh
Cc: linux-renesas-soc, devicetree, linux-serial, Yoshihiro Shimoda,
Krzysztof Kozlowski
Initial support for the Renesas White Hawk CPU and BreakOut boards.
Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
---
arch/arm64/boot/dts/renesas/Makefile | 2 +
.../dts/renesas/r8a779g0-white-hawk-cpu.dtsi | 45 +++++++++++++++++++
.../boot/dts/renesas/r8a779g0-white-hawk.dts | 22 +++++++++
3 files changed, 69 insertions(+)
create mode 100644 arch/arm64/boot/dts/renesas/r8a779g0-white-hawk-cpu.dtsi
create mode 100644 arch/arm64/boot/dts/renesas/r8a779g0-white-hawk.dts
diff --git a/arch/arm64/boot/dts/renesas/Makefile b/arch/arm64/boot/dts/renesas/Makefile
index fa9811251fd7..15309309a2e1 100644
--- a/arch/arm64/boot/dts/renesas/Makefile
+++ b/arch/arm64/boot/dts/renesas/Makefile
@@ -65,6 +65,8 @@ dtb-$(CONFIG_ARCH_R8A779A0) += r8a779a0-falcon.dtb
dtb-$(CONFIG_ARCH_R8A779F0) += r8a779f0-spider.dtb
+dtb-$(CONFIG_ARCH_R8A779G0) += r8a779g0-white-hawk.dtb
+
dtb-$(CONFIG_ARCH_R8A77951) += r8a779m1-salvator-xs.dtb
dtb-$(CONFIG_ARCH_R8A77951) += r8a779m1-ulcb.dtb
dtb-$(CONFIG_ARCH_R8A77951) += r8a779m1-ulcb-kf.dtb
diff --git a/arch/arm64/boot/dts/renesas/r8a779g0-white-hawk-cpu.dtsi b/arch/arm64/boot/dts/renesas/r8a779g0-white-hawk-cpu.dtsi
new file mode 100644
index 000000000000..8784bce7ec22
--- /dev/null
+++ b/arch/arm64/boot/dts/renesas/r8a779g0-white-hawk-cpu.dtsi
@@ -0,0 +1,45 @@
+// SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause)
+/*
+ * Device Tree Source for the White Hawk CPU board
+ *
+ * Copyright (C) 2022 Renesas Electronics Corp.
+ */
+
+#include "r8a779g0.dtsi"
+
+/ {
+ model = "Renesas White Hawk CPU board";
+ compatible = "renesas,white-hawk-cpu", "renesas,r8a779g0";
+
+ memory@48000000 {
+ device_type = "memory";
+ /* first 128MB is reserved for secure area. */
+ reg = <0x0 0x48000000 0x0 0x78000000>;
+ };
+
+ memory@480000000 {
+ device_type = "memory";
+ reg = <0x4 0x80000000 0x0 0x80000000>;
+ };
+
+ memory@600000000 {
+ device_type = "memory";
+ reg = <0x6 0x00000000 0x1 0x00000000>;
+ };
+};
+
+&extal_clk {
+ clock-frequency = <16666666>;
+};
+
+&extalr_clk {
+ clock-frequency = <32768>;
+};
+
+&hscif0 {
+ status = "okay";
+};
+
+&scif_clk {
+ clock-frequency = <24000000>;
+};
diff --git a/arch/arm64/boot/dts/renesas/r8a779g0-white-hawk.dts b/arch/arm64/boot/dts/renesas/r8a779g0-white-hawk.dts
new file mode 100644
index 000000000000..e905ac63b130
--- /dev/null
+++ b/arch/arm64/boot/dts/renesas/r8a779g0-white-hawk.dts
@@ -0,0 +1,22 @@
+// SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause)
+/*
+ * Device Tree Source for the White Hawk CPU and BreakOut boards
+ *
+ * Copyright (C) 2022 Renesas Electronics Corp.
+ */
+
+/dts-v1/;
+#include "r8a779g0-white-hawk-cpu.dtsi"
+
+/ {
+ model = "Renesas White Hawk CPU and Breakout boards based on r8a779g0";
+ compatible = "renesas,white-hawk-breakout", "renesas,white-hawk-cpu", "renesas,r8a779g0";
+
+ aliases {
+ serial0 = &hscif0;
+ };
+
+ chosen {
+ stdout-path = "serial0:921600n8";
+ };
+};
--
2.25.1
^ permalink raw reply related [flat|nested] 17+ messages in thread
* Re: [PATCH v2 3/7] dt-bindings: serial: renesas,hscif: Document r8a779g0 bindings
2022-04-25 6:41 ` [PATCH v2 3/7] dt-bindings: serial: renesas,hscif: Document r8a779g0 bindings Yoshihiro Shimoda
@ 2022-04-25 8:13 ` Geert Uytterhoeven
0 siblings, 0 replies; 17+ messages in thread
From: Geert Uytterhoeven @ 2022-04-25 8:13 UTC (permalink / raw)
To: Yoshihiro Shimoda
Cc: Magnus Damm, Rob Herring, Krzysztof Kozlowski, Greg KH,
Linux-Renesas,
open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
open list:SERIAL DRIVERS, Krzysztof Kozlowski
On Mon, Apr 25, 2022 at 8:42 AM Yoshihiro Shimoda
<yoshihiro.shimoda.uh@renesas.com> wrote:
> R-Car V4H (R8A779G0) SoC has the R-Car Gen4 compatible HSCIF ports,
> so document the SoC specific bindings.
>
> Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
> Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
^ permalink raw reply [flat|nested] 17+ messages in thread
* Re: [PATCH v2 2/7] dt-bindings: clock: Add r8a779g0 CPG Core Clock Definitions
2022-04-25 6:41 ` [PATCH v2 2/7] dt-bindings: clock: Add r8a779g0 CPG Core Clock Definitions Yoshihiro Shimoda
@ 2022-04-25 8:26 ` Geert Uytterhoeven
2022-04-25 18:39 ` Krzysztof Kozlowski
1 sibling, 0 replies; 17+ messages in thread
From: Geert Uytterhoeven @ 2022-04-25 8:26 UTC (permalink / raw)
To: Yoshihiro Shimoda
Cc: Magnus Damm, Rob Herring, Krzysztof Kozlowski, Greg KH,
Linux-Renesas,
open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
open list:SERIAL DRIVERS
On Mon, Apr 25, 2022 at 8:42 AM Yoshihiro Shimoda
<yoshihiro.shimoda.uh@renesas.com> wrote:
> Add all Clock Pulse Generator Core Clock Outputs for the Renesas
> R-Car V4H (R8A779G0) SoC.
>
> Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
i.e. will queue for v5.19 a branch shared by driver and DT.
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
^ permalink raw reply [flat|nested] 17+ messages in thread
* Re: [PATCH v2 4/7] clk: renesas: rcar-gen4: Add CLK_TYPE_GEN4_PLL4
2022-04-25 6:41 ` [PATCH v2 4/7] clk: renesas: rcar-gen4: Add CLK_TYPE_GEN4_PLL4 Yoshihiro Shimoda
@ 2022-04-25 14:48 ` Geert Uytterhoeven
0 siblings, 0 replies; 17+ messages in thread
From: Geert Uytterhoeven @ 2022-04-25 14:48 UTC (permalink / raw)
To: Yoshihiro Shimoda
Cc: Magnus Damm, Rob Herring, Krzysztof Kozlowski, Greg KH,
Linux-Renesas,
open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
open list:SERIAL DRIVERS
Hi Shimoda-san,
On Mon, Apr 25, 2022 at 8:42 AM Yoshihiro Shimoda
<yoshihiro.shimoda.uh@renesas.com> wrote:
> R-Car V4H (r8a779g0) has PLL4 so that add CLK_TYPE_GEN4_PLL4.
>
> Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
> --- a/drivers/clk/renesas/r8a779a0-cpg-mssr.c
> +++ b/drivers/clk/renesas/r8a779a0-cpg-mssr.c
> @@ -253,11 +253,11 @@ static const unsigned int r8a779a0_crit_mod_clks[] __initconst = {
> #define CPG_PLL_CONFIG_INDEX(md) ((((md) & BIT(14)) >> 13) | \
> (((md) & BIT(13)) >> 13))
> static const struct rcar_gen4_cpg_pll_config cpg_pll_configs[4] = {
> - /* EXTAL div PLL1 mult/div PLL2 mult/div PLL3 mult/div PLL5 mult/div PLL6 mult/div OSC prediv */
> - { 1, 128, 1, 0, 0, 0, 0, 192, 1, 0, 0, 16, },
> - { 1, 106, 1, 0, 0, 0, 0, 160, 1, 0, 0, 19, },
> - { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, },
> - { 2, 128, 1, 0, 0, 0, 0, 192, 1, 0, 0, 32, },
> + /* EXTAL div PLL1 mult/div PLL2 mult/div PLL3 mult/div PLL4 mult/div PLL5 mult/div PLL6 mult/div OSC prediv */
> + { 1, 128, 1, 0, 0, 0, 0, 144, 1, 192, 1, 0, 0, 16, },
> + { 1, 106, 1, 0, 0, 0, 0, 120, 1, 160, 1, 0, 0, 19, },
> + { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, },
> + { 2, 128, 1, 0, 0, 0, 0, 128, 1, 192, 1, 0, 0, 32, },
144?
With that fixed (I can fix that while applying)
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
^ permalink raw reply [flat|nested] 17+ messages in thread
* Re: [PATCH v2 2/7] dt-bindings: clock: Add r8a779g0 CPG Core Clock Definitions
2022-04-25 6:41 ` [PATCH v2 2/7] dt-bindings: clock: Add r8a779g0 CPG Core Clock Definitions Yoshihiro Shimoda
2022-04-25 8:26 ` Geert Uytterhoeven
@ 2022-04-25 18:39 ` Krzysztof Kozlowski
1 sibling, 0 replies; 17+ messages in thread
From: Krzysztof Kozlowski @ 2022-04-25 18:39 UTC (permalink / raw)
To: Yoshihiro Shimoda, geert+renesas, magnus.damm, robh+dt,
krzysztof.kozlowski+dt, gregkh
Cc: linux-renesas-soc, devicetree, linux-serial
On 25/04/2022 08:41, Yoshihiro Shimoda wrote:
> Add all Clock Pulse Generator Core Clock Outputs for the Renesas
> R-Car V4H (R8A779G0) SoC.
>
> Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Best regards,
Krzysztof
^ permalink raw reply [flat|nested] 17+ messages in thread
* Re: [PATCH v2 5/7] clk: renesas: cpg-mssr: Add support for R-Car V4H
2022-04-25 6:41 ` [PATCH v2 5/7] clk: renesas: cpg-mssr: Add support for R-Car V4H Yoshihiro Shimoda
@ 2022-04-27 14:26 ` Geert Uytterhoeven
2022-04-28 7:16 ` Yoshihiro Shimoda
0 siblings, 1 reply; 17+ messages in thread
From: Geert Uytterhoeven @ 2022-04-27 14:26 UTC (permalink / raw)
To: Yoshihiro Shimoda
Cc: Magnus Damm, Rob Herring, Krzysztof Kozlowski, Greg KH,
Linux-Renesas,
open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
open list:SERIAL DRIVERS
Hi Shimoda-san,
On Mon, Apr 25, 2022 at 8:42 AM Yoshihiro Shimoda
<yoshihiro.shimoda.uh@renesas.com> wrote:
> Initial CPG support for R-Car V4H (r8a779g0).
>
> Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
Thanks for your patch!
> --- /dev/null
> +++ b/drivers/clk/renesas/r8a779g0-cpg-mssr.c
> @@ -0,0 +1,217 @@
> +// SPDX-License-Identifier: GPL-2.0
> +/*
> + * r8a779g0 Clock Pulse Generator / Module Standby and Software Reset
> + *
> + * Copyright (C) 2022 Renesas Electronics Corp.
> + *
> + * Based on r8a779g0-cpg-mssr.c
I.e. based on itself? ;-)
> +static const struct cpg_core_clk r8a779g0_core_clks[] __initconst = {
> + /* External Clock Inputs */
> + DEF_INPUT("extal", CLK_EXTAL),
> + DEF_INPUT("extalr", CLK_EXTALR),
> +
> + /* Internal Core Clocks */
> + DEF_BASE(".main", CLK_MAIN, CLK_TYPE_GEN4_MAIN, CLK_EXTAL),
> + DEF_BASE(".pll1", CLK_PLL1, CLK_TYPE_GEN4_PLL1, CLK_MAIN),
> + DEF_BASE(".pll2", CLK_PLL2, CLK_TYPE_GEN4_PLL2, CLK_MAIN),
> + DEF_BASE(".pll3", CLK_PLL3, CLK_TYPE_GEN4_PLL3, CLK_MAIN),
> + DEF_BASE(".pll4", CLK_PLL4, CLK_TYPE_GEN4_PLL4, CLK_MAIN),
> + DEF_BASE(".pll5", CLK_PLL5, CLK_TYPE_GEN4_PLL5, CLK_MAIN),
> + DEF_BASE(".pll6", CLK_PLL6, CLK_TYPE_GEN4_PLL6, CLK_MAIN),
> +
> + DEF_FIXED(".pll1_div2", CLK_PLL1_DIV2, CLK_PLL1, 2, 1),
> + DEF_FIXED(".pll2_div2", CLK_PLL2_DIV2, CLK_PLL2, 2, 1),
> + DEF_FIXED(".pll3_div2", CLK_PLL3_DIV2, CLK_PLL3, 2, 1),
> + DEF_FIXED(".pll4_div2", CLK_PLL4_DIV2, CLK_PLL4, 2, 1),
> + DEF_FIXED(".pll5_div2", CLK_PLL5_DIV2, CLK_PLL5, 2, 1),
> + DEF_FIXED(".pll5_div4", CLK_PLL5_DIV4, CLK_PLL5_DIV2, 2, 1),
> + DEF_FIXED(".pll6_div2", CLK_PLL6_DIV2, CLK_PLL6, 2, 1),
> + DEF_FIXED(".s0", CLK_S0, CLK_PLL1_DIV2, 2, 1),
> + DEF_FIXED(".s0_vio", CLK_S0_VIO, CLK_PLL1_DIV2, 2, 1),
> + DEF_FIXED(".s0_vc", CLK_S0_VC, CLK_PLL1_DIV2, 2, 1),
> + DEF_FIXED(".s0_hsc", CLK_S0_HSC, CLK_PLL1_DIV2, 2, 1),
> + DEF_FIXED(".sv_vip", CLK_SV_VIP, CLK_PLL1_DIV2, 2, 1),
CLK_SV_VIP runs at 640 instead of 800 MHz, so CLK_PLL1 / 5?
> + DEF_FIXED(".sv_ir", CLK_SV_IR, CLK_PLL1_DIV2, 2, 1),
Likewise for CLK_SV_IR.
> + DEF_BASE(".sdsrc", CLK_SDSRC, CLK_TYPE_GEN4_SDSRC, CLK_PLL5),
> + DEF_RATE(".oco", CLK_OCO, 32768),
> +
> + DEF_BASE(".rpcsrc", CLK_RPCSRC, CLK_TYPE_GEN4_RPCSRC, CLK_PLL5),
> + DEF_BASE(".rpc", R8A779G0_CLK_RPC, CLK_TYPE_GEN4_RPC, CLK_RPCSRC),
"rpc".
> + DEF_BASE("rpcd2", R8A779G0_CLK_RPCD2, CLK_TYPE_GEN4_RPCD2, R8A779G0_CLK_RPC),
Please move "rpc" and "rpcd2" to Core Clock Outputs below,
as they are not Internal Core Clocks.
> + DEF_FIXED(".vio", CLK_VIO, CLK_PLL5_DIV2, 3, 1),
> + DEF_FIXED(".vc", CLK_VC, CLK_PLL5_DIV2, 3, 1),
> +
> + /* Core Clock Outputs */
> + DEF_FIXED("s0d2", R8A779G0_CLK_S0D2, CLK_S0, 2, 1),
> + DEF_FIXED("s0d3", R8A779G0_CLK_S0D3, CLK_S0, 3, 1),
> + DEF_FIXED("s0d4", R8A779G0_CLK_S0D4, CLK_S0, 4, 1),
> + DEF_FIXED("cl16m", R8A779G0_CLK_CL16M, CLK_S0, 48, 1),
> + DEF_FIXED("s0d1_vio", R8A779G0_CLK_S0D1_VIO, CLK_S0_VIO, 1, 1),
> + DEF_FIXED("s0d2_vio", R8A779G0_CLK_S0D2_VIO, CLK_S0_VIO, 2, 1),
> + DEF_FIXED("s0d4_vio", R8A779G0_CLK_S0D4_VIO, CLK_S0_VIO, 4, 1),
> + DEF_FIXED("s0d8_vio", R8A779G0_CLK_S0D8_VIO, CLK_S0_VIO, 8, 1),
> + DEF_FIXED("s0d1_vc", R8A779G0_CLK_S0D1_VC, CLK_S0_VC, 1, 1),
> + DEF_FIXED("s0d2_vc", R8A779G0_CLK_S0D2_VC, CLK_S0_VC, 2, 1),
> + DEF_FIXED("s0d4_vc", R8A779G0_CLK_S0D4_VC, CLK_S0_VC, 4, 1),
> + DEF_FIXED("s0d2_mm", R8A779G0_CLK_S0D2_MM, CLK_S0, 2, 1),
> + DEF_FIXED("s0d4_mm", R8A779G0_CLK_S0D4_MM, CLK_S0, 4, 1),
> + DEF_FIXED("cl16m_mm", R8A779G0_CLK_CL16M_MM, CLK_S0, 48, 1),
> + DEF_FIXED("s0d2_u3dg", R8A779G0_CLK_S0D2_U3DG, CLK_S0, 2, 1),
> + DEF_FIXED("s0d4_u3dg", R8A779G0_CLK_S0D4_U3DG, CLK_S0, 4, 1),
> + DEF_FIXED("s0d2_rt", R8A779G0_CLK_S0D2_RT, CLK_S0, 2, 1),
> + DEF_FIXED("s0d3_rt", R8A779G0_CLK_S0D3_RT, CLK_S0, 3, 1),
> + DEF_FIXED("s0d4_rt", R8A779G0_CLK_S0D4_RT, CLK_S0, 4, 1),
> + DEF_FIXED("s0d6_rt", R8A779G0_CLK_S0D6_RT, CLK_S0, 6, 1),
> + DEF_FIXED("s0d24_rt", R8A779G0_CLK_S0D24_RT, CLK_S0, 24, 1),
> + DEF_FIXED("cl16m_rt", R8A779G0_CLK_CL16M_RT, CLK_S0, 48, 1),
> + DEF_FIXED("s0d2_per", R8A779G0_CLK_S0D2_PER, CLK_S0, 2, 1),
> + DEF_FIXED("s0d3_per", R8A779G0_CLK_S0D3_PER, CLK_S0, 3, 1),
Missing "s0d4_per".
> + DEF_FIXED("s0d6_per", R8A779G0_CLK_S0D6_PER, CLK_S0, 6, 1),
> + DEF_FIXED("s0d12_per", R8A779G0_CLK_S0D12_PER, CLK_S0, 12, 1),
> + DEF_FIXED("s0d24_per", R8A779G0_CLK_S0D24_PER, CLK_S0, 24, 1),
> + DEF_FIXED("cl16m_per", R8A779G0_CLK_CL16M_PER, CLK_S0, 48, 1),
> + DEF_FIXED("s0d1_hsc", R8A779G0_CLK_S0D1_HSC, CLK_S0_HSC, 1, 1),
> + DEF_FIXED("s0d2_hsc", R8A779G0_CLK_S0D2_HSC, CLK_S0_HSC, 2, 1),
> + DEF_FIXED("s0d4_hsc", R8A779G0_CLK_S0D4_HSC, CLK_S0_HSC, 4, 1),
> + DEF_FIXED("cl16m_hsc", R8A779G0_CLK_CL16M_HSC, CLK_S0_HSC, 48, 1),
> + DEF_FIXED("s0d2_cc", R8A779G0_CLK_S0D2_CC, CLK_S0, 2, 1),
> + DEF_FIXED("svd1_ir", R8A779G0_CLK_SVD1_IR, CLK_SV_IR, 1, 1),
> + DEF_FIXED("svd2_ir", R8A779G0_CLK_SVD2_IR, CLK_SV_IR, 2, 1),
> + DEF_FIXED("svd1_vip", R8A779G0_CLK_SVD1_VIP, CLK_SV_VIP, 1, 1),
> + DEF_FIXED("svd2_vip", R8A779G0_CLK_SVD2_VIP, CLK_SV_VIP, 2, 1),
> + DEF_FIXED("s0d2_cc", R8A779G0_CLK_S0D2_CC, CLK_S0, 2, 1),
"s0d2_cc" is already defined 5 lines above.
> + DEF_FIXED("cbfusa", R8A779G0_CLK_CBFUSA, CLK_EXTAL, 2, 1),
> + DEF_FIXED("cpex", R8A779G0_CLK_CPEX, CLK_EXTAL, 2, 1),
> + DEF_FIXED("viobus", R8A779G0_CLK_VIOBUS, CLK_VIO, 1, 1),
> + DEF_FIXED("viobusd2", R8A779G0_CLK_VIOBUSD2, CLK_VIO, 2, 1),
> + DEF_FIXED("vcbus", R8A779G0_CLK_VCBUS, CLK_VC, 1, 1),
> + DEF_FIXED("vcbusd2", R8A779G0_CLK_VCBUSD2, CLK_VC, 2, 1),
> +
> + DEF_GEN4_SD("sd0", R8A779G0_CLK_SD0, CLK_SDSRC, 0x870),
> + DEF_DIV6P1("mso", R8A779G0_CLK_MSO, CLK_PLL5_DIV4, 0x87c),
> +
> + DEF_GEN4_OSC("osc", R8A779G0_CLK_OSC, CLK_EXTAL, 8),
> + DEF_GEN4_MDSEL("r", R8A779G0_CLK_R, 29, CLK_EXTALR, 1, CLK_OCO, 1),
> +};
> +
> +static const struct mssr_mod_clk r8a779g0_mod_clks[] __initconst = {
> + DEF_MOD("hscif0", 514, R8A779G0_CLK_S0D3_PER),
> + DEF_MOD("hscif1", 515, R8A779G0_CLK_S0D3_PER),
> + DEF_MOD("hscif2", 516, R8A779G0_CLK_S0D3_PER),
> + DEF_MOD("hscif3", 517, R8A779G0_CLK_S0D3_PER),
> +};
> +
> +/*
> + * CPG Clock Data
> + */
> +/*
> + * MD EXTAL PLL1 PLL2 PLL3 PLL4 PLL5 PLL6 OSC
> + * 14 13 (MHz)
> + * ----------------------------------------------------------------
You may want to make the horizontal line longer.
> + * 0 0 16.66 / 1 x192 x204 x192 x144 x192 x168 /8
> + * 0 1 20 / 1 x160 x170 x160 x120 x160 x140 /8
> + * 1 0 Prohibited setting
> + * 1 1 33.33 / 2 x192 x204 x192 x144 x192 x168 /8
The last column values (OSC) should be /15, /19, resp. /38.
> + */
> +#define CPG_PLL_CONFIG_INDEX(md) ((((md) & BIT(14)) >> 13) | \
> + (((md) & BIT(13)) >> 13))
> +
> +static const struct rcar_gen4_cpg_pll_config cpg_pll_configs[4] = {
> + /* EXTAL div PLL1 mult/div PLL2 mult/div PLL3 mult/div PLL4 mult/div PLL5 mult/div PLL6 mult/div OSC prediv */
> + { 1, 192, 1, 204, 1, 192, 1, 144, 1, 192, 1, 168, 1, 8, },
> + { 1, 160, 1, 170, 1, 160, 1, 120, 1, 160, 1, 140, 1, 8, },
> + { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, },
> + { 2, 192, 1, 204, 1, 192, 1, 144, 1, 192, 1, 168, 1, 8, },
The last column values should be 15, 19, 0, resp. 38.
The rest LGTM.
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
^ permalink raw reply [flat|nested] 17+ messages in thread
* Re: [PATCH v2 6/7] arm64: dts: renesas: Add Renesas R8A779G0 SoC support
2022-04-25 6:42 ` [PATCH v2 6/7] arm64: dts: renesas: Add Renesas R8A779G0 SoC support Yoshihiro Shimoda
@ 2022-04-27 14:37 ` Geert Uytterhoeven
2022-04-28 7:27 ` Yoshihiro Shimoda
0 siblings, 1 reply; 17+ messages in thread
From: Geert Uytterhoeven @ 2022-04-27 14:37 UTC (permalink / raw)
To: Yoshihiro Shimoda
Cc: Magnus Damm, Rob Herring, Krzysztof Kozlowski, Greg KH,
Linux-Renesas,
open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
open list:SERIAL DRIVERS
Hi Shimoda-san,
On Mon, Apr 25, 2022 at 8:42 AM Yoshihiro Shimoda
<yoshihiro.shimoda.uh@renesas.com> wrote:
> Add initial support for the Renesas R8A779G0 (R-Car V4H) SoC.
>
> Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
Thanks for your patch!
> --- /dev/null
> +++ b/arch/arm64/boot/dts/renesas/r8a779g0.dtsi
> + soc: soc {
> + hscif0: serial@e6540000 {
> + compatible = "renesas,hscif-r8a779g0",
> + "renesas,rcar-gen4-hscif",
> + "renesas,hscif";
> + reg = <0 0xe6540000 0 96>;
> + interrupts = <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>;
245
> + clocks = <&cpg CPG_MOD 514>,
> + <&cpg CPG_CORE R8A779G0_CLK_S0D3_PER>,
> + <&scif_clk>;
> + clock-names = "fck", "brg_int", "scif_clk";
> + power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>;
> + resets = <&cpg 514>;
> + status = "disabled";
> + };
The rest LGTM, so with the above fixed:
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
^ permalink raw reply [flat|nested] 17+ messages in thread
* Re: [PATCH v2 7/7] arm64: dts: renesas: Add Renesas White Hawk boards support
2022-04-25 6:42 ` [PATCH v2 7/7] arm64: dts: renesas: Add Renesas White Hawk boards support Yoshihiro Shimoda
@ 2022-04-27 14:52 ` Geert Uytterhoeven
0 siblings, 0 replies; 17+ messages in thread
From: Geert Uytterhoeven @ 2022-04-27 14:52 UTC (permalink / raw)
To: Yoshihiro Shimoda
Cc: Magnus Damm, Rob Herring, Krzysztof Kozlowski, Greg KH,
Linux-Renesas,
open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
open list:SERIAL DRIVERS, Krzysztof Kozlowski
On Mon, Apr 25, 2022 at 8:42 AM Yoshihiro Shimoda
<yoshihiro.shimoda.uh@renesas.com> wrote:
> Initial support for the Renesas White Hawk CPU and BreakOut boards.
>
> Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
> Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
^ permalink raw reply [flat|nested] 17+ messages in thread
* RE: [PATCH v2 5/7] clk: renesas: cpg-mssr: Add support for R-Car V4H
2022-04-27 14:26 ` Geert Uytterhoeven
@ 2022-04-28 7:16 ` Yoshihiro Shimoda
0 siblings, 0 replies; 17+ messages in thread
From: Yoshihiro Shimoda @ 2022-04-28 7:16 UTC (permalink / raw)
To: Geert Uytterhoeven
Cc: Magnus Damm, Rob Herring, Krzysztof Kozlowski, Greg KH,
Linux-Renesas,
open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
open list:SERIAL DRIVERS
Hi Geert-san,
Thank you for your review!
> From: Geert Uytterhoeven, Sent: Wednesday, April 27, 2022 11:26 PM
>
> On Mon, Apr 25, 2022 at 8:42 AM Yoshihiro Shimoda
> <yoshihiro.shimoda.uh@renesas.com> wrote:
> > Initial CPG support for R-Car V4H (r8a779g0).
> >
> > Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
>
> Thanks for your patch!
>
> > --- /dev/null
> > +++ b/drivers/clk/renesas/r8a779g0-cpg-mssr.c
> > @@ -0,0 +1,217 @@
> > +// SPDX-License-Identifier: GPL-2.0
> > +/*
> > + * r8a779g0 Clock Pulse Generator / Module Standby and Software Reset
> > + *
> > + * Copyright (C) 2022 Renesas Electronics Corp.
> > + *
> > + * Based on r8a779g0-cpg-mssr.c
>
> I.e. based on itself? ;-)
Oops! It's r8a779f0 instead :)
> > +static const struct cpg_core_clk r8a779g0_core_clks[] __initconst = {
> > + /* External Clock Inputs */
> > + DEF_INPUT("extal", CLK_EXTAL),
> > + DEF_INPUT("extalr", CLK_EXTALR),
> > +
> > + /* Internal Core Clocks */
> > + DEF_BASE(".main", CLK_MAIN, CLK_TYPE_GEN4_MAIN, CLK_EXTAL),
> > + DEF_BASE(".pll1", CLK_PLL1, CLK_TYPE_GEN4_PLL1, CLK_MAIN),
> > + DEF_BASE(".pll2", CLK_PLL2, CLK_TYPE_GEN4_PLL2, CLK_MAIN),
> > + DEF_BASE(".pll3", CLK_PLL3, CLK_TYPE_GEN4_PLL3, CLK_MAIN),
> > + DEF_BASE(".pll4", CLK_PLL4, CLK_TYPE_GEN4_PLL4, CLK_MAIN),
> > + DEF_BASE(".pll5", CLK_PLL5, CLK_TYPE_GEN4_PLL5, CLK_MAIN),
> > + DEF_BASE(".pll6", CLK_PLL6, CLK_TYPE_GEN4_PLL6, CLK_MAIN),
> > +
> > + DEF_FIXED(".pll1_div2", CLK_PLL1_DIV2, CLK_PLL1, 2, 1),
> > + DEF_FIXED(".pll2_div2", CLK_PLL2_DIV2, CLK_PLL2, 2, 1),
> > + DEF_FIXED(".pll3_div2", CLK_PLL3_DIV2, CLK_PLL3, 2, 1),
> > + DEF_FIXED(".pll4_div2", CLK_PLL4_DIV2, CLK_PLL4, 2, 1),
> > + DEF_FIXED(".pll5_div2", CLK_PLL5_DIV2, CLK_PLL5, 2, 1),
> > + DEF_FIXED(".pll5_div4", CLK_PLL5_DIV4, CLK_PLL5_DIV2, 2, 1),
> > + DEF_FIXED(".pll6_div2", CLK_PLL6_DIV2, CLK_PLL6, 2, 1),
> > + DEF_FIXED(".s0", CLK_S0, CLK_PLL1_DIV2, 2, 1),
> > + DEF_FIXED(".s0_vio", CLK_S0_VIO, CLK_PLL1_DIV2, 2, 1),
> > + DEF_FIXED(".s0_vc", CLK_S0_VC, CLK_PLL1_DIV2, 2, 1),
> > + DEF_FIXED(".s0_hsc", CLK_S0_HSC, CLK_PLL1_DIV2, 2, 1),
> > + DEF_FIXED(".sv_vip", CLK_SV_VIP, CLK_PLL1_DIV2, 2, 1),
>
> CLK_SV_VIP runs at 640 instead of 800 MHz, so CLK_PLL1 / 5?
You're correct. I'll fix it.
> > + DEF_FIXED(".sv_ir", CLK_SV_IR, CLK_PLL1_DIV2, 2, 1),
>
> Likewise for CLK_SV_IR.
Yes, I'll fix it.
> > + DEF_BASE(".sdsrc", CLK_SDSRC, CLK_TYPE_GEN4_SDSRC, CLK_PLL5),
> > + DEF_RATE(".oco", CLK_OCO, 32768),
> > +
> > + DEF_BASE(".rpcsrc", CLK_RPCSRC, CLK_TYPE_GEN4_RPCSRC, CLK_PLL5),
> > + DEF_BASE(".rpc", R8A779G0_CLK_RPC, CLK_TYPE_GEN4_RPC, CLK_RPCSRC),
>
> "rpc".
I got it.
> > + DEF_BASE("rpcd2", R8A779G0_CLK_RPCD2, CLK_TYPE_GEN4_RPCD2, R8A779G0_CLK_RPC),
>
> Please move "rpc" and "rpcd2" to Core Clock Outputs below,
> as they are not Internal Core Clocks.
I'll fix it.
> > + DEF_FIXED(".vio", CLK_VIO, CLK_PLL5_DIV2, 3, 1),
> > + DEF_FIXED(".vc", CLK_VC, CLK_PLL5_DIV2, 3, 1),
> > +
> > + /* Core Clock Outputs */
> > + DEF_FIXED("s0d2", R8A779G0_CLK_S0D2, CLK_S0, 2, 1),
> > + DEF_FIXED("s0d3", R8A779G0_CLK_S0D3, CLK_S0, 3, 1),
> > + DEF_FIXED("s0d4", R8A779G0_CLK_S0D4, CLK_S0, 4, 1),
> > + DEF_FIXED("cl16m", R8A779G0_CLK_CL16M, CLK_S0, 48, 1),
> > + DEF_FIXED("s0d1_vio", R8A779G0_CLK_S0D1_VIO, CLK_S0_VIO, 1, 1),
> > + DEF_FIXED("s0d2_vio", R8A779G0_CLK_S0D2_VIO, CLK_S0_VIO, 2, 1),
> > + DEF_FIXED("s0d4_vio", R8A779G0_CLK_S0D4_VIO, CLK_S0_VIO, 4, 1),
> > + DEF_FIXED("s0d8_vio", R8A779G0_CLK_S0D8_VIO, CLK_S0_VIO, 8, 1),
> > + DEF_FIXED("s0d1_vc", R8A779G0_CLK_S0D1_VC, CLK_S0_VC, 1, 1),
> > + DEF_FIXED("s0d2_vc", R8A779G0_CLK_S0D2_VC, CLK_S0_VC, 2, 1),
> > + DEF_FIXED("s0d4_vc", R8A779G0_CLK_S0D4_VC, CLK_S0_VC, 4, 1),
> > + DEF_FIXED("s0d2_mm", R8A779G0_CLK_S0D2_MM, CLK_S0, 2, 1),
> > + DEF_FIXED("s0d4_mm", R8A779G0_CLK_S0D4_MM, CLK_S0, 4, 1),
> > + DEF_FIXED("cl16m_mm", R8A779G0_CLK_CL16M_MM, CLK_S0, 48, 1),
> > + DEF_FIXED("s0d2_u3dg", R8A779G0_CLK_S0D2_U3DG, CLK_S0, 2, 1),
> > + DEF_FIXED("s0d4_u3dg", R8A779G0_CLK_S0D4_U3DG, CLK_S0, 4, 1),
> > + DEF_FIXED("s0d2_rt", R8A779G0_CLK_S0D2_RT, CLK_S0, 2, 1),
> > + DEF_FIXED("s0d3_rt", R8A779G0_CLK_S0D3_RT, CLK_S0, 3, 1),
> > + DEF_FIXED("s0d4_rt", R8A779G0_CLK_S0D4_RT, CLK_S0, 4, 1),
> > + DEF_FIXED("s0d6_rt", R8A779G0_CLK_S0D6_RT, CLK_S0, 6, 1),
> > + DEF_FIXED("s0d24_rt", R8A779G0_CLK_S0D24_RT, CLK_S0, 24, 1),
> > + DEF_FIXED("cl16m_rt", R8A779G0_CLK_CL16M_RT, CLK_S0, 48, 1),
> > + DEF_FIXED("s0d2_per", R8A779G0_CLK_S0D2_PER, CLK_S0, 2, 1),
> > + DEF_FIXED("s0d3_per", R8A779G0_CLK_S0D3_PER, CLK_S0, 3, 1),
>
> Missing "s0d4_per".
Oops. I'll add it.
> > + DEF_FIXED("s0d6_per", R8A779G0_CLK_S0D6_PER, CLK_S0, 6, 1),
> > + DEF_FIXED("s0d12_per", R8A779G0_CLK_S0D12_PER, CLK_S0, 12, 1),
> > + DEF_FIXED("s0d24_per", R8A779G0_CLK_S0D24_PER, CLK_S0, 24, 1),
> > + DEF_FIXED("cl16m_per", R8A779G0_CLK_CL16M_PER, CLK_S0, 48, 1),
> > + DEF_FIXED("s0d1_hsc", R8A779G0_CLK_S0D1_HSC, CLK_S0_HSC, 1, 1),
> > + DEF_FIXED("s0d2_hsc", R8A779G0_CLK_S0D2_HSC, CLK_S0_HSC, 2, 1),
> > + DEF_FIXED("s0d4_hsc", R8A779G0_CLK_S0D4_HSC, CLK_S0_HSC, 4, 1),
> > + DEF_FIXED("cl16m_hsc", R8A779G0_CLK_CL16M_HSC, CLK_S0_HSC, 48, 1),
> > + DEF_FIXED("s0d2_cc", R8A779G0_CLK_S0D2_CC, CLK_S0, 2, 1),
> > + DEF_FIXED("svd1_ir", R8A779G0_CLK_SVD1_IR, CLK_SV_IR, 1, 1),
> > + DEF_FIXED("svd2_ir", R8A779G0_CLK_SVD2_IR, CLK_SV_IR, 2, 1),
> > + DEF_FIXED("svd1_vip", R8A779G0_CLK_SVD1_VIP, CLK_SV_VIP, 1, 1),
> > + DEF_FIXED("svd2_vip", R8A779G0_CLK_SVD2_VIP, CLK_SV_VIP, 2, 1),
> > + DEF_FIXED("s0d2_cc", R8A779G0_CLK_S0D2_CC, CLK_S0, 2, 1),
>
> "s0d2_cc" is already defined 5 lines above.
Oops. I'll remove this.
> > + DEF_FIXED("cbfusa", R8A779G0_CLK_CBFUSA, CLK_EXTAL, 2, 1),
> > + DEF_FIXED("cpex", R8A779G0_CLK_CPEX, CLK_EXTAL, 2, 1),
> > + DEF_FIXED("viobus", R8A779G0_CLK_VIOBUS, CLK_VIO, 1, 1),
> > + DEF_FIXED("viobusd2", R8A779G0_CLK_VIOBUSD2, CLK_VIO, 2, 1),
> > + DEF_FIXED("vcbus", R8A779G0_CLK_VCBUS, CLK_VC, 1, 1),
> > + DEF_FIXED("vcbusd2", R8A779G0_CLK_VCBUSD2, CLK_VC, 2, 1),
> > +
> > + DEF_GEN4_SD("sd0", R8A779G0_CLK_SD0, CLK_SDSRC, 0x870),
> > + DEF_DIV6P1("mso", R8A779G0_CLK_MSO, CLK_PLL5_DIV4, 0x87c),
> > +
> > + DEF_GEN4_OSC("osc", R8A779G0_CLK_OSC, CLK_EXTAL, 8),
> > + DEF_GEN4_MDSEL("r", R8A779G0_CLK_R, 29, CLK_EXTALR, 1, CLK_OCO, 1),
> > +};
> > +
> > +static const struct mssr_mod_clk r8a779g0_mod_clks[] __initconst = {
> > + DEF_MOD("hscif0", 514, R8A779G0_CLK_S0D3_PER),
> > + DEF_MOD("hscif1", 515, R8A779G0_CLK_S0D3_PER),
> > + DEF_MOD("hscif2", 516, R8A779G0_CLK_S0D3_PER),
> > + DEF_MOD("hscif3", 517, R8A779G0_CLK_S0D3_PER),
> > +};
> > +
> > +/*
> > + * CPG Clock Data
> > + */
> > +/*
> > + * MD EXTAL PLL1 PLL2 PLL3 PLL4 PLL5 PLL6 OSC
> > + * 14 13 (MHz)
> > + * ----------------------------------------------------------------
>
> You may want to make the horizontal line longer.
I'll fix it.
> > + * 0 0 16.66 / 1 x192 x204 x192 x144 x192 x168 /8
> > + * 0 1 20 / 1 x160 x170 x160 x120 x160 x140 /8
> > + * 1 0 Prohibited setting
> > + * 1 1 33.33 / 2 x192 x204 x192 x144 x192 x168 /8
>
> The last column values (OSC) should be /15, /19, resp. /38.
I completely misunderstood these parameters. I'll fix it.
> > + */
> > +#define CPG_PLL_CONFIG_INDEX(md) ((((md) & BIT(14)) >> 13) | \
> > + (((md) & BIT(13)) >> 13))
> > +
> > +static const struct rcar_gen4_cpg_pll_config cpg_pll_configs[4] = {
> > + /* EXTAL div PLL1 mult/div PLL2 mult/div PLL3 mult/div PLL4 mult/div PLL5 mult/div PLL6 mult/div
> OSC prediv */
> > + { 1, 192, 1, 204, 1, 192, 1, 144, 1, 192, 1, 168, 1,
> 8, },
> > + { 1, 160, 1, 170, 1, 160, 1, 120, 1, 160, 1, 140, 1,
> 8, },
> > + { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
> 0, },
> > + { 2, 192, 1, 204, 1, 192, 1, 144, 1, 192, 1, 168, 1,
> 8, },
>
> The last column values should be 15, 19, 0, resp. 38.
I got it.
> The rest LGTM.
Thanks!
Best regards,
Yoshihiro Shimoda
^ permalink raw reply [flat|nested] 17+ messages in thread
* RE: [PATCH v2 6/7] arm64: dts: renesas: Add Renesas R8A779G0 SoC support
2022-04-27 14:37 ` Geert Uytterhoeven
@ 2022-04-28 7:27 ` Yoshihiro Shimoda
0 siblings, 0 replies; 17+ messages in thread
From: Yoshihiro Shimoda @ 2022-04-28 7:27 UTC (permalink / raw)
To: Geert Uytterhoeven
Cc: Magnus Damm, Rob Herring, Krzysztof Kozlowski, Greg KH,
Linux-Renesas,
open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
open list:SERIAL DRIVERS
Hi Geert-san,
> From: Geert Uytterhoeven, Sent: Wednesday, April 27, 2022 11:37 PM
>
> On Mon, Apr 25, 2022 at 8:42 AM Yoshihiro Shimoda
> <yoshihiro.shimoda.uh@renesas.com> wrote:
> > Add initial support for the Renesas R8A779G0 (R-Car V4H) SoC.
> >
> > Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
>
> Thanks for your patch!
Thank you for your review!
> > --- /dev/null
> > +++ b/arch/arm64/boot/dts/renesas/r8a779g0.dtsi
>
> > + soc: soc {
>
> > + hscif0: serial@e6540000 {
> > + compatible = "renesas,hscif-r8a779g0",
> > + "renesas,rcar-gen4-hscif",
> > + "renesas,hscif";
> > + reg = <0 0xe6540000 0 96>;
> > + interrupts = <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>;
>
> 245
Oops! I'll fix it.
> > + clocks = <&cpg CPG_MOD 514>,
> > + <&cpg CPG_CORE R8A779G0_CLK_S0D3_PER>,
> > + <&scif_clk>;
> > + clock-names = "fck", "brg_int", "scif_clk";
> > + power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>;
> > + resets = <&cpg 514>;
> > + status = "disabled";
> > + };
>
> The rest LGTM, so with the above fixed:
> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Thank you for your review!
Best regards,
Yoshihiro Shimoda
^ permalink raw reply [flat|nested] 17+ messages in thread
end of thread, other threads:[~2022-04-28 7:27 UTC | newest]
Thread overview: 17+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2022-04-25 6:41 [PATCH v2 0/7] treewide: Initial support for R-Car V4H Yoshihiro Shimoda
2022-04-25 6:41 ` [PATCH v2 1/7] dt-bindings: power: Add r8a779g0 SYSC power domain definitions Yoshihiro Shimoda
2022-04-25 6:41 ` [PATCH v2 2/7] dt-bindings: clock: Add r8a779g0 CPG Core Clock Definitions Yoshihiro Shimoda
2022-04-25 8:26 ` Geert Uytterhoeven
2022-04-25 18:39 ` Krzysztof Kozlowski
2022-04-25 6:41 ` [PATCH v2 3/7] dt-bindings: serial: renesas,hscif: Document r8a779g0 bindings Yoshihiro Shimoda
2022-04-25 8:13 ` Geert Uytterhoeven
2022-04-25 6:41 ` [PATCH v2 4/7] clk: renesas: rcar-gen4: Add CLK_TYPE_GEN4_PLL4 Yoshihiro Shimoda
2022-04-25 14:48 ` Geert Uytterhoeven
2022-04-25 6:41 ` [PATCH v2 5/7] clk: renesas: cpg-mssr: Add support for R-Car V4H Yoshihiro Shimoda
2022-04-27 14:26 ` Geert Uytterhoeven
2022-04-28 7:16 ` Yoshihiro Shimoda
2022-04-25 6:42 ` [PATCH v2 6/7] arm64: dts: renesas: Add Renesas R8A779G0 SoC support Yoshihiro Shimoda
2022-04-27 14:37 ` Geert Uytterhoeven
2022-04-28 7:27 ` Yoshihiro Shimoda
2022-04-25 6:42 ` [PATCH v2 7/7] arm64: dts: renesas: Add Renesas White Hawk boards support Yoshihiro Shimoda
2022-04-27 14:52 ` Geert Uytterhoeven
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