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From: "Lazar, Lijo" <lijo.lazar@amd.com>
To: Evan Quan <evan.quan@amd.com>, amd-gfx@lists.freedesktop.org
Cc: Alexander.Deucher@amd.com
Subject: Re: [PATCH 4/5] drm/amd/pm: clear the cached dpm feature status
Date: Thu, 3 Jun 2021 16:34:18 +0530	[thread overview]
Message-ID: <1a396a96-3c99-1e16-b170-75667c97ccfc@amd.com> (raw)
In-Reply-To: <20210603045603.977998-4-evan.quan@amd.com>



On 6/3/2021 10:26 AM, Evan Quan wrote:
> For some ASICs, the real dpm feature disablement job is handled by
> PMFW during baco reset and custom pptable loading. Cached dpm feature
> status need to be cleared to pair that.
> 
> Change-Id: I9e37d80e13599833301c04711b097fb37c2e41f9
> Signed-off-by: Evan Quan <evan.quan@amd.com>
> ---
>   drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c | 18 ++++++++++++++++--
>   1 file changed, 16 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c b/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
> index c9a31556e077..fd7b1b8edeb7 100644
> --- a/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
> +++ b/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
> @@ -1352,6 +1352,16 @@ static int smu_hw_init(void *handle)
>   	return 0;
>   }
>   
> +static void smu_reset_cached_dpm_feature_status(struct smu_context *smu)
> +{
> +	struct smu_feature *feature = &smu->smu_feature;
> +
> +	mutex_lock(&feature->mutex);
> +	bitmap_zero(feature->enabled, feature->feature_num);
> +	bitmap_zero(feature->supported, feature->feature_num);

This will clear also clear the BACO feature status. Won't that affect 
using baco exit for runtime pm resume?

Thanks,
Lijo

> +	mutex_unlock(&feature->mutex);
> +}
> +
>   static int smu_disable_dpms(struct smu_context *smu)
>   {
>   	struct amdgpu_device *adev = smu->adev;
> @@ -1374,16 +1384,20 @@ static int smu_disable_dpms(struct smu_context *smu)
>   	 */
>   	if (smu->uploading_custom_pp_table &&
>   	    (adev->asic_type >= CHIP_NAVI10) &&
> -	    (adev->asic_type <= CHIP_DIMGREY_CAVEFISH))
> +	    (adev->asic_type <= CHIP_DIMGREY_CAVEFISH)) {
> +		smu_reset_cached_dpm_feature_status(smu);
>   		return 0;
> +	}
>   
>   	/*
>   	 * For Sienna_Cichlid, PMFW will handle the features disablement properly
>   	 * on BACO in. Driver involvement is unnecessary.
>   	 */
>   	if ((adev->asic_type == CHIP_SIENNA_CICHLID) &&
> -	     use_baco)
> +	     use_baco) {
> +		smu_reset_cached_dpm_feature_status(smu);
>   		return 0;
> +	}
>   
>   	/*
>   	 * For gpu reset, runpm and hibernation through BACO,
> 
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  reply	other threads:[~2021-06-03 11:04 UTC|newest]

Thread overview: 9+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-06-03  4:55 [PATCH 1/5] drm/amd/pm: drop the incomplete fix for Navi14 runpm issue Evan Quan
2021-06-03  4:56 ` [PATCH 2/5] drm/amd/pm: correct the runpm handling for BACO supported ASIC Evan Quan
2021-06-03  4:56 ` [PATCH 3/5] drm/amdgpu: correct the audio function initial Dstate Evan Quan
2021-06-03 11:08   ` Lazar, Lijo
2021-06-04  4:22     ` Quan, Evan
2021-06-03  4:56 ` [PATCH 4/5] drm/amd/pm: clear the cached dpm feature status Evan Quan
2021-06-03 11:04   ` Lazar, Lijo [this message]
2021-06-04  4:23     ` Quan, Evan
2021-06-03  4:56 ` [PATCH 5/5] drm/amd/pm: correct the dpm features disablement for Navi1x Evan Quan

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