From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S936468AbeE2PYE (ORCPT ); Tue, 29 May 2018 11:24:04 -0400 Received: from esa6.microchip.iphmx.com ([216.71.154.253]:27017 "EHLO esa6.microchip.iphmx.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S935483AbeE2PYC (ORCPT ); Tue, 29 May 2018 11:24:02 -0400 X-IronPort-AV: E=Sophos;i="5.49,456,1520924400"; d="scan'208";a="12000422" Subject: Re: [PATCH] mtd: nand: raw: atmel: add module param to avoid using dma To: Boris Brezillon CC: Peter Rosin , Tudor Ambarus , Nicolas Ferre , Ludovic Desroches , Alexandre Belloni , Marek Vasut , Josh Wu , Cyrille Pitchen , , , Richard Weinberger , Brian Norris , David Woodhouse , References: <20180329131054.22506-1-peda@axentia.se> <20180329153322.5e2fc1e7@bbrezillon> <20180329154416.5c1a0013@bbrezillon> <20180402142249.7e076a64@bbrezillon> <20180402212843.164d5d21@bbrezillon> <20180402222020.1d344c14@bbrezillon> <20180403091813.5fb5c18c@bbrezillon> <959d826d-1a98-ca22-acee-a4548427fcd3@microchip.com> <024079cb-77ad-9c48-e370-e6e8f2de171b@axentia.se> <9c496531-f7b6-4b9d-dd51-0bfb68ead303@axentia.se> <19d68279-072e-7646-6fdd-8649578229ea@microchip.com> <20180529164911.29820e07@bbrezillon> <20180529171555.19dd723f@bbrezillon> From: Eugen Hristev Message-ID: <1affd186-7f78-8bb0-050e-da82143c2982@microchip.com> Date: Tue, 29 May 2018 18:21:40 +0300 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:52.0) Gecko/20100101 Thunderbird/52.8.0 MIME-Version: 1.0 In-Reply-To: <20180529171555.19dd723f@bbrezillon> Content-Type: text/plain; charset="utf-8"; format=flowed Content-Language: en-US Content-Transfer-Encoding: 7bit Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 29.05.2018 18:15, Boris Brezillon wrote: > On Tue, 29 May 2018 18:01:40 +0300 > Eugen Hristev wrote: > >> [...] >> >> >>> >>> I think you're missing something here. We use the DMA engine in memcpy >>> mode (SRAM -> DRAM), not in device mode (dev -> DRAM or DRAM -> dev). >>> So there's no dmas prop defined in the DT and there should not be. >>> >>> Regards, >>> >>> Boris >>> >> >> Ok, so the memcpy SRAM <-> DRAM will hog the transfer between DRAM and >> LCD if my understanding is correct. That's the DMA that Peter wants to >> disable with his patch ? >> >> Then we can then try to force NFC SRAM DMA channels to use just DDR port >> 1 or 2 for memcpy ? > > You mean the dmaengine? According to "14.1.3 Master to Slave Access" > that's already the case. > > Only DMAC0 can access the NFC SRAM and it's done through DMAC0:IF0, > then access to DDR is going through port DDR port 1 (DMAC0:IF1) or 2 > (DMAC0:IF0). If we can make NFC use port 1 only, then HLCDC could have two ports as master 8 & 9, maybe a better bandwidth. > >> >> I have also received a suggestion to try to increase the porches in >> LCDC_LCDCFG3 . > > Yep, Nicolas suggested something similar. Peter, can you try that? > From mboxrd@z Thu Jan 1 00:00:00 1970 From: eugen.hristev@microchip.com (Eugen Hristev) Date: Tue, 29 May 2018 18:21:40 +0300 Subject: [PATCH] mtd: nand: raw: atmel: add module param to avoid using dma In-Reply-To: <20180529171555.19dd723f@bbrezillon> References: <20180329131054.22506-1-peda@axentia.se> <20180329153322.5e2fc1e7@bbrezillon> <20180329154416.5c1a0013@bbrezillon> <20180402142249.7e076a64@bbrezillon> <20180402212843.164d5d21@bbrezillon> <20180402222020.1d344c14@bbrezillon> <20180403091813.5fb5c18c@bbrezillon> <959d826d-1a98-ca22-acee-a4548427fcd3@microchip.com> <024079cb-77ad-9c48-e370-e6e8f2de171b@axentia.se> <9c496531-f7b6-4b9d-dd51-0bfb68ead303@axentia.se> <19d68279-072e-7646-6fdd-8649578229ea@microchip.com> <20180529164911.29820e07@bbrezillon> <20180529171555.19dd723f@bbrezillon> Message-ID: <1affd186-7f78-8bb0-050e-da82143c2982@microchip.com> To: linux-arm-kernel@lists.infradead.org List-Id: linux-arm-kernel.lists.infradead.org On 29.05.2018 18:15, Boris Brezillon wrote: > On Tue, 29 May 2018 18:01:40 +0300 > Eugen Hristev wrote: > >> [...] >> >> >>> >>> I think you're missing something here. We use the DMA engine in memcpy >>> mode (SRAM -> DRAM), not in device mode (dev -> DRAM or DRAM -> dev). >>> So there's no dmas prop defined in the DT and there should not be. >>> >>> Regards, >>> >>> Boris >>> >> >> Ok, so the memcpy SRAM <-> DRAM will hog the transfer between DRAM and >> LCD if my understanding is correct. That's the DMA that Peter wants to >> disable with his patch ? >> >> Then we can then try to force NFC SRAM DMA channels to use just DDR port >> 1 or 2 for memcpy ? > > You mean the dmaengine? According to "14.1.3 Master to Slave Access" > that's already the case. > > Only DMAC0 can access the NFC SRAM and it's done through DMAC0:IF0, > then access to DDR is going through port DDR port 1 (DMAC0:IF1) or 2 > (DMAC0:IF0). If we can make NFC use port 1 only, then HLCDC could have two ports as master 8 & 9, maybe a better bandwidth. > >> >> I have also received a suggestion to try to increase the porches in >> LCDC_LCDCFG3 . > > Yep, Nicolas suggested something similar. Peter, can you try that? >