From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:45525) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1c4UXK-00040O-Uw for qemu-devel@nongnu.org; Wed, 09 Nov 2016 10:11:39 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1c4UXG-0006J3-2x for qemu-devel@nongnu.org; Wed, 09 Nov 2016 10:11:38 -0500 Received: from mx1.redhat.com ([209.132.183.28]:45656) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1c4UXF-0006IH-Tw for qemu-devel@nongnu.org; Wed, 09 Nov 2016 10:11:34 -0500 References: <20161109145748.27282-1-alex.bennee@linaro.org> From: Paolo Bonzini Message-ID: <1b4e51fd-92c9-d731-4d15-63e330422f20@redhat.com> Date: Wed, 9 Nov 2016 16:11:26 +0100 MIME-Version: 1.0 In-Reply-To: <20161109145748.27282-1-alex.bennee@linaro.org> Content-Type: text/plain; charset=windows-1252 Content-Transfer-Encoding: quoted-printable Subject: Re: [Qemu-devel] [PATCH v6 00/19] Remaining MTTCG Base patches and ARM enablement List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: =?UTF-8?Q?Alex_Benn=c3=a9e?= Cc: qemu-devel@nongnu.org, mttcg@greensocs.com, fred.konrad@greensocs.com, a.rigo@virtualopensystems.com, cota@braap.org, bobby.prani@gmail.com, nikunj@linux.vnet.ibm.com, mark.burton@greensocs.com, jan.kiszka@siemens.com, serge.fdrv@gmail.com, rth@twiddle.net, peter.maydell@linaro.org, claudio.fontana@huawei.com On 09/11/2016 15:57, Alex Benn=E9e wrote: > The one outstanding question is how to deal with the TLB flush > semantics of the various guest architectures. Currently flushes to > other vCPUs will happen at the end of their currently executing > Translation Block which could mean the originating vCPU makes > assumptions about flushes having been completed when they haven't. In > practice this hasn't been a problem and I haven't been able to > construct a test case so far that would fail in such a case. This is > probably because most tear downs of the other vCPU TLBs tend to be > done while the other vCPUs are not doing much. If anyone can come up > with a test case that would fail if this assumption isn't met then > please let me know. Have you tried implementing ARM's DMB semantics correctly? Paolo