From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([208.118.235.92]:49889) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1TPJPz-0004yr-Fk for qemu-devel@nongnu.org; Fri, 19 Oct 2012 16:43:47 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1TPJPx-0006Yk-IF for qemu-devel@nongnu.org; Fri, 19 Oct 2012 16:43:43 -0400 Received: from mx1.redhat.com ([209.132.183.28]:30282) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1TPJPx-0006YM-A1 for qemu-devel@nongnu.org; Fri, 19 Oct 2012 16:43:41 -0400 Date: Fri, 19 Oct 2012 16:43:38 -0400 From: Jason Baron Message-Id: <1b6424bdbc20646537f4ebc8218ffdfac6560cea.1350677362.git.jbaron@redhat.com> In-Reply-To: References: Subject: [Qemu-devel] [PATCH v3 20/26] q35: smbus: Remove PCI_STATUS_SIG_SYSTEM_ERROR and PCI_STATUS_DETECTED_PARITY from w1cmask List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: aliguori@us.ibm.com, juzhang@redhat.com, mst@redhat.com, jan.kiszka@siemens.com, armbru@redhat.com, agraf@suse.de, blauwirbel@gmail.com, yamahata@valinux.co.jp, alex.williamson@redhat.com, kevin@koconnor.net, avi@redhat.com, mkletzan@redhat.com, pbonzini@redhat.com, lcapitulino@redhat.com, afaerber@suse.de, kraxel@redhat.com From: Jan Kiszka Both bits are added to the write-1-to-clear mask by default. As the smbus device does not allow writes at all, we have to remove it from that mask, also to avoid triggering a runtime assertion. Reviewed-by: Paolo Bonzini Signed-off-by: Jan Kiszka Signed-off-by: Jason Baron --- hw/smbus_ich9.c | 4 ++++ 1 files changed, 4 insertions(+), 0 deletions(-) diff --git a/hw/smbus_ich9.c b/hw/smbus_ich9.c index 8c2cd44..e856063 100644 --- a/hw/smbus_ich9.c +++ b/hw/smbus_ich9.c @@ -94,6 +94,10 @@ static int ich9_smbus_initfn(PCIDevice *d) { ICH9SMBState *s = ICH9_SMB_DEVICE(d); + pci_set_word(d->w1cmask + PCI_STATUS, + pci_get_word(d->w1cmask + PCI_STATUS) & + ~(PCI_STATUS_SIG_SYSTEM_ERROR | PCI_STATUS_DETECTED_PARITY)); + /* TODO? D31IP.SMIP in chipset configuration space */ pci_config_set_interrupt_pin(d->config, 0x01); /* interrupt pin 1 */ -- 1.7.1