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([2a02:908:1252:fb60:cd07:2759:3eec:1d00]) by smtp.gmail.com with ESMTPSA id m4sm2422442ljp.9.2021.06.01.23.53.24 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Tue, 01 Jun 2021 23:53:24 -0700 (PDT) Subject: Re: [PATCH 1/4] drm/amdkfd: Add flush-type parameter to kfd_flush_tlb To: Eric Huang , amd-gfx@lists.freedesktop.org, "Kuehling, Felix" , "Yang, Philip" References: <20210601225907.749049-1-jinhuieric.huang@amd.com> From: =?UTF-8?Q?Christian_K=c3=b6nig?= Message-ID: <1b688ac5-e4cd-5c8b-7972-1f120186b502@gmail.com> Date: Wed, 2 Jun 2021 08:53:23 +0200 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:78.0) Gecko/20100101 Thunderbird/78.8.1 MIME-Version: 1.0 In-Reply-To: <20210601225907.749049-1-jinhuieric.huang@amd.com> Content-Language: en-US X-BeenThere: amd-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Discussion list for AMD gfx List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Transfer-Encoding: 7bit Content-Type: text/plain; charset="us-ascii"; Format="flowed" Errors-To: amd-gfx-bounces@lists.freedesktop.org Sender: "amd-gfx" Mostly a question for Felix and Philip: I've been thinking for a bit about how that case happens in the first place? I mean if we have a PDE which points to PTEs and then switch that into a 2MiB PTE then why wasn't that range invalidated before? In other words when the PDE points to the PTEs we should have had an unmap operation on that range before which should have invalidated the TLB. Regards, Christian. Am 02.06.21 um 00:59 schrieb Eric Huang: > It is to provide more tlb flush types opotion for different > case scenario. > > Signed-off-by: Eric Huang > --- > drivers/gpu/drm/amd/amdkfd/kfd_chardev.c | 2 +- > drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c | 6 +++--- > drivers/gpu/drm/amd/amdkfd/kfd_priv.h | 2 +- > drivers/gpu/drm/amd/amdkfd/kfd_process.c | 4 ++-- > 4 files changed, 7 insertions(+), 7 deletions(-) > > diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c b/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c > index 960913a35ee4..4da8aff3df27 100644 > --- a/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c > +++ b/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c > @@ -1666,7 +1666,7 @@ static int kfd_ioctl_map_memory_to_gpu(struct file *filep, > if (WARN_ON_ONCE(!peer_pdd)) > continue; > if (!amdgpu_read_lock(peer->ddev, true)) { > - kfd_flush_tlb(peer_pdd); > + kfd_flush_tlb(peer_pdd, TLB_FLUSH_LEGACY); > amdgpu_read_unlock(peer->ddev); > } > } > diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c b/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c > index 2bd621eee4e0..904b8178c1d7 100644 > --- a/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c > +++ b/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c > @@ -278,7 +278,7 @@ static int allocate_vmid(struct device_queue_manager *dqm, > qpd->vmid, > qpd->page_table_base); > /* invalidate the VM context after pasid and vmid mapping is set up */ > - kfd_flush_tlb(qpd_to_pdd(qpd)); > + kfd_flush_tlb(qpd_to_pdd(qpd), TLB_FLUSH_LEGACY); > > if (dqm->dev->kfd2kgd->set_scratch_backing_va) > dqm->dev->kfd2kgd->set_scratch_backing_va(dqm->dev->kgd, > @@ -314,7 +314,7 @@ static void deallocate_vmid(struct device_queue_manager *dqm, > if (flush_texture_cache_nocpsch(q->device, qpd)) > pr_err("Failed to flush TC\n"); > > - kfd_flush_tlb(qpd_to_pdd(qpd)); > + kfd_flush_tlb(qpd_to_pdd(qpd), TLB_FLUSH_LEGACY); > > /* Release the vmid mapping */ > set_pasid_vmid_mapping(dqm, 0, qpd->vmid); > @@ -885,7 +885,7 @@ static int restore_process_queues_nocpsch(struct device_queue_manager *dqm, > dqm->dev->kgd, > qpd->vmid, > qpd->page_table_base); > - kfd_flush_tlb(pdd); > + kfd_flush_tlb(pdd, TLB_FLUSH_LEGACY); > } > > /* Take a safe reference to the mm_struct, which may otherwise > diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_priv.h b/drivers/gpu/drm/amd/amdkfd/kfd_priv.h > index ecdd5e782b81..edce3ecf207d 100644 > --- a/drivers/gpu/drm/amd/amdkfd/kfd_priv.h > +++ b/drivers/gpu/drm/amd/amdkfd/kfd_priv.h > @@ -1338,7 +1338,7 @@ void kfd_signal_reset_event(struct kfd_dev *dev); > > void kfd_signal_poison_consumed_event(struct kfd_dev *dev, u32 pasid); > > -void kfd_flush_tlb(struct kfd_process_device *pdd); > +void kfd_flush_tlb(struct kfd_process_device *pdd, enum TLB_FLUSH_TYPE type); > > int dbgdev_wave_reset_wavefronts(struct kfd_dev *dev, struct kfd_process *p); > > diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_process.c b/drivers/gpu/drm/amd/amdkfd/kfd_process.c > index 3995002c582b..72741f6579d3 100644 > --- a/drivers/gpu/drm/amd/amdkfd/kfd_process.c > +++ b/drivers/gpu/drm/amd/amdkfd/kfd_process.c > @@ -2159,7 +2159,7 @@ int kfd_reserved_mem_mmap(struct kfd_dev *dev, struct kfd_process *process, > KFD_CWSR_TBA_TMA_SIZE, vma->vm_page_prot); > } > > -void kfd_flush_tlb(struct kfd_process_device *pdd) > +void kfd_flush_tlb(struct kfd_process_device *pdd, enum TLB_FLUSH_TYPE type) > { > struct kfd_dev *dev = pdd->dev; > > @@ -2172,7 +2172,7 @@ void kfd_flush_tlb(struct kfd_process_device *pdd) > pdd->qpd.vmid); > } else { > amdgpu_amdkfd_flush_gpu_tlb_pasid(dev->kgd, > - pdd->process->pasid, TLB_FLUSH_LEGACY); > + pdd->process->pasid, type); > } > } > _______________________________________________ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx