From mboxrd@z Thu Jan 1 00:00:00 1970 From: Vivek Gautam Subject: Re: [PATCH 4/5] iommu/arm-smmu: Make way to add Qcom's smmu-500 errata handling Date: Tue, 28 Aug 2018 12:29:02 +0530 Message-ID: <1b73ab8e-a5fa-e917-cd78-1e0fafe8d00f@codeaurora.org> References: <20180814105528.20592-1-vivek.gautam@codeaurora.org> <20180814105528.20592-5-vivek.gautam@codeaurora.org> Mime-Version: 1.0 Content-Type: text/plain; charset="utf-8"; Format="flowed" Content-Transfer-Encoding: base64 Return-path: In-Reply-To: Content-Language: en-US List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: iommu-bounces-cunTk1MwBs9QetFLy7KEm3xJsTq8ys+cHZ5vskTnxNA@public.gmane.org Errors-To: iommu-bounces-cunTk1MwBs9QetFLy7KEm3xJsTq8ys+cHZ5vskTnxNA@public.gmane.org To: Robin Murphy , joro-zLv9SwRftAIdnm+yROfE0A@public.gmane.org, andy.gross-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org, will.deacon-5wv7dgnIgG8@public.gmane.org, bjorn.andersson-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org, iommu-cunTk1MwBs9QetFLy7KEm3xJsTq8ys+cHZ5vskTnxNA@public.gmane.org Cc: mark.rutland-5wv7dgnIgG8@public.gmane.org, linux-arm-msm-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, linux-kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, swboyd-F7+t8E8rja9g9hUCZPvPmw@public.gmane.org, david.brown-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org, linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org List-Id: linux-arm-msm@vger.kernel.org SGkgUm9iaW4sCgoKT24gOC8xNC8yMDE4IDEwOjI5IFBNLCBSb2JpbiBNdXJwaHkgd3JvdGU6Cj4g T24gMTQvMDgvMTggMTE6NTUsIFZpdmVrIEdhdXRhbSB3cm90ZToKPj4gQ2xlYW51cCB0byByZS11 c2Ugc29tZSBvZiB0aGUgc3R1ZmYKPj4KPj4gU2lnbmVkLW9mZi1ieTogVml2ZWsgR2F1dGFtIDx2 aXZlay5nYXV0YW1AY29kZWF1cm9yYS5vcmc+Cj4+IC0tLQo+PiDCoCBkcml2ZXJzL2lvbW11L2Fy bS1zbW11LmMgfCAzMiArKysrKysrKysrKysrKysrKysrKysrKysrLS0tLS0tLQo+PiDCoCAxIGZp bGUgY2hhbmdlZCwgMjUgaW5zZXJ0aW9ucygrKSwgNyBkZWxldGlvbnMoLSkKPgo+IEkgdGhpbmsg dGhlIG92ZXJhbGwgZGlmZnN0YXQgd291bGQgYmUgYW4gYXdmdWwgbG90IHNtYWxsZXIgaWYgdGhl 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d=codeaurora.org; s=default; t=1535439549; bh=rYHGFQua5yUKkHi3ur7wqg3hOvWel1YiSJuqmXJx+cU=; h=Subject:To:Cc:References:From:Date:In-Reply-To:From; b=F1GvUkaaH6her/M+Y2pTOQ+j6zoVW3rgS2KxU0Il+z7i+CBhRUKlyXkp/OMMJfdyy eAArHZek+SsA5zom4iA4tQgsMoDEdH3i2qtqVvsc2L+ebNtwUKZBUeju00GMrqPxJs y5rvl4jkO0Y6ahrVhVC+0VTs3qDjvXfgJjV0rqCw= Received: from [10.79.40.134] (blr-bdr-fw-01_globalnat_allzones-outside.qualcomm.com [103.229.18.19]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) (Authenticated sender: vivek.gautam@smtp.codeaurora.org) by smtp.codeaurora.org (Postfix) with ESMTPSA id B49A56021C; Tue, 28 Aug 2018 06:59:04 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=codeaurora.org; s=default; t=1535439548; bh=rYHGFQua5yUKkHi3ur7wqg3hOvWel1YiSJuqmXJx+cU=; h=Subject:To:Cc:References:From:Date:In-Reply-To:From; b=N9rYuBI07rC0aIyN7oexKusQlW+/6WM/RYHIhUyvo3GeSRD/O/8jQZLvPavV/VDWR mdIzCSwUhYOc6uOQtGXEvHLFvblMqUh2qQb4g4ibAPjc/D0VOVHUr7uDwBrEcTyN2W 67wO1q+D2I55abkTBUbE1bEZl2qyYn8UXnz0z5qE= DMARC-Filter: OpenDMARC Filter v1.3.2 smtp.codeaurora.org B49A56021C Authentication-Results: pdx-caf-mail.web.codeaurora.org; dmarc=none (p=none dis=none) header.from=codeaurora.org Authentication-Results: pdx-caf-mail.web.codeaurora.org; spf=none smtp.mailfrom=vivek.gautam@codeaurora.org Subject: Re: [PATCH 4/5] iommu/arm-smmu: Make way to add Qcom's smmu-500 errata handling To: Robin Murphy , joro@8bytes.org, andy.gross@linaro.org, will.deacon@arm.com, bjorn.andersson@linaro.org, iommu@lists.linux-foundation.org Cc: mark.rutland@arm.com, david.brown@linaro.org, tfiga@chromium.org, swboyd@chromium.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-arm-kernel@lists.infradead.org References: <20180814105528.20592-1-vivek.gautam@codeaurora.org> <20180814105528.20592-5-vivek.gautam@codeaurora.org> From: Vivek Gautam Message-ID: <1b73ab8e-a5fa-e917-cd78-1e0fafe8d00f@codeaurora.org> Date: Tue, 28 Aug 2018 12:29:02 +0530 User-Agent: Mozilla/5.0 (Windows NT 6.1; WOW64; rv:52.0) Gecko/20100101 Thunderbird/52.9.1 MIME-Version: 1.0 In-Reply-To: Content-Type: text/plain; charset=utf-8; format=flowed Content-Transfer-Encoding: 8bit Content-Language: en-US Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Hi Robin, On 8/14/2018 10:29 PM, Robin Murphy wrote: > On 14/08/18 11:55, Vivek Gautam wrote: >> Cleanup to re-use some of the stuff >> >> Signed-off-by: Vivek Gautam >> --- >>   drivers/iommu/arm-smmu.c | 32 +++++++++++++++++++++++++------- >>   1 file changed, 25 insertions(+), 7 deletions(-) > > I think the overall diffstat would be an awful lot smaller if the > erratum workaround just has its own readl_poll_timeout() as it does in > the vendor kernel. The burst-polling loop is for minimising latency in > high-throughput situations, and if you're in a workaround which has to > lock *every* register write and issue two firmware calls around each > sync I think you're already well out of that game. Sorry for the delayed response. I was on vacation. I will fix this in my next version by adding the separate read_poll_timeout() for the erratum WA. > >> diff --git a/drivers/iommu/arm-smmu.c b/drivers/iommu/arm-smmu.c >> index 32e86df80428..75c146751c87 100644 >> --- a/drivers/iommu/arm-smmu.c >> +++ b/drivers/iommu/arm-smmu.c >> @@ -391,21 +391,31 @@ static void __arm_smmu_free_bitmap(unsigned >> long *map, int idx) >>       clear_bit(idx, map); >>   } >>   -/* Wait for any pending TLB invalidations to complete */ >> -static void __arm_smmu_tlb_sync(struct arm_smmu_device *smmu, >> -                void __iomem *sync, void __iomem *status) >> +static int __arm_smmu_tlb_sync_wait(void __iomem *status) >>   { >>       unsigned int spin_cnt, delay; >>   -    writel_relaxed(0, sync); >>       for (delay = 1; delay < TLB_LOOP_TIMEOUT; delay *= 2) { >>           for (spin_cnt = TLB_SPIN_COUNT; spin_cnt > 0; spin_cnt--) { >>               if (!(readl_relaxed(status) & sTLBGSTATUS_GSACTIVE)) >> -                return; >> +                return 0; >>               cpu_relax(); >>           } >>           udelay(delay); >>       } >> + >> +    return -EBUSY; >> +} >> + >> +/* Wait for any pending TLB invalidations to complete */ >> +static void __arm_smmu_tlb_sync(struct arm_smmu_device *smmu, >> +                void __iomem *sync, void __iomem *status) >> +{ >> +    writel_relaxed(0, sync); >> + >> +    if (!__arm_smmu_tlb_sync_wait(status)) >> +        return; >> + >>       dev_err_ratelimited(smmu->dev, >>                   "TLB sync timed out -- SMMU may be deadlocked\n"); >>   } >> @@ -461,8 +471,9 @@ static void arm_smmu_tlb_inv_context_s2(void >> *cookie) >>       arm_smmu_tlb_sync_global(smmu); >>   } >>   -static void arm_smmu_tlb_inv_range_nosync(unsigned long iova, >> size_t size, >> -                      size_t granule, bool leaf, void *cookie) >> +static void __arm_smmu_tlb_inv_range_nosync(unsigned long iova, >> size_t size, >> +                        size_t granule, bool leaf, >> +                        void *cookie) >>   { >>       struct arm_smmu_domain *smmu_domain = cookie; >>       struct arm_smmu_cfg *cfg = &smmu_domain->cfg; >> @@ -498,6 +509,13 @@ static void >> arm_smmu_tlb_inv_range_nosync(unsigned long iova, size_t size, >>       } >>   } >>   +static void arm_smmu_tlb_inv_range_nosync(unsigned long iova, >> size_t size, >> +                      size_t granule, bool leaf, >> +                      void *cookie) >> +{ >> +    __arm_smmu_tlb_inv_range_nosync(iova, size, granule, leaf, cookie); >> +} >> + > > AFAICS even after patch #5 this does absolutely nothing except make > the code needlessly harder to read :( Sure, I will rather call arm_smmu_tlb_inv_range_nosync() from qcom_errata_tlb_inv_range_nosync() then make this change. Thanks for the review. Best regards Vivek > > Robin. > >>   /* >>    * On MMU-401 at least, the cost of firing off multiple TLBIVMIDs >> appears >>    * almost negligible, but the benefit of getting the first one in >> as far ahead >> From mboxrd@z Thu Jan 1 00:00:00 1970 From: vivek.gautam@codeaurora.org (Vivek Gautam) Date: Tue, 28 Aug 2018 12:29:02 +0530 Subject: [PATCH 4/5] iommu/arm-smmu: Make way to add Qcom's smmu-500 errata handling In-Reply-To: References: <20180814105528.20592-1-vivek.gautam@codeaurora.org> <20180814105528.20592-5-vivek.gautam@codeaurora.org> Message-ID: <1b73ab8e-a5fa-e917-cd78-1e0fafe8d00f@codeaurora.org> To: linux-arm-kernel@lists.infradead.org List-Id: linux-arm-kernel.lists.infradead.org Hi Robin, On 8/14/2018 10:29 PM, Robin Murphy wrote: > On 14/08/18 11:55, Vivek Gautam wrote: >> Cleanup to re-use some of the stuff >> >> Signed-off-by: Vivek Gautam >> --- >> ? drivers/iommu/arm-smmu.c | 32 +++++++++++++++++++++++++------- >> ? 1 file changed, 25 insertions(+), 7 deletions(-) > > I think the overall diffstat would be an awful lot smaller if the > erratum workaround just has its own readl_poll_timeout() as it does in > the vendor kernel. The burst-polling loop is for minimising latency in > high-throughput situations, and if you're in a workaround which has to > lock *every* register write and issue two firmware calls around each > sync I think you're already well out of that game. Sorry for the delayed response. I was on vacation. I will fix this in my next version by adding the separate read_poll_timeout() for the erratum WA. > >> diff --git a/drivers/iommu/arm-smmu.c b/drivers/iommu/arm-smmu.c >> index 32e86df80428..75c146751c87 100644 >> --- a/drivers/iommu/arm-smmu.c >> +++ b/drivers/iommu/arm-smmu.c >> @@ -391,21 +391,31 @@ static void __arm_smmu_free_bitmap(unsigned >> long *map, int idx) >> ????? clear_bit(idx, map); >> ? } >> ? -/* Wait for any pending TLB invalidations to complete */ >> -static void __arm_smmu_tlb_sync(struct arm_smmu_device *smmu, >> -??????????????? void __iomem *sync, void __iomem *status) >> +static int __arm_smmu_tlb_sync_wait(void __iomem *status) >> ? { >> ????? unsigned int spin_cnt, delay; >> ? -??? writel_relaxed(0, sync); >> ????? for (delay = 1; delay < TLB_LOOP_TIMEOUT; delay *= 2) { >> ????????? for (spin_cnt = TLB_SPIN_COUNT; spin_cnt > 0; spin_cnt--) { >> ????????????? if (!(readl_relaxed(status) & sTLBGSTATUS_GSACTIVE)) >> -??????????????? return; >> +??????????????? return 0; >> ????????????? cpu_relax(); >> ????????? } >> ????????? udelay(delay); >> ????? } >> + >> +??? return -EBUSY; >> +} >> + >> +/* Wait for any pending TLB invalidations to complete */ >> +static void __arm_smmu_tlb_sync(struct arm_smmu_device *smmu, >> +??????????????? void __iomem *sync, void __iomem *status) >> +{ >> +??? writel_relaxed(0, sync); >> + >> +??? if (!__arm_smmu_tlb_sync_wait(status)) >> +??????? return; >> + >> ????? dev_err_ratelimited(smmu->dev, >> ????????????????? "TLB sync timed out -- SMMU may be deadlocked\n"); >> ? } >> @@ -461,8 +471,9 @@ static void arm_smmu_tlb_inv_context_s2(void >> *cookie) >> ????? arm_smmu_tlb_sync_global(smmu); >> ? } >> ? -static void arm_smmu_tlb_inv_range_nosync(unsigned long iova, >> size_t size, >> -????????????????????? size_t granule, bool leaf, void *cookie) >> +static void __arm_smmu_tlb_inv_range_nosync(unsigned long iova, >> size_t size, >> +??????????????????????? size_t granule, bool leaf, >> +??????????????????????? void *cookie) >> ? { >> ????? struct arm_smmu_domain *smmu_domain = cookie; >> ????? struct arm_smmu_cfg *cfg = &smmu_domain->cfg; >> @@ -498,6 +509,13 @@ static void >> arm_smmu_tlb_inv_range_nosync(unsigned long iova, size_t size, >> ????? } >> ? } >> ? +static void arm_smmu_tlb_inv_range_nosync(unsigned long iova, >> size_t size, >> +????????????????????? size_t granule, bool leaf, >> +????????????????????? void *cookie) >> +{ >> +??? __arm_smmu_tlb_inv_range_nosync(iova, size, granule, leaf, cookie); >> +} >> + > > AFAICS even after patch #5 this does absolutely nothing except make > the code needlessly harder to read :( Sure, I will rather call arm_smmu_tlb_inv_range_nosync() from qcom_errata_tlb_inv_range_nosync() then make this change. Thanks for the review. Best regards Vivek > > Robin. > >> ? /* >> ?? * On MMU-401 at least, the cost of firing off multiple TLBIVMIDs >> appears >> ?? * almost negligible, but the benefit of getting the first one in >> as far ahead >>