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[188.155.201.27]) by smtp.gmail.com with ESMTPSA id jt8-20020a170906ca0800b006df9b29eaf1sm13193117ejb.8.2022.04.12.10.06.51 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Tue, 12 Apr 2022 10:06:51 -0700 (PDT) Message-ID: <1c455b6e-0009-6f8b-15c8-2a352479c5f2@linaro.org> Date: Tue, 12 Apr 2022 19:06:50 +0200 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:91.0) Gecko/20100101 Thunderbird/91.7.0 Subject: Re: [PATCH 1/2] dt-bindings: timer: Update TI timer to yaml Content-Language: en-US To: Tony Lindgren , Rob Herring , Krzysztof Kozlowski Cc: devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-omap@vger.kernel.org, Daniel Lezcano , Keerthy , Nishanth Menon , Vignesh Raghavendra References: <20220412131644.59195-1-tony@atomide.com> <20220412131644.59195-2-tony@atomide.com> From: Krzysztof Kozlowski In-Reply-To: <20220412131644.59195-2-tony@atomide.com> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org On 12/04/2022 15:16, Tony Lindgren wrote: > Let's update the TI timer binding to use yaml. As this binding is specific > to the TI dual-mode timers also known as dm-timers, let's use file name > ti,timer-dm.yaml to avoid confusion with other timers. > > We also correct the issue with the old binding that was out of date for > several properties. > > The am43 related timers are undocumented, but compatible with the am3 > timers. Let's add the am43 timers too. > > The dm814 and dm816 timers are missing, let's add them. > > Some timers on some SoCs are dual mapped, like the ABE timers on omap4 > and 5. The reg property maxItems must be updated to 2. > > The timer clocks can be managed by the parent interconnect target module > with no clocks assigned for the timer node. And in some cases the SoC may > need to configure additional clocks for the timer in addition to the > functional clock. > > The clock names are optional and not specific to the comptible property. > For example, dra7 timers on l3 interconnect do not need clock-names,while > the timers on dra7 l4 interconnect need them with both being compatible > with ti,omap5430-timer. > > Cc: Daniel Lezcano > Cc: Keerthy > Cc: Nishanth Menon > Cc: Vignesh Raghavendra > Signed-off-by: Tony Lindgren > --- > .../bindings/pwm/pwm-omap-dmtimer.txt | 2 +- > .../bindings/timer/ti,timer-dm.yaml | 161 ++++++++++++++++++ > .../devicetree/bindings/timer/ti,timer.txt | 44 ----- > 3 files changed, 162 insertions(+), 45 deletions(-) > create mode 100644 Documentation/devicetree/bindings/timer/ti,timer-dm.yaml > delete mode 100644 Documentation/devicetree/bindings/timer/ti,timer.txt > > diff --git a/Documentation/devicetree/bindings/pwm/pwm-omap-dmtimer.txt b/Documentation/devicetree/bindings/pwm/pwm-omap-dmtimer.txt > --- a/Documentation/devicetree/bindings/pwm/pwm-omap-dmtimer.txt > +++ b/Documentation/devicetree/bindings/pwm/pwm-omap-dmtimer.txt > @@ -2,7 +2,7 @@ > > Required properties: > - compatible: Shall contain "ti,omap-dmtimer-pwm". > -- ti,timers: phandle to PWM capable OMAP timer. See timer/ti,timer.txt for info > +- ti,timers: phandle to PWM capable OMAP timer. See timer/ti,timer-dm.yaml for info > about these timers. > - #pwm-cells: Should be 3. See pwm.yaml in this directory for a description of > the cells format. > diff --git a/Documentation/devicetree/bindings/timer/ti,timer-dm.yaml b/Documentation/devicetree/bindings/timer/ti,timer-dm.yaml > new file mode 100644 > --- /dev/null > +++ b/Documentation/devicetree/bindings/timer/ti,timer-dm.yaml > @@ -0,0 +1,161 @@ > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) > +%YAML 1.2 > +--- > +$id: http://devicetree.org/schemas/timer/ti,timer-dm.yaml# > +$schema: http://devicetree.org/meta-schemas/core.yaml# > + > +title: TI dual-mode timer > + > +maintainers: > + - Tony Lindgren > + > +description: | > + The TI dual-mode timer is a general purpose timer with PWM capabilities. > + > +properties: > + compatible: > + oneOf: > + - items: > + - enum: > + - ti,am335x-timer > + - ti,am335x-timer-1ms > + - ti,dm814-timer > + - ti,dm816-timer > + - ti,omap2420-timer > + - ti,omap3430-timer > + - ti,omap4430-timer > + - ti,omap5430-timer > + - items: > + - const: ti,am4372-timer > + - const: ti,am335x-timer > + - items: > + - const: ti,am4372-timer-1ms > + - const: ti,am335x-timer-1ms > + > + reg: > + minItems: 1 > + maxItems: 2 > + > + clocks: > + minItems: 1 > + maxItems: 2 > + > + clock-names: > + minItems: 1 > + maxItems: 2 > + > + interrupts: > + description: > + Interrupt if available. The timer PWM features may be usable > + in a limited way even without interrupts. > + maxItems: 1 > + > + ti,timer-alwon: > + description: > + Timer is always enabled when the SoC is powered. Note that some SoCs like > + am335x can suspend to PM coprocessor RTC only mode and in that case the > + SoC power is cut including timers. > + type: boolean > + > + ti,timer-dsp: > + description: > + Timer is routable to the DSP in addition to the operating system. > + type: boolean > + > + ti,timer-pwm: > + description: > + Timer has been wired for PWM capability. > + type: boolean > + > + ti,timer-secure: > + description: > + Timer access has been limited to secure mode only. > + type: boolean > + > + ti,hwmods: > + description: > + Name of the HWMOD associated with timer. This is for legacy > + omap2/3 platforms only. > + $ref: /schemas/types.yaml#/definitions/string > + deprecated: true > + > +required: > + - compatible > + - reg > + - interrupts > + > +additionalProperties: false > + > +allOf: > + - if: > + properties: > + compatible: > + contains: > + enum: > + - ti,omap3430-timer > + - ti,omap4430-timer > + - ti,omap5430-timer > + then: > + properties: > + reg: > + oneOf: > + - items: > + - description: IO address > + - items: > + - description: CPU to L4 ABE IO address > + - description: L3 to L4 ABE IO address > + clocks: > + oneOf: > + - items: > + - description: Functional clock > + - items: > + - description: Functional clock > + - description: System clock I think this can be made simpler, without oneOf: clocks: items: - description: Functional clock - description: System clock minItems: 1 and similar for clock-names. > + clock-names: > + oneOf: > + - items: > + - const: fck > + - items: > + - const: fck > + - const: timer_sys_ck > + else: > + properties: > + reg: > + items: > + - description: IO address > + clocks: > + items: > + - description: Functional clock > + clock-names: > + items: > + - const: fck Hmmm, in your previous version I had impression that first clock is not the same on every flavor. Now it looks the same, so clocks you could simplify even more: 1. Define full list in main properties (not in allOf) with minItems:1 2. Use maxItems:1, for this "else:" case. This could greatly reduce amount of code you need and keep the actual definition of clocks in main properties (not in allOf; allOf are only to constrain it). Best regards, Krzysztof From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id F3718C433EF for ; Tue, 12 Apr 2022 17:08:10 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:In-Reply-To:From:References:Cc:To: Subject:MIME-Version:Date:Message-ID:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=79sT+PjkkfZtXarQLozg9gte4uEjOgTj9UfM+lIivCI=; b=eE3D+KwOulMDdt r5Q4KVB7MIm2cgNt6oNSYaduYTKgH4iHcx1OGup1uiliqvnzEKI9X9qi+hhrVN4JHvG/vtmbYVkZW hTIY+4o12sMlU5r1kEk9CIUHfPVHEwRJiUJX4VW7zEOoSbs7yycrg2HijcasH8ZHZaGfan9Olowg8 tJbR2m9mo2Sx0R5P2c86pP/ul7Ou34bbIMWXiN8KIuObR+Ywr2ZcmzPHn0+u14OCkgv1176gSCubE DkKWZL14SQ+6PhflhADd4dElRREIHyig0eM9QQzZvzywNdEr+qGDd2ccnyWnxEMdG8g+mPJ4rp1gk L27yR1VaMYBcd8CZSORA==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1neJym-00FAiw-BB; Tue, 12 Apr 2022 17:07:00 +0000 Received: from mail-ed1-x52b.google.com ([2a00:1450:4864:20::52b]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1neJyi-00FAhe-IE for linux-arm-kernel@lists.infradead.org; Tue, 12 Apr 2022 17:06:58 +0000 Received: by mail-ed1-x52b.google.com with SMTP id v4so9634338edl.7 for ; Tue, 12 Apr 2022 10:06:53 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=message-id:date:mime-version:user-agent:subject:content-language:to :cc:references:from:in-reply-to:content-transfer-encoding; bh=raAfMnfaujy89EROt6olDuVb61IfOgxmWloOA8zYdSc=; b=ELgABCdoXxbB4A1nHTqsqvRAfOeSH2V02z4cWqlIXeTjWlmMPVrzehBo2TS2Oc0blZ E9nxqEulOyevAIZEAwD0bvvgVQjxNJwOiZ0FJygqyscuhDM03ZUQG5c7Hyh6aRBaQI69 FgMcUwT8ohJpIeA4nuMZal2fcI6qJIQysYxpjbSjJUvFnosGA5RgqDh76PZ6PKzQbP+a 71C+5IC5rUCnQ4VDgFCobr8rlBANbI516HmintavSbcvRbZQtCsfJbGNLN7Oer/p9dig OsazMkPoxXtA/zO2Wg5uZhN13ZCVM0pHr/bCD6v9hZUJZVdjZq4TrbS/4Vn0RTLUBjfW SnHw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:message-id:date:mime-version:user-agent:subject :content-language:to:cc:references:from:in-reply-to :content-transfer-encoding; bh=raAfMnfaujy89EROt6olDuVb61IfOgxmWloOA8zYdSc=; b=1dr3GQXr6p5FaWr5D+i4t0EpBbdkzatyneCbq5eHQOTrfzlzE3o6B1+OjzF93hzvPl bk9mbqeP8BOp0fiALbSSGAO0NjAWqAIyH6rNlbTH5/jfWzi6qUTD0+KpNUnvMKe1JJd4 cGokODPucMhlx33A0CTd2Zg12LxBXxt2nCbZ0z7UmwMCIubzHrndSXjQsGdmSqLh8iFX OjJ+798GcrWbwAGCP5Gh2Bi+3x2wra7rNAPynNSn4NyP6TdJWeuovHZq2Lyj9Aw4sM8N rkLDrJJnnbTLuNqbaHt5zHXJ0v+MvxFONoE9oJMjNkBhsD7EkhUJ5G9KmPcY/1szI1QL gipw== X-Gm-Message-State: AOAM530ZzXicroHyT+aCGJ1l9cH7bjZiOWII6mJBsgyp7bwepWsocAsZ 0Vmr7QeG95Q7X4dQsmotWEElDA== X-Google-Smtp-Source: ABdhPJwHR9sNZxYXaGCKigm/l0SZUbKWRM44zmXJ4Y5xiGe48Qr+Xe62j1kJ/qk4naQMzzPJIpjVQw== X-Received: by 2002:a50:fb03:0:b0:41d:8d3f:9427 with SMTP id d3-20020a50fb03000000b0041d8d3f9427mr5849088edq.263.1649783211989; Tue, 12 Apr 2022 10:06:51 -0700 (PDT) Received: from [192.168.0.198] (xdsl-188-155-201-27.adslplus.ch. [188.155.201.27]) by smtp.gmail.com with ESMTPSA id jt8-20020a170906ca0800b006df9b29eaf1sm13193117ejb.8.2022.04.12.10.06.51 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Tue, 12 Apr 2022 10:06:51 -0700 (PDT) Message-ID: <1c455b6e-0009-6f8b-15c8-2a352479c5f2@linaro.org> Date: Tue, 12 Apr 2022 19:06:50 +0200 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:91.0) Gecko/20100101 Thunderbird/91.7.0 Subject: Re: [PATCH 1/2] dt-bindings: timer: Update TI timer to yaml Content-Language: en-US To: Tony Lindgren , Rob Herring , Krzysztof Kozlowski Cc: devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-omap@vger.kernel.org, Daniel Lezcano , Keerthy , Nishanth Menon , Vignesh Raghavendra References: <20220412131644.59195-1-tony@atomide.com> <20220412131644.59195-2-tony@atomide.com> From: Krzysztof Kozlowski In-Reply-To: <20220412131644.59195-2-tony@atomide.com> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220412_100656_618077_69CA107E X-CRM114-Status: GOOD ( 35.31 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On 12/04/2022 15:16, Tony Lindgren wrote: > Let's update the TI timer binding to use yaml. As this binding is specific > to the TI dual-mode timers also known as dm-timers, let's use file name > ti,timer-dm.yaml to avoid confusion with other timers. > > We also correct the issue with the old binding that was out of date for > several properties. > > The am43 related timers are undocumented, but compatible with the am3 > timers. Let's add the am43 timers too. > > The dm814 and dm816 timers are missing, let's add them. > > Some timers on some SoCs are dual mapped, like the ABE timers on omap4 > and 5. The reg property maxItems must be updated to 2. > > The timer clocks can be managed by the parent interconnect target module > with no clocks assigned for the timer node. And in some cases the SoC may > need to configure additional clocks for the timer in addition to the > functional clock. > > The clock names are optional and not specific to the comptible property. > For example, dra7 timers on l3 interconnect do not need clock-names,while > the timers on dra7 l4 interconnect need them with both being compatible > with ti,omap5430-timer. > > Cc: Daniel Lezcano > Cc: Keerthy > Cc: Nishanth Menon > Cc: Vignesh Raghavendra > Signed-off-by: Tony Lindgren > --- > .../bindings/pwm/pwm-omap-dmtimer.txt | 2 +- > .../bindings/timer/ti,timer-dm.yaml | 161 ++++++++++++++++++ > .../devicetree/bindings/timer/ti,timer.txt | 44 ----- > 3 files changed, 162 insertions(+), 45 deletions(-) > create mode 100644 Documentation/devicetree/bindings/timer/ti,timer-dm.yaml > delete mode 100644 Documentation/devicetree/bindings/timer/ti,timer.txt > > diff --git a/Documentation/devicetree/bindings/pwm/pwm-omap-dmtimer.txt b/Documentation/devicetree/bindings/pwm/pwm-omap-dmtimer.txt > --- a/Documentation/devicetree/bindings/pwm/pwm-omap-dmtimer.txt > +++ b/Documentation/devicetree/bindings/pwm/pwm-omap-dmtimer.txt > @@ -2,7 +2,7 @@ > > Required properties: > - compatible: Shall contain "ti,omap-dmtimer-pwm". > -- ti,timers: phandle to PWM capable OMAP timer. See timer/ti,timer.txt for info > +- ti,timers: phandle to PWM capable OMAP timer. See timer/ti,timer-dm.yaml for info > about these timers. > - #pwm-cells: Should be 3. See pwm.yaml in this directory for a description of > the cells format. > diff --git a/Documentation/devicetree/bindings/timer/ti,timer-dm.yaml b/Documentation/devicetree/bindings/timer/ti,timer-dm.yaml > new file mode 100644 > --- /dev/null > +++ b/Documentation/devicetree/bindings/timer/ti,timer-dm.yaml > @@ -0,0 +1,161 @@ > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) > +%YAML 1.2 > +--- > +$id: http://devicetree.org/schemas/timer/ti,timer-dm.yaml# > +$schema: http://devicetree.org/meta-schemas/core.yaml# > + > +title: TI dual-mode timer > + > +maintainers: > + - Tony Lindgren > + > +description: | > + The TI dual-mode timer is a general purpose timer with PWM capabilities. > + > +properties: > + compatible: > + oneOf: > + - items: > + - enum: > + - ti,am335x-timer > + - ti,am335x-timer-1ms > + - ti,dm814-timer > + - ti,dm816-timer > + - ti,omap2420-timer > + - ti,omap3430-timer > + - ti,omap4430-timer > + - ti,omap5430-timer > + - items: > + - const: ti,am4372-timer > + - const: ti,am335x-timer > + - items: > + - const: ti,am4372-timer-1ms > + - const: ti,am335x-timer-1ms > + > + reg: > + minItems: 1 > + maxItems: 2 > + > + clocks: > + minItems: 1 > + maxItems: 2 > + > + clock-names: > + minItems: 1 > + maxItems: 2 > + > + interrupts: > + description: > + Interrupt if available. The timer PWM features may be usable > + in a limited way even without interrupts. > + maxItems: 1 > + > + ti,timer-alwon: > + description: > + Timer is always enabled when the SoC is powered. Note that some SoCs like > + am335x can suspend to PM coprocessor RTC only mode and in that case the > + SoC power is cut including timers. > + type: boolean > + > + ti,timer-dsp: > + description: > + Timer is routable to the DSP in addition to the operating system. > + type: boolean > + > + ti,timer-pwm: > + description: > + Timer has been wired for PWM capability. > + type: boolean > + > + ti,timer-secure: > + description: > + Timer access has been limited to secure mode only. > + type: boolean > + > + ti,hwmods: > + description: > + Name of the HWMOD associated with timer. This is for legacy > + omap2/3 platforms only. > + $ref: /schemas/types.yaml#/definitions/string > + deprecated: true > + > +required: > + - compatible > + - reg > + - interrupts > + > +additionalProperties: false > + > +allOf: > + - if: > + properties: > + compatible: > + contains: > + enum: > + - ti,omap3430-timer > + - ti,omap4430-timer > + - ti,omap5430-timer > + then: > + properties: > + reg: > + oneOf: > + - items: > + - description: IO address > + - items: > + - description: CPU to L4 ABE IO address > + - description: L3 to L4 ABE IO address > + clocks: > + oneOf: > + - items: > + - description: Functional clock > + - items: > + - description: Functional clock > + - description: System clock I think this can be made simpler, without oneOf: clocks: items: - description: Functional clock - description: System clock minItems: 1 and similar for clock-names. > + clock-names: > + oneOf: > + - items: > + - const: fck > + - items: > + - const: fck > + - const: timer_sys_ck > + else: > + properties: > + reg: > + items: > + - description: IO address > + clocks: > + items: > + - description: Functional clock > + clock-names: > + items: > + - const: fck Hmmm, in your previous version I had impression that first clock is not the same on every flavor. Now it looks the same, so clocks you could simplify even more: 1. Define full list in main properties (not in allOf) with minItems:1 2. Use maxItems:1, for this "else:" case. This could greatly reduce amount of code you need and keep the actual definition of clocks in main properties (not in allOf; allOf are only to constrain it). Best regards, Krzysztof _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel