* [PATCH 0/5] drm/displayid: VESA vendor block and drm/i915 MSO use of it
@ 2021-08-30 10:28 ` Jani Nikula
0 siblings, 0 replies; 23+ messages in thread
From: Jani Nikula @ 2021-08-30 10:28 UTC (permalink / raw)
To: intel-gfx, dri-devel; +Cc: jani.nikula
We need the DisplayID VESA vendor block data for properly configuring
eDP MSO (Multi-SST Operation) pixel overlap.
I haven't actually tested this on a panel that requires the overlap, but
this is all pretty straightforward to prepare for that use case.
BR,
Jani.
Jani Nikula (5):
drm/displayid: re-align data block macros
drm/displayid: add DisplayID v2.0 data blocks and primary use cases
drm/edid: parse the DisplayID v2.0 VESA vendor block for MSO
drm/i915/edp: postpone MSO init until after EDID read
drm/i915/edp: use MSO pixel overlap from DisplayID data
drivers/gpu/drm/drm_edid.c | 63 ++++++++++++++++
drivers/gpu/drm/i915/display/intel_dp.c | 14 ++--
include/drm/drm_connector.h | 12 +++
include/drm/drm_displayid.h | 99 +++++++++++++++++--------
4 files changed, 154 insertions(+), 34 deletions(-)
--
2.20.1
^ permalink raw reply [flat|nested] 23+ messages in thread
* [Intel-gfx] [PATCH 0/5] drm/displayid: VESA vendor block and drm/i915 MSO use of it
@ 2021-08-30 10:28 ` Jani Nikula
0 siblings, 0 replies; 23+ messages in thread
From: Jani Nikula @ 2021-08-30 10:28 UTC (permalink / raw)
To: intel-gfx, dri-devel; +Cc: jani.nikula
We need the DisplayID VESA vendor block data for properly configuring
eDP MSO (Multi-SST Operation) pixel overlap.
I haven't actually tested this on a panel that requires the overlap, but
this is all pretty straightforward to prepare for that use case.
BR,
Jani.
Jani Nikula (5):
drm/displayid: re-align data block macros
drm/displayid: add DisplayID v2.0 data blocks and primary use cases
drm/edid: parse the DisplayID v2.0 VESA vendor block for MSO
drm/i915/edp: postpone MSO init until after EDID read
drm/i915/edp: use MSO pixel overlap from DisplayID data
drivers/gpu/drm/drm_edid.c | 63 ++++++++++++++++
drivers/gpu/drm/i915/display/intel_dp.c | 14 ++--
include/drm/drm_connector.h | 12 +++
include/drm/drm_displayid.h | 99 +++++++++++++++++--------
4 files changed, 154 insertions(+), 34 deletions(-)
--
2.20.1
^ permalink raw reply [flat|nested] 23+ messages in thread
* [PATCH 1/5] drm/displayid: re-align data block macros
2021-08-30 10:28 ` [Intel-gfx] " Jani Nikula
@ 2021-08-30 10:28 ` Jani Nikula
-1 siblings, 0 replies; 23+ messages in thread
From: Jani Nikula @ 2021-08-30 10:28 UTC (permalink / raw)
To: intel-gfx, dri-devel; +Cc: jani.nikula
Make the values easier to read. Also add DisplayID Structure version and
revision information (this is different from the spec version).
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
include/drm/drm_displayid.h | 57 +++++++++++++++++++------------------
1 file changed, 29 insertions(+), 28 deletions(-)
diff --git a/include/drm/drm_displayid.h b/include/drm/drm_displayid.h
index ec64d141f578..0ed9445b5482 100644
--- a/include/drm/drm_displayid.h
+++ b/include/drm/drm_displayid.h
@@ -26,35 +26,36 @@
struct edid;
-#define DATA_BLOCK_PRODUCT_ID 0x00
-#define DATA_BLOCK_DISPLAY_PARAMETERS 0x01
-#define DATA_BLOCK_COLOR_CHARACTERISTICS 0x02
-#define DATA_BLOCK_TYPE_1_DETAILED_TIMING 0x03
-#define DATA_BLOCK_TYPE_2_DETAILED_TIMING 0x04
-#define DATA_BLOCK_TYPE_3_SHORT_TIMING 0x05
-#define DATA_BLOCK_TYPE_4_DMT_TIMING 0x06
-#define DATA_BLOCK_VESA_TIMING 0x07
-#define DATA_BLOCK_CEA_TIMING 0x08
-#define DATA_BLOCK_VIDEO_TIMING_RANGE 0x09
-#define DATA_BLOCK_PRODUCT_SERIAL_NUMBER 0x0a
-#define DATA_BLOCK_GP_ASCII_STRING 0x0b
-#define DATA_BLOCK_DISPLAY_DEVICE_DATA 0x0c
-#define DATA_BLOCK_INTERFACE_POWER_SEQUENCING 0x0d
-#define DATA_BLOCK_TRANSFER_CHARACTERISTICS 0x0e
-#define DATA_BLOCK_DISPLAY_INTERFACE 0x0f
-#define DATA_BLOCK_STEREO_DISPLAY_INTERFACE 0x10
-#define DATA_BLOCK_TILED_DISPLAY 0x12
-#define DATA_BLOCK_CTA 0x81
+/* DisplayID Structure v1r2 Data Blocks */
+#define DATA_BLOCK_PRODUCT_ID 0x00
+#define DATA_BLOCK_DISPLAY_PARAMETERS 0x01
+#define DATA_BLOCK_COLOR_CHARACTERISTICS 0x02
+#define DATA_BLOCK_TYPE_1_DETAILED_TIMING 0x03
+#define DATA_BLOCK_TYPE_2_DETAILED_TIMING 0x04
+#define DATA_BLOCK_TYPE_3_SHORT_TIMING 0x05
+#define DATA_BLOCK_TYPE_4_DMT_TIMING 0x06
+#define DATA_BLOCK_VESA_TIMING 0x07
+#define DATA_BLOCK_CEA_TIMING 0x08
+#define DATA_BLOCK_VIDEO_TIMING_RANGE 0x09
+#define DATA_BLOCK_PRODUCT_SERIAL_NUMBER 0x0a
+#define DATA_BLOCK_GP_ASCII_STRING 0x0b
+#define DATA_BLOCK_DISPLAY_DEVICE_DATA 0x0c
+#define DATA_BLOCK_INTERFACE_POWER_SEQUENCING 0x0d
+#define DATA_BLOCK_TRANSFER_CHARACTERISTICS 0x0e
+#define DATA_BLOCK_DISPLAY_INTERFACE 0x0f
+#define DATA_BLOCK_STEREO_DISPLAY_INTERFACE 0x10
+#define DATA_BLOCK_TILED_DISPLAY 0x12
+#define DATA_BLOCK_VENDOR_SPECIFIC 0x7f
+#define DATA_BLOCK_CTA 0x81
-#define DATA_BLOCK_VENDOR_SPECIFIC 0x7f
-
-#define PRODUCT_TYPE_EXTENSION 0
-#define PRODUCT_TYPE_TEST 1
-#define PRODUCT_TYPE_PANEL 2
-#define PRODUCT_TYPE_MONITOR 3
-#define PRODUCT_TYPE_TV 4
-#define PRODUCT_TYPE_REPEATER 5
-#define PRODUCT_TYPE_DIRECT_DRIVE 6
+/* DisplayID Structure v1r2 Product Type */
+#define PRODUCT_TYPE_EXTENSION 0
+#define PRODUCT_TYPE_TEST 1
+#define PRODUCT_TYPE_PANEL 2
+#define PRODUCT_TYPE_MONITOR 3
+#define PRODUCT_TYPE_TV 4
+#define PRODUCT_TYPE_REPEATER 5
+#define PRODUCT_TYPE_DIRECT_DRIVE 6
struct displayid_header {
u8 rev;
--
2.20.1
^ permalink raw reply related [flat|nested] 23+ messages in thread
* [Intel-gfx] [PATCH 1/5] drm/displayid: re-align data block macros
@ 2021-08-30 10:28 ` Jani Nikula
0 siblings, 0 replies; 23+ messages in thread
From: Jani Nikula @ 2021-08-30 10:28 UTC (permalink / raw)
To: intel-gfx, dri-devel; +Cc: jani.nikula
Make the values easier to read. Also add DisplayID Structure version and
revision information (this is different from the spec version).
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
include/drm/drm_displayid.h | 57 +++++++++++++++++++------------------
1 file changed, 29 insertions(+), 28 deletions(-)
diff --git a/include/drm/drm_displayid.h b/include/drm/drm_displayid.h
index ec64d141f578..0ed9445b5482 100644
--- a/include/drm/drm_displayid.h
+++ b/include/drm/drm_displayid.h
@@ -26,35 +26,36 @@
struct edid;
-#define DATA_BLOCK_PRODUCT_ID 0x00
-#define DATA_BLOCK_DISPLAY_PARAMETERS 0x01
-#define DATA_BLOCK_COLOR_CHARACTERISTICS 0x02
-#define DATA_BLOCK_TYPE_1_DETAILED_TIMING 0x03
-#define DATA_BLOCK_TYPE_2_DETAILED_TIMING 0x04
-#define DATA_BLOCK_TYPE_3_SHORT_TIMING 0x05
-#define DATA_BLOCK_TYPE_4_DMT_TIMING 0x06
-#define DATA_BLOCK_VESA_TIMING 0x07
-#define DATA_BLOCK_CEA_TIMING 0x08
-#define DATA_BLOCK_VIDEO_TIMING_RANGE 0x09
-#define DATA_BLOCK_PRODUCT_SERIAL_NUMBER 0x0a
-#define DATA_BLOCK_GP_ASCII_STRING 0x0b
-#define DATA_BLOCK_DISPLAY_DEVICE_DATA 0x0c
-#define DATA_BLOCK_INTERFACE_POWER_SEQUENCING 0x0d
-#define DATA_BLOCK_TRANSFER_CHARACTERISTICS 0x0e
-#define DATA_BLOCK_DISPLAY_INTERFACE 0x0f
-#define DATA_BLOCK_STEREO_DISPLAY_INTERFACE 0x10
-#define DATA_BLOCK_TILED_DISPLAY 0x12
-#define DATA_BLOCK_CTA 0x81
+/* DisplayID Structure v1r2 Data Blocks */
+#define DATA_BLOCK_PRODUCT_ID 0x00
+#define DATA_BLOCK_DISPLAY_PARAMETERS 0x01
+#define DATA_BLOCK_COLOR_CHARACTERISTICS 0x02
+#define DATA_BLOCK_TYPE_1_DETAILED_TIMING 0x03
+#define DATA_BLOCK_TYPE_2_DETAILED_TIMING 0x04
+#define DATA_BLOCK_TYPE_3_SHORT_TIMING 0x05
+#define DATA_BLOCK_TYPE_4_DMT_TIMING 0x06
+#define DATA_BLOCK_VESA_TIMING 0x07
+#define DATA_BLOCK_CEA_TIMING 0x08
+#define DATA_BLOCK_VIDEO_TIMING_RANGE 0x09
+#define DATA_BLOCK_PRODUCT_SERIAL_NUMBER 0x0a
+#define DATA_BLOCK_GP_ASCII_STRING 0x0b
+#define DATA_BLOCK_DISPLAY_DEVICE_DATA 0x0c
+#define DATA_BLOCK_INTERFACE_POWER_SEQUENCING 0x0d
+#define DATA_BLOCK_TRANSFER_CHARACTERISTICS 0x0e
+#define DATA_BLOCK_DISPLAY_INTERFACE 0x0f
+#define DATA_BLOCK_STEREO_DISPLAY_INTERFACE 0x10
+#define DATA_BLOCK_TILED_DISPLAY 0x12
+#define DATA_BLOCK_VENDOR_SPECIFIC 0x7f
+#define DATA_BLOCK_CTA 0x81
-#define DATA_BLOCK_VENDOR_SPECIFIC 0x7f
-
-#define PRODUCT_TYPE_EXTENSION 0
-#define PRODUCT_TYPE_TEST 1
-#define PRODUCT_TYPE_PANEL 2
-#define PRODUCT_TYPE_MONITOR 3
-#define PRODUCT_TYPE_TV 4
-#define PRODUCT_TYPE_REPEATER 5
-#define PRODUCT_TYPE_DIRECT_DRIVE 6
+/* DisplayID Structure v1r2 Product Type */
+#define PRODUCT_TYPE_EXTENSION 0
+#define PRODUCT_TYPE_TEST 1
+#define PRODUCT_TYPE_PANEL 2
+#define PRODUCT_TYPE_MONITOR 3
+#define PRODUCT_TYPE_TV 4
+#define PRODUCT_TYPE_REPEATER 5
+#define PRODUCT_TYPE_DIRECT_DRIVE 6
struct displayid_header {
u8 rev;
--
2.20.1
^ permalink raw reply related [flat|nested] 23+ messages in thread
* [PATCH 2/5] drm/displayid: add DisplayID v2.0 data blocks and primary use cases
2021-08-30 10:28 ` [Intel-gfx] " Jani Nikula
@ 2021-08-30 10:29 ` Jani Nikula
-1 siblings, 0 replies; 23+ messages in thread
From: Jani Nikula @ 2021-08-30 10:29 UTC (permalink / raw)
To: intel-gfx, dri-devel; +Cc: jani.nikula
DisplayID v2.0 changes the data block identifiers and product types (now
called primary use cases).
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
include/drm/drm_displayid.h | 29 +++++++++++++++++++++++++++++
1 file changed, 29 insertions(+)
diff --git a/include/drm/drm_displayid.h b/include/drm/drm_displayid.h
index 0ed9445b5482..79771091771a 100644
--- a/include/drm/drm_displayid.h
+++ b/include/drm/drm_displayid.h
@@ -26,6 +26,10 @@
struct edid;
+/* DisplayID Structure versions */
+#define DISPLAY_ID_STRUCTURE_VER_12 0x12
+#define DISPLAY_ID_STRUCTURE_VER_20 0x20
+
/* DisplayID Structure v1r2 Data Blocks */
#define DATA_BLOCK_PRODUCT_ID 0x00
#define DATA_BLOCK_DISPLAY_PARAMETERS 0x01
@@ -48,6 +52,20 @@ struct edid;
#define DATA_BLOCK_VENDOR_SPECIFIC 0x7f
#define DATA_BLOCK_CTA 0x81
+/* DisplayID Structure v2r0 Data Blocks */
+#define DATA_BLOCK_2_PRODUCT_ID 0x20
+#define DATA_BLOCK_2_DISPLAY_PARAMETERS 0x21
+#define DATA_BLOCK_2_TYPE_7_DETAILED_TIMING 0x22
+#define DATA_BLOCK_2_TYPE_8_ENUMERATED_TIMING 0x23
+#define DATA_BLOCK_2_TYPE_9_FORMULA_TIMING 0x24
+#define DATA_BLOCK_2_DYNAMIC_VIDEO_TIMING 0x25
+#define DATA_BLOCK_2_DISPLAY_INTERFACE_FEATURES 0x26
+#define DATA_BLOCK_2_STEREO_DISPLAY_INTERFACE 0x27
+#define DATA_BLOCK_2_TILED_DISPLAY_TOPOLOGY 0x28
+#define DATA_BLOCK_2_CONTAINER_ID 0x29
+#define DATA_BLOCK_2_VENDOR_SPECIFIC 0x7e
+#define DATA_BLOCK_2_CTA_DISPLAY_ID 0x81
+
/* DisplayID Structure v1r2 Product Type */
#define PRODUCT_TYPE_EXTENSION 0
#define PRODUCT_TYPE_TEST 1
@@ -57,6 +75,17 @@ struct edid;
#define PRODUCT_TYPE_REPEATER 5
#define PRODUCT_TYPE_DIRECT_DRIVE 6
+/* DisplayID Structure v2r0 Display Product Primary Use Case (~Product Type) */
+#define PRIMARY_USE_EXTENSION 0
+#define PRIMARY_USE_TEST 1
+#define PRIMARY_USE_GENERIC 2
+#define PRIMARY_USE_TV 3
+#define PRIMARY_USE_DESKTOP_PRODUCTIVITY 4
+#define PRIMARY_USE_DESKTOP_GAMING 5
+#define PRIMARY_USE_PRESENTATION 6
+#define PRIMARY_USE_HEAD_MOUNTED_VR 7
+#define PRIMARY_USE_HEAD_MOUNTED_AR 8
+
struct displayid_header {
u8 rev;
u8 bytes;
--
2.20.1
^ permalink raw reply related [flat|nested] 23+ messages in thread
* [Intel-gfx] [PATCH 2/5] drm/displayid: add DisplayID v2.0 data blocks and primary use cases
@ 2021-08-30 10:29 ` Jani Nikula
0 siblings, 0 replies; 23+ messages in thread
From: Jani Nikula @ 2021-08-30 10:29 UTC (permalink / raw)
To: intel-gfx, dri-devel; +Cc: jani.nikula
DisplayID v2.0 changes the data block identifiers and product types (now
called primary use cases).
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
include/drm/drm_displayid.h | 29 +++++++++++++++++++++++++++++
1 file changed, 29 insertions(+)
diff --git a/include/drm/drm_displayid.h b/include/drm/drm_displayid.h
index 0ed9445b5482..79771091771a 100644
--- a/include/drm/drm_displayid.h
+++ b/include/drm/drm_displayid.h
@@ -26,6 +26,10 @@
struct edid;
+/* DisplayID Structure versions */
+#define DISPLAY_ID_STRUCTURE_VER_12 0x12
+#define DISPLAY_ID_STRUCTURE_VER_20 0x20
+
/* DisplayID Structure v1r2 Data Blocks */
#define DATA_BLOCK_PRODUCT_ID 0x00
#define DATA_BLOCK_DISPLAY_PARAMETERS 0x01
@@ -48,6 +52,20 @@ struct edid;
#define DATA_BLOCK_VENDOR_SPECIFIC 0x7f
#define DATA_BLOCK_CTA 0x81
+/* DisplayID Structure v2r0 Data Blocks */
+#define DATA_BLOCK_2_PRODUCT_ID 0x20
+#define DATA_BLOCK_2_DISPLAY_PARAMETERS 0x21
+#define DATA_BLOCK_2_TYPE_7_DETAILED_TIMING 0x22
+#define DATA_BLOCK_2_TYPE_8_ENUMERATED_TIMING 0x23
+#define DATA_BLOCK_2_TYPE_9_FORMULA_TIMING 0x24
+#define DATA_BLOCK_2_DYNAMIC_VIDEO_TIMING 0x25
+#define DATA_BLOCK_2_DISPLAY_INTERFACE_FEATURES 0x26
+#define DATA_BLOCK_2_STEREO_DISPLAY_INTERFACE 0x27
+#define DATA_BLOCK_2_TILED_DISPLAY_TOPOLOGY 0x28
+#define DATA_BLOCK_2_CONTAINER_ID 0x29
+#define DATA_BLOCK_2_VENDOR_SPECIFIC 0x7e
+#define DATA_BLOCK_2_CTA_DISPLAY_ID 0x81
+
/* DisplayID Structure v1r2 Product Type */
#define PRODUCT_TYPE_EXTENSION 0
#define PRODUCT_TYPE_TEST 1
@@ -57,6 +75,17 @@ struct edid;
#define PRODUCT_TYPE_REPEATER 5
#define PRODUCT_TYPE_DIRECT_DRIVE 6
+/* DisplayID Structure v2r0 Display Product Primary Use Case (~Product Type) */
+#define PRIMARY_USE_EXTENSION 0
+#define PRIMARY_USE_TEST 1
+#define PRIMARY_USE_GENERIC 2
+#define PRIMARY_USE_TV 3
+#define PRIMARY_USE_DESKTOP_PRODUCTIVITY 4
+#define PRIMARY_USE_DESKTOP_GAMING 5
+#define PRIMARY_USE_PRESENTATION 6
+#define PRIMARY_USE_HEAD_MOUNTED_VR 7
+#define PRIMARY_USE_HEAD_MOUNTED_AR 8
+
struct displayid_header {
u8 rev;
u8 bytes;
--
2.20.1
^ permalink raw reply related [flat|nested] 23+ messages in thread
* [PATCH 3/5] drm/edid: parse the DisplayID v2.0 VESA vendor block for MSO
2021-08-30 10:28 ` [Intel-gfx] " Jani Nikula
@ 2021-08-30 10:29 ` Jani Nikula
-1 siblings, 0 replies; 23+ messages in thread
From: Jani Nikula @ 2021-08-30 10:29 UTC (permalink / raw)
To: intel-gfx, dri-devel; +Cc: jani.nikula
The VESA Organization Vendor-Specific Data Block, defined in VESA
DisplayID Standard v2.0, specifies the eDP Multi-SST Operation (MSO)
stream count and segment pixel overlap.
DisplayID v1.3 has Appendix B: DisplayID as an EDID Extension,
describing how DisplayID sections may be embedded in EDID extension
blocks. DisplayID v2.0 does not have such a section, perhaps implying
that DisplayID v2.0 data should not be included in EDID extensions, but
rather in a "pure" DisplayID structure at its own DDC address pair
A4h/A5h, as described in VESA E-DDC Standard v1.3 chapter 3.
However, in practice, displays out in the field have embedded DisplayID
v2.0 data blocks in EDID extensions, including, in particular, some eDP
MSO displays, where a pure DisplayID structure is not available at all.
Parse the MSO data from the DisplayID data block. Do it as part of
drm_add_display_info(), extending it to parse also DisplayID data to
avoid requiring extra calls to update the information.
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
drivers/gpu/drm/drm_edid.c | 63 +++++++++++++++++++++++++++++++++++++
include/drm/drm_connector.h | 12 +++++++
include/drm/drm_displayid.h | 11 +++++++
3 files changed, 86 insertions(+)
diff --git a/drivers/gpu/drm/drm_edid.c b/drivers/gpu/drm/drm_edid.c
index 6325877c5fd6..7e8083068f3f 100644
--- a/drivers/gpu/drm/drm_edid.c
+++ b/drivers/gpu/drm/drm_edid.c
@@ -28,6 +28,7 @@
* DEALINGS IN THE SOFTWARE.
*/
+#include <linux/bitfield.h>
#include <linux/hdmi.h>
#include <linux/i2c.h>
#include <linux/kernel.h>
@@ -5148,6 +5149,62 @@ void drm_get_monitor_range(struct drm_connector *connector,
info->monitor_range.max_vfreq);
}
+static void drm_parse_vesa_mso_data(struct drm_connector *connector,
+ const struct displayid_block *block)
+{
+ struct displayid_vesa_vendor_specific_block *vesa =
+ (struct displayid_vesa_vendor_specific_block *)block;
+ struct drm_display_info *info = &connector->display_info;
+
+ if (sizeof(*vesa) != sizeof(*block) + block->num_bytes) {
+ drm_dbg_kms(connector->dev, "Unexpected VESA vendor block size\n");
+ return;
+ }
+
+ switch (FIELD_GET(DISPLAYID_VESA_MSO_MODE, vesa->mso)) {
+ default:
+ drm_dbg_kms(connector->dev, "Reserved MSO mode value\n");
+ fallthrough;
+ case 0:
+ info->mso_stream_count = 0;
+ break;
+ case 1:
+ info->mso_stream_count = 2; /* 2 or 4 links */
+ break;
+ case 2:
+ info->mso_stream_count = 4; /* 4 links */
+ break;
+ }
+
+ if (!info->mso_stream_count) {
+ info->mso_pixel_overlap = 0;
+ return;
+ }
+
+ info->mso_pixel_overlap = FIELD_GET(DISPLAYID_VESA_MSO_OVERLAP, vesa->mso);
+ if (info->mso_pixel_overlap > 8) {
+ drm_dbg_kms(connector->dev, "Reserved MSO pixel overlap value %u\n",
+ info->mso_pixel_overlap);
+ info->mso_pixel_overlap = 8;
+ }
+
+ drm_dbg_kms(connector->dev, "MSO stream count %u, pixel overlap %u\n",
+ info->mso_stream_count, info->mso_pixel_overlap);
+}
+
+static void drm_update_mso(struct drm_connector *connector, const struct edid *edid)
+{
+ const struct displayid_block *block;
+ struct displayid_iter iter;
+
+ displayid_iter_edid_begin(edid, &iter);
+ displayid_iter_for_each(block, &iter) {
+ if (block->tag == DATA_BLOCK_2_VENDOR_SPECIFIC)
+ drm_parse_vesa_mso_data(connector, block);
+ }
+ displayid_iter_end(&iter);
+}
+
/* A connector has no EDID information, so we've got no EDID to compute quirks from. Reset
* all of the values which would have been set from EDID
*/
@@ -5171,6 +5228,9 @@ drm_reset_display_info(struct drm_connector *connector)
info->non_desktop = 0;
memset(&info->monitor_range, 0, sizeof(info->monitor_range));
+
+ info->mso_stream_count = 0;
+ info->mso_pixel_overlap = 0;
}
u32 drm_add_display_info(struct drm_connector *connector, const struct edid *edid)
@@ -5249,6 +5309,9 @@ u32 drm_add_display_info(struct drm_connector *connector, const struct edid *edi
info->color_formats |= DRM_COLOR_FORMAT_YCRCB444;
if (edid->features & DRM_EDID_FEATURE_RGB_YCRCB422)
info->color_formats |= DRM_COLOR_FORMAT_YCRCB422;
+
+ drm_update_mso(connector, edid);
+
return quirks;
}
diff --git a/include/drm/drm_connector.h b/include/drm/drm_connector.h
index 79fa34e5ccdb..379746d3266f 100644
--- a/include/drm/drm_connector.h
+++ b/include/drm/drm_connector.h
@@ -590,6 +590,18 @@ struct drm_display_info {
* @monitor_range: Frequency range supported by monitor range descriptor
*/
struct drm_monitor_range_info monitor_range;
+
+ /**
+ * @mso_stream_count: eDP Multi-SST Operation (MSO) stream count from
+ * the DisplayID VESA vendor block. 0 for conventional Single-Stream
+ * Transport (SST), or 2 or 4 MSO streams.
+ */
+ u8 mso_stream_count;
+
+ /**
+ * @mso_pixel_overlap: eDP MSO segment pixel overlap, 0-8 pixels.
+ */
+ u8 mso_pixel_overlap;
};
int drm_display_info_set_bus_formats(struct drm_display_info *info,
diff --git a/include/drm/drm_displayid.h b/include/drm/drm_displayid.h
index 79771091771a..b18611e016a2 100644
--- a/include/drm/drm_displayid.h
+++ b/include/drm/drm_displayid.h
@@ -23,6 +23,7 @@
#define DRM_DISPLAYID_H
#include <linux/types.h>
+#include <linux/bits.h>
struct edid;
@@ -126,6 +127,16 @@ struct displayid_detailed_timing_block {
struct displayid_detailed_timings_1 timings[];
};
+#define DISPLAYID_VESA_MSO_OVERLAP GENMASK(3, 0)
+#define DISPLAYID_VESA_MSO_MODE GENMASK(6, 5)
+
+struct displayid_vesa_vendor_specific_block {
+ struct displayid_block base;
+ u8 oui[3];
+ u8 data_structure_type;
+ u8 mso;
+} __packed;
+
/* DisplayID iteration */
struct displayid_iter {
const struct edid *edid;
--
2.20.1
^ permalink raw reply related [flat|nested] 23+ messages in thread
* [Intel-gfx] [PATCH 3/5] drm/edid: parse the DisplayID v2.0 VESA vendor block for MSO
@ 2021-08-30 10:29 ` Jani Nikula
0 siblings, 0 replies; 23+ messages in thread
From: Jani Nikula @ 2021-08-30 10:29 UTC (permalink / raw)
To: intel-gfx, dri-devel; +Cc: jani.nikula
The VESA Organization Vendor-Specific Data Block, defined in VESA
DisplayID Standard v2.0, specifies the eDP Multi-SST Operation (MSO)
stream count and segment pixel overlap.
DisplayID v1.3 has Appendix B: DisplayID as an EDID Extension,
describing how DisplayID sections may be embedded in EDID extension
blocks. DisplayID v2.0 does not have such a section, perhaps implying
that DisplayID v2.0 data should not be included in EDID extensions, but
rather in a "pure" DisplayID structure at its own DDC address pair
A4h/A5h, as described in VESA E-DDC Standard v1.3 chapter 3.
However, in practice, displays out in the field have embedded DisplayID
v2.0 data blocks in EDID extensions, including, in particular, some eDP
MSO displays, where a pure DisplayID structure is not available at all.
Parse the MSO data from the DisplayID data block. Do it as part of
drm_add_display_info(), extending it to parse also DisplayID data to
avoid requiring extra calls to update the information.
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
drivers/gpu/drm/drm_edid.c | 63 +++++++++++++++++++++++++++++++++++++
include/drm/drm_connector.h | 12 +++++++
include/drm/drm_displayid.h | 11 +++++++
3 files changed, 86 insertions(+)
diff --git a/drivers/gpu/drm/drm_edid.c b/drivers/gpu/drm/drm_edid.c
index 6325877c5fd6..7e8083068f3f 100644
--- a/drivers/gpu/drm/drm_edid.c
+++ b/drivers/gpu/drm/drm_edid.c
@@ -28,6 +28,7 @@
* DEALINGS IN THE SOFTWARE.
*/
+#include <linux/bitfield.h>
#include <linux/hdmi.h>
#include <linux/i2c.h>
#include <linux/kernel.h>
@@ -5148,6 +5149,62 @@ void drm_get_monitor_range(struct drm_connector *connector,
info->monitor_range.max_vfreq);
}
+static void drm_parse_vesa_mso_data(struct drm_connector *connector,
+ const struct displayid_block *block)
+{
+ struct displayid_vesa_vendor_specific_block *vesa =
+ (struct displayid_vesa_vendor_specific_block *)block;
+ struct drm_display_info *info = &connector->display_info;
+
+ if (sizeof(*vesa) != sizeof(*block) + block->num_bytes) {
+ drm_dbg_kms(connector->dev, "Unexpected VESA vendor block size\n");
+ return;
+ }
+
+ switch (FIELD_GET(DISPLAYID_VESA_MSO_MODE, vesa->mso)) {
+ default:
+ drm_dbg_kms(connector->dev, "Reserved MSO mode value\n");
+ fallthrough;
+ case 0:
+ info->mso_stream_count = 0;
+ break;
+ case 1:
+ info->mso_stream_count = 2; /* 2 or 4 links */
+ break;
+ case 2:
+ info->mso_stream_count = 4; /* 4 links */
+ break;
+ }
+
+ if (!info->mso_stream_count) {
+ info->mso_pixel_overlap = 0;
+ return;
+ }
+
+ info->mso_pixel_overlap = FIELD_GET(DISPLAYID_VESA_MSO_OVERLAP, vesa->mso);
+ if (info->mso_pixel_overlap > 8) {
+ drm_dbg_kms(connector->dev, "Reserved MSO pixel overlap value %u\n",
+ info->mso_pixel_overlap);
+ info->mso_pixel_overlap = 8;
+ }
+
+ drm_dbg_kms(connector->dev, "MSO stream count %u, pixel overlap %u\n",
+ info->mso_stream_count, info->mso_pixel_overlap);
+}
+
+static void drm_update_mso(struct drm_connector *connector, const struct edid *edid)
+{
+ const struct displayid_block *block;
+ struct displayid_iter iter;
+
+ displayid_iter_edid_begin(edid, &iter);
+ displayid_iter_for_each(block, &iter) {
+ if (block->tag == DATA_BLOCK_2_VENDOR_SPECIFIC)
+ drm_parse_vesa_mso_data(connector, block);
+ }
+ displayid_iter_end(&iter);
+}
+
/* A connector has no EDID information, so we've got no EDID to compute quirks from. Reset
* all of the values which would have been set from EDID
*/
@@ -5171,6 +5228,9 @@ drm_reset_display_info(struct drm_connector *connector)
info->non_desktop = 0;
memset(&info->monitor_range, 0, sizeof(info->monitor_range));
+
+ info->mso_stream_count = 0;
+ info->mso_pixel_overlap = 0;
}
u32 drm_add_display_info(struct drm_connector *connector, const struct edid *edid)
@@ -5249,6 +5309,9 @@ u32 drm_add_display_info(struct drm_connector *connector, const struct edid *edi
info->color_formats |= DRM_COLOR_FORMAT_YCRCB444;
if (edid->features & DRM_EDID_FEATURE_RGB_YCRCB422)
info->color_formats |= DRM_COLOR_FORMAT_YCRCB422;
+
+ drm_update_mso(connector, edid);
+
return quirks;
}
diff --git a/include/drm/drm_connector.h b/include/drm/drm_connector.h
index 79fa34e5ccdb..379746d3266f 100644
--- a/include/drm/drm_connector.h
+++ b/include/drm/drm_connector.h
@@ -590,6 +590,18 @@ struct drm_display_info {
* @monitor_range: Frequency range supported by monitor range descriptor
*/
struct drm_monitor_range_info monitor_range;
+
+ /**
+ * @mso_stream_count: eDP Multi-SST Operation (MSO) stream count from
+ * the DisplayID VESA vendor block. 0 for conventional Single-Stream
+ * Transport (SST), or 2 or 4 MSO streams.
+ */
+ u8 mso_stream_count;
+
+ /**
+ * @mso_pixel_overlap: eDP MSO segment pixel overlap, 0-8 pixels.
+ */
+ u8 mso_pixel_overlap;
};
int drm_display_info_set_bus_formats(struct drm_display_info *info,
diff --git a/include/drm/drm_displayid.h b/include/drm/drm_displayid.h
index 79771091771a..b18611e016a2 100644
--- a/include/drm/drm_displayid.h
+++ b/include/drm/drm_displayid.h
@@ -23,6 +23,7 @@
#define DRM_DISPLAYID_H
#include <linux/types.h>
+#include <linux/bits.h>
struct edid;
@@ -126,6 +127,16 @@ struct displayid_detailed_timing_block {
struct displayid_detailed_timings_1 timings[];
};
+#define DISPLAYID_VESA_MSO_OVERLAP GENMASK(3, 0)
+#define DISPLAYID_VESA_MSO_MODE GENMASK(6, 5)
+
+struct displayid_vesa_vendor_specific_block {
+ struct displayid_block base;
+ u8 oui[3];
+ u8 data_structure_type;
+ u8 mso;
+} __packed;
+
/* DisplayID iteration */
struct displayid_iter {
const struct edid *edid;
--
2.20.1
^ permalink raw reply related [flat|nested] 23+ messages in thread
* [PATCH 4/5] drm/i915/edp: postpone MSO init until after EDID read
2021-08-30 10:28 ` [Intel-gfx] " Jani Nikula
@ 2021-08-30 10:29 ` Jani Nikula
-1 siblings, 0 replies; 23+ messages in thread
From: Jani Nikula @ 2021-08-30 10:29 UTC (permalink / raw)
To: intel-gfx, dri-devel; +Cc: jani.nikula
MSO will require segment pixel overlap information from the
EDID. Postpone MSO init until after we've read and cached the EDID.
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
drivers/gpu/drm/i915/display/intel_dp.c | 5 +++--
1 file changed, 3 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index 7f8e8865048f..8e75543334c2 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -2575,8 +2575,6 @@ intel_edp_init_dpcd(struct intel_dp *intel_dp)
*/
intel_edp_init_source_oui(intel_dp, true);
- intel_edp_mso_init(intel_dp);
-
return true;
}
@@ -5269,6 +5267,9 @@ static bool intel_edp_init_connector(struct intel_dp *intel_dp,
if (fixed_mode)
downclock_mode = intel_dp_drrs_init(intel_connector, fixed_mode);
+ /* MSO requires information from the EDID */
+ intel_edp_mso_init(intel_dp);
+
/* multiply the mode clock and horizontal timings for MSO */
intel_edp_mso_mode_fixup(intel_connector, fixed_mode);
intel_edp_mso_mode_fixup(intel_connector, downclock_mode);
--
2.20.1
^ permalink raw reply related [flat|nested] 23+ messages in thread
* [Intel-gfx] [PATCH 4/5] drm/i915/edp: postpone MSO init until after EDID read
@ 2021-08-30 10:29 ` Jani Nikula
0 siblings, 0 replies; 23+ messages in thread
From: Jani Nikula @ 2021-08-30 10:29 UTC (permalink / raw)
To: intel-gfx, dri-devel; +Cc: jani.nikula
MSO will require segment pixel overlap information from the
EDID. Postpone MSO init until after we've read and cached the EDID.
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
drivers/gpu/drm/i915/display/intel_dp.c | 5 +++--
1 file changed, 3 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index 7f8e8865048f..8e75543334c2 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -2575,8 +2575,6 @@ intel_edp_init_dpcd(struct intel_dp *intel_dp)
*/
intel_edp_init_source_oui(intel_dp, true);
- intel_edp_mso_init(intel_dp);
-
return true;
}
@@ -5269,6 +5267,9 @@ static bool intel_edp_init_connector(struct intel_dp *intel_dp,
if (fixed_mode)
downclock_mode = intel_dp_drrs_init(intel_connector, fixed_mode);
+ /* MSO requires information from the EDID */
+ intel_edp_mso_init(intel_dp);
+
/* multiply the mode clock and horizontal timings for MSO */
intel_edp_mso_mode_fixup(intel_connector, fixed_mode);
intel_edp_mso_mode_fixup(intel_connector, downclock_mode);
--
2.20.1
^ permalink raw reply related [flat|nested] 23+ messages in thread
* [PATCH 5/5] drm/i915/edp: use MSO pixel overlap from DisplayID data
2021-08-30 10:28 ` [Intel-gfx] " Jani Nikula
@ 2021-08-30 10:29 ` Jani Nikula
-1 siblings, 0 replies; 23+ messages in thread
From: Jani Nikula @ 2021-08-30 10:29 UTC (permalink / raw)
To: intel-gfx, dri-devel; +Cc: jani.nikula
Now that we have MSO pixel overlap in display info, use it.
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
drivers/gpu/drm/i915/display/intel_dp.c | 9 ++++++---
1 file changed, 6 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index 8e75543334c2..0d7c9eadca08 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -2459,6 +2459,8 @@ static void intel_edp_mso_mode_fixup(struct intel_connector *connector,
static void intel_edp_mso_init(struct intel_dp *intel_dp)
{
struct drm_i915_private *i915 = dp_to_i915(intel_dp);
+ struct intel_connector *connector = intel_dp->attached_connector;
+ struct drm_display_info *info = &connector->base.display_info;
u8 mso;
if (intel_dp->edp_dpcd[0] < DP_EDP_14)
@@ -2477,8 +2479,9 @@ static void intel_edp_mso_init(struct intel_dp *intel_dp)
}
if (mso) {
- drm_dbg_kms(&i915->drm, "Sink MSO %ux%u configuration\n",
- mso, drm_dp_max_lane_count(intel_dp->dpcd) / mso);
+ drm_dbg_kms(&i915->drm, "Sink MSO %ux%u configuration, pixel overlap %u\n",
+ mso, drm_dp_max_lane_count(intel_dp->dpcd) / mso,
+ info->mso_pixel_overlap);
if (!HAS_MSO(i915)) {
drm_err(&i915->drm, "No source MSO support, disabling\n");
mso = 0;
@@ -2486,7 +2489,7 @@ static void intel_edp_mso_init(struct intel_dp *intel_dp)
}
intel_dp->mso_link_count = mso;
- intel_dp->mso_pixel_overlap = 0; /* FIXME: read from DisplayID v2.0 */
+ intel_dp->mso_pixel_overlap = mso ? info->mso_pixel_overlap : 0;
}
static bool
--
2.20.1
^ permalink raw reply related [flat|nested] 23+ messages in thread
* [Intel-gfx] [PATCH 5/5] drm/i915/edp: use MSO pixel overlap from DisplayID data
@ 2021-08-30 10:29 ` Jani Nikula
0 siblings, 0 replies; 23+ messages in thread
From: Jani Nikula @ 2021-08-30 10:29 UTC (permalink / raw)
To: intel-gfx, dri-devel; +Cc: jani.nikula
Now that we have MSO pixel overlap in display info, use it.
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
drivers/gpu/drm/i915/display/intel_dp.c | 9 ++++++---
1 file changed, 6 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index 8e75543334c2..0d7c9eadca08 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -2459,6 +2459,8 @@ static void intel_edp_mso_mode_fixup(struct intel_connector *connector,
static void intel_edp_mso_init(struct intel_dp *intel_dp)
{
struct drm_i915_private *i915 = dp_to_i915(intel_dp);
+ struct intel_connector *connector = intel_dp->attached_connector;
+ struct drm_display_info *info = &connector->base.display_info;
u8 mso;
if (intel_dp->edp_dpcd[0] < DP_EDP_14)
@@ -2477,8 +2479,9 @@ static void intel_edp_mso_init(struct intel_dp *intel_dp)
}
if (mso) {
- drm_dbg_kms(&i915->drm, "Sink MSO %ux%u configuration\n",
- mso, drm_dp_max_lane_count(intel_dp->dpcd) / mso);
+ drm_dbg_kms(&i915->drm, "Sink MSO %ux%u configuration, pixel overlap %u\n",
+ mso, drm_dp_max_lane_count(intel_dp->dpcd) / mso,
+ info->mso_pixel_overlap);
if (!HAS_MSO(i915)) {
drm_err(&i915->drm, "No source MSO support, disabling\n");
mso = 0;
@@ -2486,7 +2489,7 @@ static void intel_edp_mso_init(struct intel_dp *intel_dp)
}
intel_dp->mso_link_count = mso;
- intel_dp->mso_pixel_overlap = 0; /* FIXME: read from DisplayID v2.0 */
+ intel_dp->mso_pixel_overlap = mso ? info->mso_pixel_overlap : 0;
}
static bool
--
2.20.1
^ permalink raw reply related [flat|nested] 23+ messages in thread
* Re: [PATCH 3/5] drm/edid: parse the DisplayID v2.0 VESA vendor block for MSO
2021-08-30 10:29 ` [Intel-gfx] " Jani Nikula
@ 2021-08-30 10:43 ` Jani Nikula
-1 siblings, 0 replies; 23+ messages in thread
From: Jani Nikula @ 2021-08-30 10:43 UTC (permalink / raw)
To: intel-gfx, dri-devel
On Mon, 30 Aug 2021, Jani Nikula <jani.nikula@intel.com> wrote:
> The VESA Organization Vendor-Specific Data Block, defined in VESA
> DisplayID Standard v2.0, specifies the eDP Multi-SST Operation (MSO)
> stream count and segment pixel overlap.
>
> DisplayID v1.3 has Appendix B: DisplayID as an EDID Extension,
> describing how DisplayID sections may be embedded in EDID extension
> blocks. DisplayID v2.0 does not have such a section, perhaps implying
> that DisplayID v2.0 data should not be included in EDID extensions, but
> rather in a "pure" DisplayID structure at its own DDC address pair
> A4h/A5h, as described in VESA E-DDC Standard v1.3 chapter 3.
>
> However, in practice, displays out in the field have embedded DisplayID
> v2.0 data blocks in EDID extensions, including, in particular, some eDP
> MSO displays, where a pure DisplayID structure is not available at all.
>
> Parse the MSO data from the DisplayID data block. Do it as part of
> drm_add_display_info(), extending it to parse also DisplayID data to
> avoid requiring extra calls to update the information.
For reference, this is the EDID from a Lenovo ThinkPad X1 with eDP MSO
display. AFAICT, the display does not respond on A4h/A5h at all, it only
has the usual EDID at the usual DDC address.
BR,
Jani.
edid-decode (hex):
00 ff ff ff ff ff ff 00 06 af 13 10 00 00 00 00
00 1c 01 04 a5 1c 13 78 02 ee 95 a3 54 4c 99 26
0f 50 54 00 00 00 01 01 01 01 01 01 01 01 01 01
01 01 01 01 01 01 d5 2b 68 50 40 e0 2c 50 18 10
3a 00 1c bd 10 00 00 18 00 00 00 0f 00 00 00 00
00 00 00 00 00 00 00 00 00 20 00 00 00 fe 00 41
55 4f 0a 20 20 20 20 20 20 20 20 20 00 00 00 fe
00 42 31 33 35 51 41 4e 30 31 2e 30 20 0a 01 e1
70 20 08 06 00 7e 00 05 3a 02 92 00 20 61 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 90
----------------
Block 0, Base EDID:
EDID Structure Version & Revision: 1.4
Vendor & Product Identification:
Manufacturer: AUO
Model: 4115
Made in: 2018
Basic Display Parameters & Features:
Digital display
Bits per primary color channel: 8
DisplayPort interface
Maximum image size: 28 cm x 19 cm
Gamma: 2.20
Supported color formats: RGB 4:4:4
First detailed timing includes the native pixel format and preferred refresh rate
Color Characteristics:
Red : 0.6396, 0.3300
Green: 0.2998, 0.5996
Blue : 0.1503, 0.0595
White: 0.3134, 0.3291
Established Timings I & II: none
Standard Timings: none
Detailed Timing Descriptors:
DTD 1: 1128x1504 60.006 Hz 3:4 92.889 kHz 112.210 MHz (284 mm x 189 mm)
Hfront 24 Hsync 16 Hback 40 Hpol N
Vfront 3 Vsync 10 Vback 31 Vpol N
Manufacturer-Specified Display Descriptor (0x0f): 00 0f 00 00 00 00 00 00 00 00 00 00 00 00 00 20 '............... '
Alphanumeric Data String: 'AUO'
Alphanumeric Data String: 'B135QAN01.0 '
Extension blocks: 1
Checksum: 0xe1
----------------
Block 1, DisplayID Extension Block:
Version: 2.0
Extension Count: 0
Display Product Primary Use Case: Presentation display
Vendor-Specific Data Block (VESA):
Data Structure Type: eDP
Default Colorspace and EOTF Handling: sRGB
Number of Pixels in Hor Pix Cnt Overlapping an Adjacent Panel: 0
Multi-SST Operation: Two Streams (number of links shall be 2 or 4)
Checksum: 0x61
Checksum: 0x90
--
Jani Nikula, Intel Open Source Graphics Center
^ permalink raw reply [flat|nested] 23+ messages in thread
* Re: [Intel-gfx] [PATCH 3/5] drm/edid: parse the DisplayID v2.0 VESA vendor block for MSO
@ 2021-08-30 10:43 ` Jani Nikula
0 siblings, 0 replies; 23+ messages in thread
From: Jani Nikula @ 2021-08-30 10:43 UTC (permalink / raw)
To: intel-gfx, dri-devel
On Mon, 30 Aug 2021, Jani Nikula <jani.nikula@intel.com> wrote:
> The VESA Organization Vendor-Specific Data Block, defined in VESA
> DisplayID Standard v2.0, specifies the eDP Multi-SST Operation (MSO)
> stream count and segment pixel overlap.
>
> DisplayID v1.3 has Appendix B: DisplayID as an EDID Extension,
> describing how DisplayID sections may be embedded in EDID extension
> blocks. DisplayID v2.0 does not have such a section, perhaps implying
> that DisplayID v2.0 data should not be included in EDID extensions, but
> rather in a "pure" DisplayID structure at its own DDC address pair
> A4h/A5h, as described in VESA E-DDC Standard v1.3 chapter 3.
>
> However, in practice, displays out in the field have embedded DisplayID
> v2.0 data blocks in EDID extensions, including, in particular, some eDP
> MSO displays, where a pure DisplayID structure is not available at all.
>
> Parse the MSO data from the DisplayID data block. Do it as part of
> drm_add_display_info(), extending it to parse also DisplayID data to
> avoid requiring extra calls to update the information.
For reference, this is the EDID from a Lenovo ThinkPad X1 with eDP MSO
display. AFAICT, the display does not respond on A4h/A5h at all, it only
has the usual EDID at the usual DDC address.
BR,
Jani.
edid-decode (hex):
00 ff ff ff ff ff ff 00 06 af 13 10 00 00 00 00
00 1c 01 04 a5 1c 13 78 02 ee 95 a3 54 4c 99 26
0f 50 54 00 00 00 01 01 01 01 01 01 01 01 01 01
01 01 01 01 01 01 d5 2b 68 50 40 e0 2c 50 18 10
3a 00 1c bd 10 00 00 18 00 00 00 0f 00 00 00 00
00 00 00 00 00 00 00 00 00 20 00 00 00 fe 00 41
55 4f 0a 20 20 20 20 20 20 20 20 20 00 00 00 fe
00 42 31 33 35 51 41 4e 30 31 2e 30 20 0a 01 e1
70 20 08 06 00 7e 00 05 3a 02 92 00 20 61 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 90
----------------
Block 0, Base EDID:
EDID Structure Version & Revision: 1.4
Vendor & Product Identification:
Manufacturer: AUO
Model: 4115
Made in: 2018
Basic Display Parameters & Features:
Digital display
Bits per primary color channel: 8
DisplayPort interface
Maximum image size: 28 cm x 19 cm
Gamma: 2.20
Supported color formats: RGB 4:4:4
First detailed timing includes the native pixel format and preferred refresh rate
Color Characteristics:
Red : 0.6396, 0.3300
Green: 0.2998, 0.5996
Blue : 0.1503, 0.0595
White: 0.3134, 0.3291
Established Timings I & II: none
Standard Timings: none
Detailed Timing Descriptors:
DTD 1: 1128x1504 60.006 Hz 3:4 92.889 kHz 112.210 MHz (284 mm x 189 mm)
Hfront 24 Hsync 16 Hback 40 Hpol N
Vfront 3 Vsync 10 Vback 31 Vpol N
Manufacturer-Specified Display Descriptor (0x0f): 00 0f 00 00 00 00 00 00 00 00 00 00 00 00 00 20 '............... '
Alphanumeric Data String: 'AUO'
Alphanumeric Data String: 'B135QAN01.0 '
Extension blocks: 1
Checksum: 0xe1
----------------
Block 1, DisplayID Extension Block:
Version: 2.0
Extension Count: 0
Display Product Primary Use Case: Presentation display
Vendor-Specific Data Block (VESA):
Data Structure Type: eDP
Default Colorspace and EOTF Handling: sRGB
Number of Pixels in Hor Pix Cnt Overlapping an Adjacent Panel: 0
Multi-SST Operation: Two Streams (number of links shall be 2 or 4)
Checksum: 0x61
Checksum: 0x90
--
Jani Nikula, Intel Open Source Graphics Center
^ permalink raw reply [flat|nested] 23+ messages in thread
* [Intel-gfx] ✗ Fi.CI.SPARSE: warning for drm/displayid: VESA vendor block and drm/i915 MSO use of it
2021-08-30 10:28 ` [Intel-gfx] " Jani Nikula
` (5 preceding siblings ...)
(?)
@ 2021-08-30 12:31 ` Patchwork
-1 siblings, 0 replies; 23+ messages in thread
From: Patchwork @ 2021-08-30 12:31 UTC (permalink / raw)
To: Jani Nikula; +Cc: intel-gfx
== Series Details ==
Series: drm/displayid: VESA vendor block and drm/i915 MSO use of it
URL : https://patchwork.freedesktop.org/series/94161/
State : warning
== Summary ==
$ dim sparse --fast origin/drm-tip
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
-
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:316:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:316:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:316:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:316:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:316:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:316:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:316:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:316:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:316:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:316:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:316:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:316:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:316:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:316:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:316:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:316:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:316:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:316:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:316:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:316:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:316:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:316:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:316:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:316:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:316:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:316:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:316:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:316:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:316:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:316:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:316:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:316:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:316:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:316:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:316:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:316:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:316:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:316:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:316:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:316:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:316:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:316:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:316:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:316:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:316:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:316:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:316:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:316:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:316:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:316:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:316:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:316:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:316:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:316:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:316:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:316:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:316:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:316:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:316:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:316:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:316:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:316:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:316:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:316:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:316:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:316:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:316:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:316:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:316:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:316:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:316:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:316:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:316:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:316:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:316:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:316:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:316:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:316:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:316:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:316:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:316:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:1345:25: error: incompatible types in comparison expression (different address spaces):
+drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:1345:25: struct dma_fence *
+drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:1345:25: struct dma_fence [noderef] __rcu *
+drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:1346:17: error: incompatible types in comparison expression (different address spaces):
+drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:1346:17: struct dma_fence *
+drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:1346:17: struct dma_fence [noderef] __rcu *
+drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:1405:17: error: incompatible types in comparison expression (different address spaces):
+drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:1405:17: struct dma_fence *
+drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:1405:17: struct dma_fence [noderef] __rcu *
+drivers/gpu/drm/amd/amdgpu/amdgpu_device.c:354:16: error: incompatible types in comparison expression (different type sizes):
+drivers/gpu/drm/amd/amdgpu/amdgpu_device.c:354:16: unsigned long *
+drivers/gpu/drm/amd/amdgpu/amdgpu_device.c:354:16: unsigned long long *
+drivers/gpu/drm/amd/amdgpu/amdgpu_device.c:4483:31: error: incompatible types in comparison expression (different address spaces):
+drivers/gpu/drm/amd/amdgpu/amdgpu_device.c:4483:31: struct dma_fence *
+drivers/gpu/drm/amd/amdgpu/amdgpu_device.c:4483:31: struct dma_fence [noderef] __rcu *
+drivers/gpu/drm/amd/amdgpu/amdgpu_device.c:4485:33: error: incompatible types in comparison expression (different address spaces):
+drivers/gpu/drm/amd/amdgpu/amdgpu_device.c:4485:33: struct dma_fence *
+drivers/gpu/drm/amd/amdgpu/amdgpu_device.c:4485:33: struct dma_fence [noderef] __rcu *
+drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c:295:25: error: incompatible types in comparison expression (different address spaces):
+drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c:295:25: struct dma_fence *
+drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c:295:25: struct dma_fence [noderef] __rcu *
+drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c:296:17: error: incompatible types in comparison expression (different address spaces):
+drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c:296:17: struct dma_fence *
+drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c:296:17: struct dma_fence [noderef] __rcu *
+drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c:350:17: error: incompatible types in comparison expression (different address spaces):
+drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c:350:17: struct dma_fence *
+drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c:350:17: struct dma_fence [noderef] __rcu *
+drivers/gpu/drm/amd/amdgpu/amdgpu_mca.c:117:1: warning: no newline at end of file
+drivers/gpu/drm/amd/amdgpu/amdgpu_ras_eeprom.h:123:51: error: marked inline, but without a definition
+drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2p
^ permalink raw reply [flat|nested] 23+ messages in thread
* [Intel-gfx] ✓ Fi.CI.BAT: success for drm/displayid: VESA vendor block and drm/i915 MSO use of it
2021-08-30 10:28 ` [Intel-gfx] " Jani Nikula
` (6 preceding siblings ...)
(?)
@ 2021-08-30 12:59 ` Patchwork
-1 siblings, 0 replies; 23+ messages in thread
From: Patchwork @ 2021-08-30 12:59 UTC (permalink / raw)
To: Jani Nikula; +Cc: intel-gfx
[-- Attachment #1: Type: text/plain, Size: 4141 bytes --]
== Series Details ==
Series: drm/displayid: VESA vendor block and drm/i915 MSO use of it
URL : https://patchwork.freedesktop.org/series/94161/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_10536 -> Patchwork_20916
====================================================
Summary
-------
**SUCCESS**
No regressions found.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20916/index.html
Known issues
------------
Here are the changes found in Patchwork_20916 that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@amdgpu/amd_basic@cs-gfx:
- fi-rkl-guc: NOTRUN -> [SKIP][1] ([fdo#109315]) +17 similar issues
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20916/fi-rkl-guc/igt@amdgpu/amd_basic@cs-gfx.html
* igt@amdgpu/amd_cs_nop@sync-fork-compute0:
- fi-snb-2600: NOTRUN -> [SKIP][2] ([fdo#109271]) +17 similar issues
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20916/fi-snb-2600/igt@amdgpu/amd_cs_nop@sync-fork-compute0.html
- fi-kbl-soraka: NOTRUN -> [SKIP][3] ([fdo#109271]) +8 similar issues
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20916/fi-kbl-soraka/igt@amdgpu/amd_cs_nop@sync-fork-compute0.html
* igt@kms_chamelium@common-hpd-after-suspend:
- fi-icl-u2: [PASS][4] -> [DMESG-WARN][5] ([i915#2868])
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10536/fi-icl-u2/igt@kms_chamelium@common-hpd-after-suspend.html
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20916/fi-icl-u2/igt@kms_chamelium@common-hpd-after-suspend.html
* igt@kms_chamelium@hdmi-edid-read:
- fi-kbl-7500u: [PASS][6] -> [FAIL][7] ([i915#3449])
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10536/fi-kbl-7500u/igt@kms_chamelium@hdmi-edid-read.html
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20916/fi-kbl-7500u/igt@kms_chamelium@hdmi-edid-read.html
#### Possible fixes ####
* igt@i915_selftest@live@hangcheck:
- fi-snb-2600: [INCOMPLETE][8] ([i915#3921]) -> [PASS][9]
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10536/fi-snb-2600/igt@i915_selftest@live@hangcheck.html
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20916/fi-snb-2600/igt@i915_selftest@live@hangcheck.html
* igt@i915_selftest@live@workarounds:
- fi-rkl-guc: [DMESG-FAIL][10] ([i915#3928]) -> [PASS][11]
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10536/fi-rkl-guc/igt@i915_selftest@live@workarounds.html
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20916/fi-rkl-guc/igt@i915_selftest@live@workarounds.html
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[fdo#109315]: https://bugs.freedesktop.org/show_bug.cgi?id=109315
[i915#2868]: https://gitlab.freedesktop.org/drm/intel/issues/2868
[i915#3449]: https://gitlab.freedesktop.org/drm/intel/issues/3449
[i915#3921]: https://gitlab.freedesktop.org/drm/intel/issues/3921
[i915#3928]: https://gitlab.freedesktop.org/drm/intel/issues/3928
Participating hosts (44 -> 35)
------------------------------
Missing (9): fi-ilk-m540 bat-adls-5 bat-dg1-6 bat-dg1-5 fi-bsw-cyan fi-ctg-p8600 fi-bsw-kefka fi-bdw-samus bat-jsl-1
Build changes
-------------
* Linux: CI_DRM_10536 -> Patchwork_20916
CI-20190529: 20190529
CI_DRM_10536: b6d834a72c14ca22b2df32a607c1ee36e8629f1a @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_6191: e9292b533691784f46eeb9bae522ca7a8710c920 @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
Patchwork_20916: 533fe7f4d344374c1bc87c5862a3c484974327ad @ git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
533fe7f4d344 drm/i915/edp: use MSO pixel overlap from DisplayID data
8d04ff6612d7 drm/i915/edp: postpone MSO init until after EDID read
5b93f3332ae5 drm/edid: parse the DisplayID v2.0 VESA vendor block for MSO
015c7a3f599e drm/displayid: add DisplayID v2.0 data blocks and primary use cases
9460c37da4ef drm/displayid: re-align data block macros
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20916/index.html
[-- Attachment #2: Type: text/html, Size: 4998 bytes --]
^ permalink raw reply [flat|nested] 23+ messages in thread
* Re: [PATCH 3/5] drm/edid: parse the DisplayID v2.0 VESA vendor block for MSO
2021-08-30 10:29 ` [Intel-gfx] " Jani Nikula
@ 2021-08-30 15:10 ` Ville Syrjälä
-1 siblings, 0 replies; 23+ messages in thread
From: Ville Syrjälä @ 2021-08-30 15:10 UTC (permalink / raw)
To: Jani Nikula; +Cc: intel-gfx, dri-devel
On Mon, Aug 30, 2021 at 01:29:01PM +0300, Jani Nikula wrote:
> The VESA Organization Vendor-Specific Data Block, defined in VESA
> DisplayID Standard v2.0, specifies the eDP Multi-SST Operation (MSO)
> stream count and segment pixel overlap.
>
> DisplayID v1.3 has Appendix B: DisplayID as an EDID Extension,
> describing how DisplayID sections may be embedded in EDID extension
> blocks. DisplayID v2.0 does not have such a section, perhaps implying
> that DisplayID v2.0 data should not be included in EDID extensions, but
> rather in a "pure" DisplayID structure at its own DDC address pair
> A4h/A5h, as described in VESA E-DDC Standard v1.3 chapter 3.
>
> However, in practice, displays out in the field have embedded DisplayID
> v2.0 data blocks in EDID extensions, including, in particular, some eDP
> MSO displays, where a pure DisplayID structure is not available at all.
>
> Parse the MSO data from the DisplayID data block. Do it as part of
> drm_add_display_info(), extending it to parse also DisplayID data to
> avoid requiring extra calls to update the information.
>
> Signed-off-by: Jani Nikula <jani.nikula@intel.com>
> ---
> drivers/gpu/drm/drm_edid.c | 63 +++++++++++++++++++++++++++++++++++++
> include/drm/drm_connector.h | 12 +++++++
> include/drm/drm_displayid.h | 11 +++++++
> 3 files changed, 86 insertions(+)
>
> diff --git a/drivers/gpu/drm/drm_edid.c b/drivers/gpu/drm/drm_edid.c
> index 6325877c5fd6..7e8083068f3f 100644
> --- a/drivers/gpu/drm/drm_edid.c
> +++ b/drivers/gpu/drm/drm_edid.c
> @@ -28,6 +28,7 @@
> * DEALINGS IN THE SOFTWARE.
> */
>
> +#include <linux/bitfield.h>
> #include <linux/hdmi.h>
> #include <linux/i2c.h>
> #include <linux/kernel.h>
> @@ -5148,6 +5149,62 @@ void drm_get_monitor_range(struct drm_connector *connector,
> info->monitor_range.max_vfreq);
> }
>
> +static void drm_parse_vesa_mso_data(struct drm_connector *connector,
> + const struct displayid_block *block)
> +{
> + struct displayid_vesa_vendor_specific_block *vesa =
> + (struct displayid_vesa_vendor_specific_block *)block;
> + struct drm_display_info *info = &connector->display_info;
> +
> + if (sizeof(*vesa) != sizeof(*block) + block->num_bytes) {
> + drm_dbg_kms(connector->dev, "Unexpected VESA vendor block size\n");
> + return;
> + }
> +
> + switch (FIELD_GET(DISPLAYID_VESA_MSO_MODE, vesa->mso)) {
> + default:
> + drm_dbg_kms(connector->dev, "Reserved MSO mode value\n");
> + fallthrough;
> + case 0:
> + info->mso_stream_count = 0;
> + break;
> + case 1:
> + info->mso_stream_count = 2; /* 2 or 4 links */
> + break;
> + case 2:
> + info->mso_stream_count = 4; /* 4 links */
> + break;
> + }
> +
> + if (!info->mso_stream_count) {
> + info->mso_pixel_overlap = 0;
> + return;
> + }
> +
> + info->mso_pixel_overlap = FIELD_GET(DISPLAYID_VESA_MSO_OVERLAP, vesa->mso);
> + if (info->mso_pixel_overlap > 8) {
> + drm_dbg_kms(connector->dev, "Reserved MSO pixel overlap value %u\n",
> + info->mso_pixel_overlap);
> + info->mso_pixel_overlap = 8;
> + }
> +
> + drm_dbg_kms(connector->dev, "MSO stream count %u, pixel overlap %u\n",
> + info->mso_stream_count, info->mso_pixel_overlap);
> +}
> +
> +static void drm_update_mso(struct drm_connector *connector, const struct edid *edid)
> +{
> + const struct displayid_block *block;
> + struct displayid_iter iter;
> +
> + displayid_iter_edid_begin(edid, &iter);
> + displayid_iter_for_each(block, &iter) {
> + if (block->tag == DATA_BLOCK_2_VENDOR_SPECIFIC)
Don't we need to check the OUI to make sure the block is the right
type? I don't have the v2 spec at hand atm, but I presume a vendor
specific block could contain all kinds of different things?
> + drm_parse_vesa_mso_data(connector, block);
> + }
> + displayid_iter_end(&iter);
> +}
> +
> /* A connector has no EDID information, so we've got no EDID to compute quirks from. Reset
> * all of the values which would have been set from EDID
> */
> @@ -5171,6 +5228,9 @@ drm_reset_display_info(struct drm_connector *connector)
>
> info->non_desktop = 0;
> memset(&info->monitor_range, 0, sizeof(info->monitor_range));
> +
> + info->mso_stream_count = 0;
> + info->mso_pixel_overlap = 0;
> }
>
> u32 drm_add_display_info(struct drm_connector *connector, const struct edid *edid)
> @@ -5249,6 +5309,9 @@ u32 drm_add_display_info(struct drm_connector *connector, const struct edid *edi
> info->color_formats |= DRM_COLOR_FORMAT_YCRCB444;
> if (edid->features & DRM_EDID_FEATURE_RGB_YCRCB422)
> info->color_formats |= DRM_COLOR_FORMAT_YCRCB422;
> +
> + drm_update_mso(connector, edid);
> +
> return quirks;
> }
>
> diff --git a/include/drm/drm_connector.h b/include/drm/drm_connector.h
> index 79fa34e5ccdb..379746d3266f 100644
> --- a/include/drm/drm_connector.h
> +++ b/include/drm/drm_connector.h
> @@ -590,6 +590,18 @@ struct drm_display_info {
> * @monitor_range: Frequency range supported by monitor range descriptor
> */
> struct drm_monitor_range_info monitor_range;
> +
> + /**
> + * @mso_stream_count: eDP Multi-SST Operation (MSO) stream count from
> + * the DisplayID VESA vendor block. 0 for conventional Single-Stream
> + * Transport (SST), or 2 or 4 MSO streams.
> + */
> + u8 mso_stream_count;
> +
> + /**
> + * @mso_pixel_overlap: eDP MSO segment pixel overlap, 0-8 pixels.
> + */
> + u8 mso_pixel_overlap;
> };
>
> int drm_display_info_set_bus_formats(struct drm_display_info *info,
> diff --git a/include/drm/drm_displayid.h b/include/drm/drm_displayid.h
> index 79771091771a..b18611e016a2 100644
> --- a/include/drm/drm_displayid.h
> +++ b/include/drm/drm_displayid.h
> @@ -23,6 +23,7 @@
> #define DRM_DISPLAYID_H
>
> #include <linux/types.h>
> +#include <linux/bits.h>
>
> struct edid;
>
> @@ -126,6 +127,16 @@ struct displayid_detailed_timing_block {
> struct displayid_detailed_timings_1 timings[];
> };
>
> +#define DISPLAYID_VESA_MSO_OVERLAP GENMASK(3, 0)
> +#define DISPLAYID_VESA_MSO_MODE GENMASK(6, 5)
> +
> +struct displayid_vesa_vendor_specific_block {
> + struct displayid_block base;
> + u8 oui[3];
> + u8 data_structure_type;
> + u8 mso;
> +} __packed;
> +
> /* DisplayID iteration */
> struct displayid_iter {
> const struct edid *edid;
> --
> 2.20.1
--
Ville Syrjälä
Intel
^ permalink raw reply [flat|nested] 23+ messages in thread
* Re: [Intel-gfx] [PATCH 3/5] drm/edid: parse the DisplayID v2.0 VESA vendor block for MSO
@ 2021-08-30 15:10 ` Ville Syrjälä
0 siblings, 0 replies; 23+ messages in thread
From: Ville Syrjälä @ 2021-08-30 15:10 UTC (permalink / raw)
To: Jani Nikula; +Cc: intel-gfx, dri-devel
On Mon, Aug 30, 2021 at 01:29:01PM +0300, Jani Nikula wrote:
> The VESA Organization Vendor-Specific Data Block, defined in VESA
> DisplayID Standard v2.0, specifies the eDP Multi-SST Operation (MSO)
> stream count and segment pixel overlap.
>
> DisplayID v1.3 has Appendix B: DisplayID as an EDID Extension,
> describing how DisplayID sections may be embedded in EDID extension
> blocks. DisplayID v2.0 does not have such a section, perhaps implying
> that DisplayID v2.0 data should not be included in EDID extensions, but
> rather in a "pure" DisplayID structure at its own DDC address pair
> A4h/A5h, as described in VESA E-DDC Standard v1.3 chapter 3.
>
> However, in practice, displays out in the field have embedded DisplayID
> v2.0 data blocks in EDID extensions, including, in particular, some eDP
> MSO displays, where a pure DisplayID structure is not available at all.
>
> Parse the MSO data from the DisplayID data block. Do it as part of
> drm_add_display_info(), extending it to parse also DisplayID data to
> avoid requiring extra calls to update the information.
>
> Signed-off-by: Jani Nikula <jani.nikula@intel.com>
> ---
> drivers/gpu/drm/drm_edid.c | 63 +++++++++++++++++++++++++++++++++++++
> include/drm/drm_connector.h | 12 +++++++
> include/drm/drm_displayid.h | 11 +++++++
> 3 files changed, 86 insertions(+)
>
> diff --git a/drivers/gpu/drm/drm_edid.c b/drivers/gpu/drm/drm_edid.c
> index 6325877c5fd6..7e8083068f3f 100644
> --- a/drivers/gpu/drm/drm_edid.c
> +++ b/drivers/gpu/drm/drm_edid.c
> @@ -28,6 +28,7 @@
> * DEALINGS IN THE SOFTWARE.
> */
>
> +#include <linux/bitfield.h>
> #include <linux/hdmi.h>
> #include <linux/i2c.h>
> #include <linux/kernel.h>
> @@ -5148,6 +5149,62 @@ void drm_get_monitor_range(struct drm_connector *connector,
> info->monitor_range.max_vfreq);
> }
>
> +static void drm_parse_vesa_mso_data(struct drm_connector *connector,
> + const struct displayid_block *block)
> +{
> + struct displayid_vesa_vendor_specific_block *vesa =
> + (struct displayid_vesa_vendor_specific_block *)block;
> + struct drm_display_info *info = &connector->display_info;
> +
> + if (sizeof(*vesa) != sizeof(*block) + block->num_bytes) {
> + drm_dbg_kms(connector->dev, "Unexpected VESA vendor block size\n");
> + return;
> + }
> +
> + switch (FIELD_GET(DISPLAYID_VESA_MSO_MODE, vesa->mso)) {
> + default:
> + drm_dbg_kms(connector->dev, "Reserved MSO mode value\n");
> + fallthrough;
> + case 0:
> + info->mso_stream_count = 0;
> + break;
> + case 1:
> + info->mso_stream_count = 2; /* 2 or 4 links */
> + break;
> + case 2:
> + info->mso_stream_count = 4; /* 4 links */
> + break;
> + }
> +
> + if (!info->mso_stream_count) {
> + info->mso_pixel_overlap = 0;
> + return;
> + }
> +
> + info->mso_pixel_overlap = FIELD_GET(DISPLAYID_VESA_MSO_OVERLAP, vesa->mso);
> + if (info->mso_pixel_overlap > 8) {
> + drm_dbg_kms(connector->dev, "Reserved MSO pixel overlap value %u\n",
> + info->mso_pixel_overlap);
> + info->mso_pixel_overlap = 8;
> + }
> +
> + drm_dbg_kms(connector->dev, "MSO stream count %u, pixel overlap %u\n",
> + info->mso_stream_count, info->mso_pixel_overlap);
> +}
> +
> +static void drm_update_mso(struct drm_connector *connector, const struct edid *edid)
> +{
> + const struct displayid_block *block;
> + struct displayid_iter iter;
> +
> + displayid_iter_edid_begin(edid, &iter);
> + displayid_iter_for_each(block, &iter) {
> + if (block->tag == DATA_BLOCK_2_VENDOR_SPECIFIC)
Don't we need to check the OUI to make sure the block is the right
type? I don't have the v2 spec at hand atm, but I presume a vendor
specific block could contain all kinds of different things?
> + drm_parse_vesa_mso_data(connector, block);
> + }
> + displayid_iter_end(&iter);
> +}
> +
> /* A connector has no EDID information, so we've got no EDID to compute quirks from. Reset
> * all of the values which would have been set from EDID
> */
> @@ -5171,6 +5228,9 @@ drm_reset_display_info(struct drm_connector *connector)
>
> info->non_desktop = 0;
> memset(&info->monitor_range, 0, sizeof(info->monitor_range));
> +
> + info->mso_stream_count = 0;
> + info->mso_pixel_overlap = 0;
> }
>
> u32 drm_add_display_info(struct drm_connector *connector, const struct edid *edid)
> @@ -5249,6 +5309,9 @@ u32 drm_add_display_info(struct drm_connector *connector, const struct edid *edi
> info->color_formats |= DRM_COLOR_FORMAT_YCRCB444;
> if (edid->features & DRM_EDID_FEATURE_RGB_YCRCB422)
> info->color_formats |= DRM_COLOR_FORMAT_YCRCB422;
> +
> + drm_update_mso(connector, edid);
> +
> return quirks;
> }
>
> diff --git a/include/drm/drm_connector.h b/include/drm/drm_connector.h
> index 79fa34e5ccdb..379746d3266f 100644
> --- a/include/drm/drm_connector.h
> +++ b/include/drm/drm_connector.h
> @@ -590,6 +590,18 @@ struct drm_display_info {
> * @monitor_range: Frequency range supported by monitor range descriptor
> */
> struct drm_monitor_range_info monitor_range;
> +
> + /**
> + * @mso_stream_count: eDP Multi-SST Operation (MSO) stream count from
> + * the DisplayID VESA vendor block. 0 for conventional Single-Stream
> + * Transport (SST), or 2 or 4 MSO streams.
> + */
> + u8 mso_stream_count;
> +
> + /**
> + * @mso_pixel_overlap: eDP MSO segment pixel overlap, 0-8 pixels.
> + */
> + u8 mso_pixel_overlap;
> };
>
> int drm_display_info_set_bus_formats(struct drm_display_info *info,
> diff --git a/include/drm/drm_displayid.h b/include/drm/drm_displayid.h
> index 79771091771a..b18611e016a2 100644
> --- a/include/drm/drm_displayid.h
> +++ b/include/drm/drm_displayid.h
> @@ -23,6 +23,7 @@
> #define DRM_DISPLAYID_H
>
> #include <linux/types.h>
> +#include <linux/bits.h>
>
> struct edid;
>
> @@ -126,6 +127,16 @@ struct displayid_detailed_timing_block {
> struct displayid_detailed_timings_1 timings[];
> };
>
> +#define DISPLAYID_VESA_MSO_OVERLAP GENMASK(3, 0)
> +#define DISPLAYID_VESA_MSO_MODE GENMASK(6, 5)
> +
> +struct displayid_vesa_vendor_specific_block {
> + struct displayid_block base;
> + u8 oui[3];
> + u8 data_structure_type;
> + u8 mso;
> +} __packed;
> +
> /* DisplayID iteration */
> struct displayid_iter {
> const struct edid *edid;
> --
> 2.20.1
--
Ville Syrjälä
Intel
^ permalink raw reply [flat|nested] 23+ messages in thread
* [Intel-gfx] ✓ Fi.CI.IGT: success for drm/displayid: VESA vendor block and drm/i915 MSO use of it
2021-08-30 10:28 ` [Intel-gfx] " Jani Nikula
` (7 preceding siblings ...)
(?)
@ 2021-08-30 15:26 ` Patchwork
-1 siblings, 0 replies; 23+ messages in thread
From: Patchwork @ 2021-08-30 15:26 UTC (permalink / raw)
To: Jani Nikula; +Cc: intel-gfx
[-- Attachment #1: Type: text/plain, Size: 30282 bytes --]
== Series Details ==
Series: drm/displayid: VESA vendor block and drm/i915 MSO use of it
URL : https://patchwork.freedesktop.org/series/94161/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_10536_full -> Patchwork_20916_full
====================================================
Summary
-------
**SUCCESS**
No regressions found.
Known issues
------------
Here are the changes found in Patchwork_20916_full that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@gem_exec_fair@basic-deadline:
- shard-glk: NOTRUN -> [FAIL][1] ([i915#2846])
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20916/shard-glk6/igt@gem_exec_fair@basic-deadline.html
* igt@gem_exec_fair@basic-flow@rcs0:
- shard-skl: NOTRUN -> [SKIP][2] ([fdo#109271]) +85 similar issues
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20916/shard-skl3/igt@gem_exec_fair@basic-flow@rcs0.html
* igt@gem_exec_fair@basic-pace-solo@rcs0:
- shard-glk: [PASS][3] -> [FAIL][4] ([i915#2842])
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10536/shard-glk6/igt@gem_exec_fair@basic-pace-solo@rcs0.html
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20916/shard-glk7/igt@gem_exec_fair@basic-pace-solo@rcs0.html
* igt@gem_exec_suspend@basic-s3:
- shard-skl: [PASS][5] -> [INCOMPLETE][6] ([i915#198])
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10536/shard-skl4/igt@gem_exec_suspend@basic-s3.html
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20916/shard-skl5/igt@gem_exec_suspend@basic-s3.html
* igt@gem_exec_whisper@basic-contexts-priority-all:
- shard-glk: [PASS][7] -> [DMESG-WARN][8] ([i915#118] / [i915#95])
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10536/shard-glk4/igt@gem_exec_whisper@basic-contexts-priority-all.html
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20916/shard-glk6/igt@gem_exec_whisper@basic-contexts-priority-all.html
* igt@gem_huc_copy@huc-copy:
- shard-apl: NOTRUN -> [SKIP][9] ([fdo#109271] / [i915#2190])
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20916/shard-apl1/igt@gem_huc_copy@huc-copy.html
* igt@gem_pwrite@basic-exhaustion:
- shard-snb: NOTRUN -> [WARN][10] ([i915#2658])
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20916/shard-snb5/igt@gem_pwrite@basic-exhaustion.html
* igt@gem_userptr_blits@vma-merge:
- shard-glk: NOTRUN -> [FAIL][11] ([i915#3318])
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20916/shard-glk8/igt@gem_userptr_blits@vma-merge.html
* igt@gen7_exec_parse@basic-allocation:
- shard-glk: NOTRUN -> [SKIP][12] ([fdo#109271]) +77 similar issues
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20916/shard-glk6/igt@gen7_exec_parse@basic-allocation.html
* igt@i915_pm_dc@dc6-psr:
- shard-skl: NOTRUN -> [FAIL][13] ([i915#454])
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20916/shard-skl3/igt@i915_pm_dc@dc6-psr.html
* igt@i915_suspend@sysfs-reader:
- shard-kbl: [PASS][14] -> [DMESG-WARN][15] ([i915#180])
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10536/shard-kbl3/igt@i915_suspend@sysfs-reader.html
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20916/shard-kbl7/igt@i915_suspend@sysfs-reader.html
* igt@kms_big_fb@x-tiled-64bpp-rotate-0:
- shard-iclb: [PASS][16] -> [DMESG-WARN][17] ([i915#3621])
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10536/shard-iclb4/igt@kms_big_fb@x-tiled-64bpp-rotate-0.html
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20916/shard-iclb1/igt@kms_big_fb@x-tiled-64bpp-rotate-0.html
* igt@kms_big_fb@x-tiled-max-hw-stride-32bpp-rotate-0-hflip:
- shard-apl: NOTRUN -> [SKIP][18] ([fdo#109271] / [i915#3777]) +1 similar issue
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20916/shard-apl3/igt@kms_big_fb@x-tiled-max-hw-stride-32bpp-rotate-0-hflip.html
* igt@kms_big_fb@x-tiled-max-hw-stride-32bpp-rotate-180-hflip:
- shard-skl: NOTRUN -> [SKIP][19] ([fdo#109271] / [i915#3777])
[19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20916/shard-skl7/igt@kms_big_fb@x-tiled-max-hw-stride-32bpp-rotate-180-hflip.html
- shard-kbl: NOTRUN -> [SKIP][20] ([fdo#109271] / [i915#3777])
[20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20916/shard-kbl6/igt@kms_big_fb@x-tiled-max-hw-stride-32bpp-rotate-180-hflip.html
* igt@kms_big_fb@y-tiled-max-hw-stride-64bpp-rotate-180-hflip:
- shard-glk: NOTRUN -> [SKIP][21] ([fdo#109271] / [i915#3777])
[21]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20916/shard-glk8/igt@kms_big_fb@y-tiled-max-hw-stride-64bpp-rotate-180-hflip.html
* igt@kms_big_fb@yf-tiled-max-hw-stride-64bpp-rotate-0-hflip:
- shard-tglb: NOTRUN -> [SKIP][22] ([fdo#111615])
[22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20916/shard-tglb1/igt@kms_big_fb@yf-tiled-max-hw-stride-64bpp-rotate-0-hflip.html
* igt@kms_ccs@pipe-a-crc-sprite-planes-basic-y_tiled_gen12_mc_ccs:
- shard-glk: NOTRUN -> [SKIP][23] ([fdo#109271] / [i915#3886]) +2 similar issues
[23]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20916/shard-glk8/igt@kms_ccs@pipe-a-crc-sprite-planes-basic-y_tiled_gen12_mc_ccs.html
* igt@kms_ccs@pipe-a-crc-sprite-planes-basic-y_tiled_gen12_rc_ccs_cc:
- shard-kbl: NOTRUN -> [SKIP][24] ([fdo#109271] / [i915#3886]) +4 similar issues
[24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20916/shard-kbl6/igt@kms_ccs@pipe-a-crc-sprite-planes-basic-y_tiled_gen12_rc_ccs_cc.html
* igt@kms_ccs@pipe-a-missing-ccs-buffer-y_tiled_gen12_rc_ccs_cc:
- shard-apl: NOTRUN -> [SKIP][25] ([fdo#109271] / [i915#3886]) +7 similar issues
[25]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20916/shard-apl2/igt@kms_ccs@pipe-a-missing-ccs-buffer-y_tiled_gen12_rc_ccs_cc.html
* igt@kms_ccs@pipe-b-crc-primary-rotation-180-yf_tiled_ccs:
- shard-tglb: NOTRUN -> [SKIP][26] ([i915#3689]) +1 similar issue
[26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20916/shard-tglb1/igt@kms_ccs@pipe-b-crc-primary-rotation-180-yf_tiled_ccs.html
* igt@kms_ccs@pipe-c-crc-primary-rotation-180-y_tiled_gen12_mc_ccs:
- shard-tglb: NOTRUN -> [SKIP][27] ([i915#3689] / [i915#3886])
[27]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20916/shard-tglb8/igt@kms_ccs@pipe-c-crc-primary-rotation-180-y_tiled_gen12_mc_ccs.html
* igt@kms_ccs@pipe-c-crc-sprite-planes-basic-y_tiled_gen12_mc_ccs:
- shard-skl: NOTRUN -> [SKIP][28] ([fdo#109271] / [i915#3886]) +5 similar issues
[28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20916/shard-skl7/igt@kms_ccs@pipe-c-crc-sprite-planes-basic-y_tiled_gen12_mc_ccs.html
* igt@kms_ccs@pipe-d-missing-ccs-buffer-y_tiled_ccs:
- shard-iclb: NOTRUN -> [SKIP][29] ([fdo#109278]) +1 similar issue
[29]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20916/shard-iclb5/igt@kms_ccs@pipe-d-missing-ccs-buffer-y_tiled_ccs.html
* igt@kms_chamelium@hdmi-hpd-enable-disable-mode:
- shard-snb: NOTRUN -> [SKIP][30] ([fdo#109271] / [fdo#111827]) +5 similar issues
[30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20916/shard-snb5/igt@kms_chamelium@hdmi-hpd-enable-disable-mode.html
* igt@kms_chamelium@vga-frame-dump:
- shard-glk: NOTRUN -> [SKIP][31] ([fdo#109271] / [fdo#111827]) +5 similar issues
[31]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20916/shard-glk8/igt@kms_chamelium@vga-frame-dump.html
* igt@kms_chamelium@vga-hpd-for-each-pipe:
- shard-kbl: NOTRUN -> [SKIP][32] ([fdo#109271] / [fdo#111827]) +12 similar issues
[32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20916/shard-kbl6/igt@kms_chamelium@vga-hpd-for-each-pipe.html
- shard-skl: NOTRUN -> [SKIP][33] ([fdo#109271] / [fdo#111827]) +9 similar issues
[33]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20916/shard-skl7/igt@kms_chamelium@vga-hpd-for-each-pipe.html
* igt@kms_color@pipe-b-ctm-red-to-blue:
- shard-skl: NOTRUN -> [DMESG-WARN][34] ([i915#1982])
[34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20916/shard-skl7/igt@kms_color@pipe-b-ctm-red-to-blue.html
* igt@kms_color_chamelium@pipe-c-ctm-0-25:
- shard-apl: NOTRUN -> [SKIP][35] ([fdo#109271] / [fdo#111827]) +17 similar issues
[35]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20916/shard-apl1/igt@kms_color_chamelium@pipe-c-ctm-0-25.html
* igt@kms_color_chamelium@pipe-c-degamma:
- shard-iclb: NOTRUN -> [SKIP][36] ([fdo#109284] / [fdo#111827])
[36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20916/shard-iclb8/igt@kms_color_chamelium@pipe-c-degamma.html
* igt@kms_color_chamelium@pipe-d-ctm-blue-to-red:
- shard-tglb: NOTRUN -> [SKIP][37] ([fdo#109284] / [fdo#111827]) +3 similar issues
[37]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20916/shard-tglb1/igt@kms_color_chamelium@pipe-d-ctm-blue-to-red.html
* igt@kms_content_protection@content_type_change:
- shard-tglb: NOTRUN -> [SKIP][38] ([fdo#111828])
[38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20916/shard-tglb1/igt@kms_content_protection@content_type_change.html
* igt@kms_content_protection@legacy:
- shard-apl: NOTRUN -> [TIMEOUT][39] ([i915#1319])
[39]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20916/shard-apl2/igt@kms_content_protection@legacy.html
* igt@kms_content_protection@lic:
- shard-kbl: NOTRUN -> [TIMEOUT][40] ([i915#1319])
[40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20916/shard-kbl6/igt@kms_content_protection@lic.html
* igt@kms_cursor_crc@pipe-b-cursor-32x10-random:
- shard-kbl: NOTRUN -> [SKIP][41] ([fdo#109271]) +90 similar issues
[41]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20916/shard-kbl4/igt@kms_cursor_crc@pipe-b-cursor-32x10-random.html
* igt@kms_cursor_crc@pipe-d-cursor-32x10-onscreen:
- shard-tglb: NOTRUN -> [SKIP][42] ([i915#3359])
[42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20916/shard-tglb1/igt@kms_cursor_crc@pipe-d-cursor-32x10-onscreen.html
* igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions:
- shard-skl: [PASS][43] -> [FAIL][44] ([i915#2346])
[43]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10536/shard-skl10/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions.html
[44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20916/shard-skl3/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions.html
* igt@kms_fbcon_fbt@fbc-suspend:
- shard-kbl: [PASS][45] -> [INCOMPLETE][46] ([i915#155] / [i915#180] / [i915#636])
[45]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10536/shard-kbl3/igt@kms_fbcon_fbt@fbc-suspend.html
[46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20916/shard-kbl7/igt@kms_fbcon_fbt@fbc-suspend.html
* igt@kms_flip@2x-plain-flip:
- shard-iclb: NOTRUN -> [SKIP][47] ([fdo#109274])
[47]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20916/shard-iclb8/igt@kms_flip@2x-plain-flip.html
* igt@kms_flip@2x-plain-flip-fb-recreate-interruptible@ab-hdmi-a1-hdmi-a2:
- shard-glk: [PASS][48] -> [FAIL][49] ([i915#2122]) +1 similar issue
[48]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10536/shard-glk8/igt@kms_flip@2x-plain-flip-fb-recreate-interruptible@ab-hdmi-a1-hdmi-a2.html
[49]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20916/shard-glk4/igt@kms_flip@2x-plain-flip-fb-recreate-interruptible@ab-hdmi-a1-hdmi-a2.html
* igt@kms_flip@2x-plain-flip-fb-recreate@bc-hdmi-a1-hdmi-a2:
- shard-glk: NOTRUN -> [FAIL][50] ([i915#2122])
[50]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20916/shard-glk6/igt@kms_flip@2x-plain-flip-fb-recreate@bc-hdmi-a1-hdmi-a2.html
* igt@kms_flip@flip-vs-suspend@c-dp1:
- shard-kbl: [PASS][51] -> [INCOMPLETE][52] ([i915#636])
[51]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10536/shard-kbl4/igt@kms_flip@flip-vs-suspend@c-dp1.html
[52]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20916/shard-kbl2/igt@kms_flip@flip-vs-suspend@c-dp1.html
* igt@kms_flip@plain-flip-ts-check-interruptible@a-edp1:
- shard-skl: [PASS][53] -> [FAIL][54] ([i915#2122])
[53]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10536/shard-skl7/igt@kms_flip@plain-flip-ts-check-interruptible@a-edp1.html
[54]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20916/shard-skl9/igt@kms_flip@plain-flip-ts-check-interruptible@a-edp1.html
* igt@kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-spr-indfb-draw-pwrite:
- shard-iclb: NOTRUN -> [SKIP][55] ([fdo#109280]) +2 similar issues
[55]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20916/shard-iclb5/igt@kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-spr-indfb-draw-pwrite.html
* igt@kms_frontbuffer_tracking@psr-1p-primscrn-cur-indfb-onoff:
- shard-snb: NOTRUN -> [SKIP][56] ([fdo#109271]) +71 similar issues
[56]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20916/shard-snb5/igt@kms_frontbuffer_tracking@psr-1p-primscrn-cur-indfb-onoff.html
* igt@kms_frontbuffer_tracking@psr-2p-primscrn-spr-indfb-onoff:
- shard-tglb: NOTRUN -> [SKIP][57] ([fdo#111825]) +5 similar issues
[57]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20916/shard-tglb8/igt@kms_frontbuffer_tracking@psr-2p-primscrn-spr-indfb-onoff.html
* igt@kms_hdr@bpc-switch:
- shard-skl: [PASS][58] -> [FAIL][59] ([i915#1188])
[58]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10536/shard-skl5/igt@kms_hdr@bpc-switch.html
[59]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20916/shard-skl8/igt@kms_hdr@bpc-switch.html
* igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-d:
- shard-glk: NOTRUN -> [SKIP][60] ([fdo#109271] / [i915#533])
[60]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20916/shard-glk6/igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-d.html
* igt@kms_pipe_crc_basic@nonblocking-crc-pipe-d-frame-sequence:
- shard-kbl: NOTRUN -> [SKIP][61] ([fdo#109271] / [i915#533])
[61]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20916/shard-kbl6/igt@kms_pipe_crc_basic@nonblocking-crc-pipe-d-frame-sequence.html
* igt@kms_plane@plane-panning-bottom-right-suspend@pipe-a-planes:
- shard-apl: NOTRUN -> [DMESG-WARN][62] ([i915#180]) +1 similar issue
[62]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20916/shard-apl6/igt@kms_plane@plane-panning-bottom-right-suspend@pipe-a-planes.html
* igt@kms_plane_alpha_blend@pipe-a-alpha-opaque-fb:
- shard-apl: NOTRUN -> [FAIL][63] ([fdo#108145] / [i915#265])
[63]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20916/shard-apl3/igt@kms_plane_alpha_blend@pipe-a-alpha-opaque-fb.html
* igt@kms_plane_alpha_blend@pipe-a-constant-alpha-max:
- shard-glk: NOTRUN -> [FAIL][64] ([fdo#108145] / [i915#265])
[64]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20916/shard-glk6/igt@kms_plane_alpha_blend@pipe-a-constant-alpha-max.html
* igt@kms_plane_alpha_blend@pipe-c-alpha-transparent-fb:
- shard-kbl: NOTRUN -> [FAIL][65] ([i915#265])
[65]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20916/shard-kbl6/igt@kms_plane_alpha_blend@pipe-c-alpha-transparent-fb.html
- shard-skl: NOTRUN -> [FAIL][66] ([i915#265])
[66]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20916/shard-skl7/igt@kms_plane_alpha_blend@pipe-c-alpha-transparent-fb.html
* igt@kms_plane_alpha_blend@pipe-c-coverage-7efc:
- shard-skl: [PASS][67] -> [FAIL][68] ([fdo#108145] / [i915#265]) +1 similar issue
[67]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10536/shard-skl5/igt@kms_plane_alpha_blend@pipe-c-coverage-7efc.html
[68]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20916/shard-skl8/igt@kms_plane_alpha_blend@pipe-c-coverage-7efc.html
* igt@kms_plane_scaling@scaler-with-clipping-clamping@pipe-c-scaler-with-clipping-clamping:
- shard-kbl: NOTRUN -> [SKIP][69] ([fdo#109271] / [i915#2733])
[69]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20916/shard-kbl6/igt@kms_plane_scaling@scaler-with-clipping-clamping@pipe-c-scaler-with-clipping-clamping.html
* igt@kms_psr2_sf@overlay-plane-update-sf-dmg-area-3:
- shard-tglb: NOTRUN -> [SKIP][70] ([i915#2920])
[70]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20916/shard-tglb1/igt@kms_psr2_sf@overlay-plane-update-sf-dmg-area-3.html
* igt@kms_psr2_sf@overlay-primary-update-sf-dmg-area-1:
- shard-skl: NOTRUN -> [SKIP][71] ([fdo#109271] / [i915#658]) +1 similar issue
[71]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20916/shard-skl7/igt@kms_psr2_sf@overlay-primary-update-sf-dmg-area-1.html
- shard-kbl: NOTRUN -> [SKIP][72] ([fdo#109271] / [i915#658]) +2 similar issues
[72]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20916/shard-kbl6/igt@kms_psr2_sf@overlay-primary-update-sf-dmg-area-1.html
* igt@kms_psr2_sf@primary-plane-update-sf-dmg-area-1:
- shard-glk: NOTRUN -> [SKIP][73] ([fdo#109271] / [i915#658]) +1 similar issue
[73]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20916/shard-glk8/igt@kms_psr2_sf@primary-plane-update-sf-dmg-area-1.html
* igt@kms_psr2_sf@primary-plane-update-sf-dmg-area-5:
- shard-apl: NOTRUN -> [SKIP][74] ([fdo#109271] / [i915#658]) +4 similar issues
[74]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20916/shard-apl1/igt@kms_psr2_sf@primary-plane-update-sf-dmg-area-5.html
* igt@kms_psr2_su@page_flip:
- shard-tglb: NOTRUN -> [SKIP][75] ([i915#1911])
[75]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20916/shard-tglb1/igt@kms_psr2_su@page_flip.html
- shard-iclb: NOTRUN -> [SKIP][76] ([fdo#109642] / [fdo#111068] / [i915#658])
[76]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20916/shard-iclb5/igt@kms_psr2_su@page_flip.html
* igt@kms_psr@psr2_cursor_render:
- shard-iclb: [PASS][77] -> [SKIP][78] ([fdo#109441]) +1 similar issue
[77]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10536/shard-iclb2/igt@kms_psr@psr2_cursor_render.html
[78]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20916/shard-iclb3/igt@kms_psr@psr2_cursor_render.html
* igt@kms_sysfs_edid_timing:
- shard-apl: NOTRUN -> [FAIL][79] ([IGT#2])
[79]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20916/shard-apl1/igt@kms_sysfs_edid_timing.html
* igt@kms_vblank@pipe-a-ts-continuation-suspend:
- shard-kbl: [PASS][80] -> [DMESG-WARN][81] ([i915#180] / [i915#295])
[80]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10536/shard-kbl7/igt@kms_vblank@pipe-a-ts-continuation-suspend.html
[81]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20916/shard-kbl7/igt@kms_vblank@pipe-a-ts-continuation-suspend.html
* igt@kms_vblank@pipe-d-wait-forked-hang:
- shard-apl: NOTRUN -> [SKIP][82] ([fdo#109271]) +154 similar issues
[82]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20916/shard-apl2/igt@kms_vblank@pipe-d-wait-forked-hang.html
* igt@kms_writeback@writeback-pixel-formats:
- shard-apl: NOTRUN -> [SKIP][83] ([fdo#109271] / [i915#2437])
[83]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20916/shard-apl3/igt@kms_writeback@writeback-pixel-formats.html
* igt@prime_nv_api@i915_nv_double_import:
- shard-tglb: NOTRUN -> [SKIP][84] ([fdo#109291])
[84]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20916/shard-tglb1/igt@prime_nv_api@i915_nv_double_import.html
* igt@prime_nv_pcopy@test1_micro:
- shard-iclb: NOTRUN -> [SKIP][85] ([fdo#109291])
[85]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20916/shard-iclb8/igt@prime_nv_pcopy@test1_micro.html
* igt@sysfs_clients@busy:
- shard-glk: NOTRUN -> [SKIP][86] ([fdo#109271] / [i915#2994])
[86]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20916/shard-glk8/igt@sysfs_clients@busy.html
* igt@sysfs_clients@recycle:
- shard-kbl: NOTRUN -> [SKIP][87] ([fdo#109271] / [i915#2994])
[87]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20916/shard-kbl6/igt@sysfs_clients@recycle.html
* igt@sysfs_clients@sema-10:
- shard-apl: NOTRUN -> [SKIP][88] ([fdo#109271] / [i915#2994])
[88]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20916/shard-apl1/igt@sysfs_clients@sema-10.html
#### Possible fixes ####
* igt@gem_ctx_isolation@preservation-s3@bcs0:
- shard-kbl: [DMESG-WARN][89] ([i915#180]) -> [PASS][90] +3 similar issues
[89]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10536/shard-kbl7/igt@gem_ctx_isolation@preservation-s3@bcs0.html
[90]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20916/shard-kbl3/igt@gem_ctx_isolation@preservation-s3@bcs0.html
* igt@gem_ctx_persistence@legacy-engines-hang@bsd:
- {shard-rkl}: [FAIL][91] ([i915#2410]) -> [PASS][92]
[91]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10536/shard-rkl-2/igt@gem_ctx_persistence@legacy-engines-hang@bsd.html
[92]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20916/shard-rkl-5/igt@gem_ctx_persistence@legacy-engines-hang@bsd.html
* igt@gem_exec_fair@basic-deadline:
- {shard-rkl}: [FAIL][93] ([i915#2846]) -> [PASS][94]
[93]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10536/shard-rkl-5/igt@gem_exec_fair@basic-deadline.html
[94]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20916/shard-rkl-1/igt@gem_exec_fair@basic-deadline.html
* igt@gem_exec_fair@basic-pace@vecs0:
- shard-kbl: [SKIP][95] ([fdo#109271]) -> [PASS][96] +2 similar issues
[95]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10536/shard-kbl4/igt@gem_exec_fair@basic-pace@vecs0.html
[96]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20916/shard-kbl2/igt@gem_exec_fair@basic-pace@vecs0.html
* igt@gem_exec_fair@basic-throttle@rcs0:
- {shard-rkl}: [FAIL][97] ([i915#2842]) -> [PASS][98] +3 similar issues
[97]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10536/shard-rkl-1/igt@gem_exec_fair@basic-throttle@rcs0.html
[98]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20916/shard-rkl-5/igt@gem_exec_fair@basic-throttle@rcs0.html
* igt@gem_exec_suspend@basic-s4-devices:
- {shard-rkl}: [INCOMPLETE][99] ([i915#3189] / [i915#3810]) -> [PASS][100]
[99]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10536/shard-rkl-5/igt@gem_exec_suspend@basic-s4-devices.html
[100]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20916/shard-rkl-1/igt@gem_exec_suspend@basic-s4-devices.html
* igt@gem_mmap_gtt@basic-wc:
- {shard-rkl}: [FAIL][101] ([i915#3830]) -> [PASS][102]
[101]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10536/shard-rkl-5/igt@gem_mmap_gtt@basic-wc.html
[102]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20916/shard-rkl-1/igt@gem_mmap_gtt@basic-wc.html
* igt@i915_selftest@live@gt_heartbeat:
- shard-tglb: [DMESG-FAIL][103] ([i915#2291] / [i915#541]) -> [PASS][104]
[103]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10536/shard-tglb2/igt@i915_selftest@live@gt_heartbeat.html
[104]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20916/shard-tglb5/igt@i915_selftest@live@gt_heartbeat.html
* igt@kms_cursor_crc@pipe-c-cursor-suspend:
- shard-skl: [INCOMPLETE][105] ([i915#300]) -> [PASS][106]
[105]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10536/shard-skl3/igt@kms_cursor_crc@pipe-c-cursor-suspend.html
[106]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20916/shard-skl3/igt@kms_cursor_crc@pipe-c-cursor-suspend.html
* igt@kms_cursor_legacy@2x-long-flip-vs-cursor-atomic:
- shard-glk: [FAIL][107] ([i915#72]) -> [PASS][108]
[107]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10536/shard-glk8/igt@kms_cursor_legacy@2x-long-flip-vs-cursor-atomic.html
[108]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20916/shard-glk4/igt@kms_cursor_legacy@2x-long-flip-vs-cursor-atomic.html
* igt@kms_flip@2x-plain-flip-fb-recreate-interruptible@bc-hdmi-a1-hdmi-a2:
- shard-glk: [FAIL][109] ([i915#2122]) -> [PASS][110]
[109]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10536/shard-glk8/igt@kms_flip@2x-plain-flip-fb-recreate-interruptible@bc-hdmi-a1-hdmi-a2.html
[110]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20916/shard-glk4/igt@kms_flip@2x-plain-flip-fb-recreate-interruptible@bc-hdmi-a1-hdmi-a2.html
* igt@kms_hdr@bpc-switch-dpms:
- shard-skl: [FAIL][111] ([i915#1188]) -> [PASS][112]
[111]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10536/shard-skl7/igt@kms_hdr@bpc-switch-dpms.html
[112]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20916/shard-skl6/igt@kms_hdr@bpc-switch-dpms.html
* igt@kms_psr@psr2_dpms:
- shard-iclb: [SKIP][113] ([fdo#109441]) -> [PASS][114] +1 similar issue
[113]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10536/shard-iclb5/igt@kms_psr@psr2_dpms.html
[114]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20916/shard-iclb2/igt@kms_psr@psr2_dpms.html
* igt@kms_vblank@pipe-a-ts-continuation-suspend:
- shard-apl: [DMESG-WARN][115] ([i915#180] / [i915#295]) -> [PASS][116]
[115]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10536/shard-apl2/igt@kms_vblank@pipe-a-ts-continuation-suspend.html
[116]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20916/shard-apl1/igt@kms_vblank@pipe-a-ts-continuation-suspend.html
* igt@perf@blocking:
- shard-skl: [FAIL][117] ([i915#1542]) -> [PASS][118] +1 similar issue
[117]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10536/shard-skl5/igt@perf@blocking.html
[118]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20916/shard-skl8/igt@perf@blocking.html
* igt@perf@polling-parameterized:
- {shard-rkl}: [FAIL][119] ([i915#1542]) -> [PASS][120] +1 similar issue
[119]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10536/shard-rkl-2/igt@perf@polling-parameterized.html
[120]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20916/shard-rkl-1/igt@perf@polling-parameterized.html
* igt@perf_pmu@busy-idle@vecs0:
- shard-skl: [DMESG-WARN][121] ([i915#1982]) -> [PASS][122] +2 similar issues
[121]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10536/shard-skl3/igt@perf_pmu@busy-idle@vecs0.html
[122]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20916/shard-skl1/igt@perf_pmu@busy-idle@vecs0.html
* igt@sysfs_timeslice_duration@timeout@vecs0:
- shard-iclb: [FAIL][123] ([i915#1755]) -> [PASS][124]
[123]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10536/shard-iclb7/igt@sysfs_timeslice_duration@timeout@vecs0.html
[124]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20916/shard-iclb4/igt@sysfs_timeslice_duration@timeout@vecs0.html
#### Warnings ####
* igt@i915_pm_rc6_residency@rc6-idle:
- shard-iclb: [WARN][125] ([i915#2684]) -> [WARN][126] ([i915#1804] / [i915#2684])
[125]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10536/shard-iclb2/igt@i915_pm_rc6_residency@rc6-idle.html
[126]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20916/shard-iclb3/igt@i915_pm_rc6_residency@rc6-idle.html
* igt@kms_cursor_crc@pipe-b-cursor-suspend:
- shard-kbl: [INCOMPLETE][127] ([i915#155]) -> [DMESG-WARN][128] ([i915#180])
[127]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10536/shard-kbl4/igt@kms_cursor_crc@pipe-b-cursor-suspend.html
[128]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20916/shard-kbl7/igt@kms_cursor_crc@pipe-b-cursor-suspend.html
* igt@kms_psr2_sf@plane-move-sf-dmg-area-0:
- shard-iclb: [SKIP][129] ([i915#2920]) -> [SKIP][130] ([i915#658]) +1 similar issue
[129]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10536/shard-iclb2/igt@kms_psr2_sf@plane-move-sf-dmg-area-0.html
[130]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20916/shard-iclb8/igt@kms_psr2_sf@plane-move-sf-dmg-area-0.html
* igt@kms_psr2_sf@primary-plane-update-sf-dmg-area-2:
- shard-iclb: [SKIP][131] ([i915#658]) -> [SKIP][132] ([i915#2920]) +1 similar issue
[131]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10536/shard-iclb5/igt@kms_psr2_sf@primary-plane-update-sf-dmg-area-2.html
[132]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20916/shard-iclb2/igt@kms_psr2_sf@primary-plane-update-sf-dmg-area-2.html
* igt@runner@aborted:
- shard-kbl: ([FAIL][133], [FAIL][134], [FAIL][135], [FAIL][136], [FAIL][137]) ([i915#1436] / [i915#180] / [i915#3002] / [i915#3363]) -> ([FAIL][138], [FAIL][139], [FAIL][140], [FAIL][141], [FAIL][142]) ([i915#180] / [i915#1814] / [i915#3002] / [i915#3363] / [i915#602] / [i915#92])
[133]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10536/shard-kbl7/igt@runner@aborted.html
[134]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10536/shard-kbl7/igt@runner@aborted.html
[135]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10536/shard-kbl7/igt@runner@aborted.html
[136]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10536/shard-kbl3/igt@runner@aborted.html
[137]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10536/shard-kbl4/igt@runner@aborted.html
[138]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20916/shard-kbl7/igt@runner@aborted.html
[139]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20916/shard-kbl7/igt@runner@aborted.html
[140]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20916/shard-kbl7/igt@runner@aborted.html
[141]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20916/shard-kbl7/igt@runner@aborted.ht
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20916/index.html
[-- Attachment #2: Type: text/html, Size: 34128 bytes --]
^ permalink raw reply [flat|nested] 23+ messages in thread
* Re: [PATCH 3/5] drm/edid: parse the DisplayID v2.0 VESA vendor block for MSO
2021-08-30 15:10 ` [Intel-gfx] " Ville Syrjälä
@ 2021-08-31 8:10 ` Jani Nikula
-1 siblings, 0 replies; 23+ messages in thread
From: Jani Nikula @ 2021-08-31 8:10 UTC (permalink / raw)
To: Ville Syrjälä; +Cc: intel-gfx, dri-devel
On Mon, 30 Aug 2021, Ville Syrjälä <ville.syrjala@linux.intel.com> wrote:
> On Mon, Aug 30, 2021 at 01:29:01PM +0300, Jani Nikula wrote:
>> The VESA Organization Vendor-Specific Data Block, defined in VESA
>> DisplayID Standard v2.0, specifies the eDP Multi-SST Operation (MSO)
>> stream count and segment pixel overlap.
>>
>> DisplayID v1.3 has Appendix B: DisplayID as an EDID Extension,
>> describing how DisplayID sections may be embedded in EDID extension
>> blocks. DisplayID v2.0 does not have such a section, perhaps implying
>> that DisplayID v2.0 data should not be included in EDID extensions, but
>> rather in a "pure" DisplayID structure at its own DDC address pair
>> A4h/A5h, as described in VESA E-DDC Standard v1.3 chapter 3.
>>
>> However, in practice, displays out in the field have embedded DisplayID
>> v2.0 data blocks in EDID extensions, including, in particular, some eDP
>> MSO displays, where a pure DisplayID structure is not available at all.
>>
>> Parse the MSO data from the DisplayID data block. Do it as part of
>> drm_add_display_info(), extending it to parse also DisplayID data to
>> avoid requiring extra calls to update the information.
>>
>> Signed-off-by: Jani Nikula <jani.nikula@intel.com>
>> ---
>> drivers/gpu/drm/drm_edid.c | 63 +++++++++++++++++++++++++++++++++++++
>> include/drm/drm_connector.h | 12 +++++++
>> include/drm/drm_displayid.h | 11 +++++++
>> 3 files changed, 86 insertions(+)
>>
>> diff --git a/drivers/gpu/drm/drm_edid.c b/drivers/gpu/drm/drm_edid.c
>> index 6325877c5fd6..7e8083068f3f 100644
>> --- a/drivers/gpu/drm/drm_edid.c
>> +++ b/drivers/gpu/drm/drm_edid.c
>> @@ -28,6 +28,7 @@
>> * DEALINGS IN THE SOFTWARE.
>> */
>>
>> +#include <linux/bitfield.h>
>> #include <linux/hdmi.h>
>> #include <linux/i2c.h>
>> #include <linux/kernel.h>
>> @@ -5148,6 +5149,62 @@ void drm_get_monitor_range(struct drm_connector *connector,
>> info->monitor_range.max_vfreq);
>> }
>>
>> +static void drm_parse_vesa_mso_data(struct drm_connector *connector,
>> + const struct displayid_block *block)
>> +{
>> + struct displayid_vesa_vendor_specific_block *vesa =
>> + (struct displayid_vesa_vendor_specific_block *)block;
>> + struct drm_display_info *info = &connector->display_info;
>> +
>> + if (sizeof(*vesa) != sizeof(*block) + block->num_bytes) {
>> + drm_dbg_kms(connector->dev, "Unexpected VESA vendor block size\n");
>> + return;
>> + }
>> +
>> + switch (FIELD_GET(DISPLAYID_VESA_MSO_MODE, vesa->mso)) {
>> + default:
>> + drm_dbg_kms(connector->dev, "Reserved MSO mode value\n");
>> + fallthrough;
>> + case 0:
>> + info->mso_stream_count = 0;
>> + break;
>> + case 1:
>> + info->mso_stream_count = 2; /* 2 or 4 links */
>> + break;
>> + case 2:
>> + info->mso_stream_count = 4; /* 4 links */
>> + break;
>> + }
>> +
>> + if (!info->mso_stream_count) {
>> + info->mso_pixel_overlap = 0;
>> + return;
>> + }
>> +
>> + info->mso_pixel_overlap = FIELD_GET(DISPLAYID_VESA_MSO_OVERLAP, vesa->mso);
>> + if (info->mso_pixel_overlap > 8) {
>> + drm_dbg_kms(connector->dev, "Reserved MSO pixel overlap value %u\n",
>> + info->mso_pixel_overlap);
>> + info->mso_pixel_overlap = 8;
>> + }
>> +
>> + drm_dbg_kms(connector->dev, "MSO stream count %u, pixel overlap %u\n",
>> + info->mso_stream_count, info->mso_pixel_overlap);
>> +}
>> +
>> +static void drm_update_mso(struct drm_connector *connector, const struct edid *edid)
>> +{
>> + const struct displayid_block *block;
>> + struct displayid_iter iter;
>> +
>> + displayid_iter_edid_begin(edid, &iter);
>> + displayid_iter_for_each(block, &iter) {
>> + if (block->tag == DATA_BLOCK_2_VENDOR_SPECIFIC)
>
> Don't we need to check the OUI to make sure the block is the right
> type? I don't have the v2 spec at hand atm, but I presume a vendor
> specific block could contain all kinds of different things?
You're right.
BR,
Jani.
>
>> + drm_parse_vesa_mso_data(connector, block);
>> + }
>> + displayid_iter_end(&iter);
>> +}
>> +
>> /* A connector has no EDID information, so we've got no EDID to compute quirks from. Reset
>> * all of the values which would have been set from EDID
>> */
>> @@ -5171,6 +5228,9 @@ drm_reset_display_info(struct drm_connector *connector)
>>
>> info->non_desktop = 0;
>> memset(&info->monitor_range, 0, sizeof(info->monitor_range));
>> +
>> + info->mso_stream_count = 0;
>> + info->mso_pixel_overlap = 0;
>> }
>>
>> u32 drm_add_display_info(struct drm_connector *connector, const struct edid *edid)
>> @@ -5249,6 +5309,9 @@ u32 drm_add_display_info(struct drm_connector *connector, const struct edid *edi
>> info->color_formats |= DRM_COLOR_FORMAT_YCRCB444;
>> if (edid->features & DRM_EDID_FEATURE_RGB_YCRCB422)
>> info->color_formats |= DRM_COLOR_FORMAT_YCRCB422;
>> +
>> + drm_update_mso(connector, edid);
>> +
>> return quirks;
>> }
>>
>> diff --git a/include/drm/drm_connector.h b/include/drm/drm_connector.h
>> index 79fa34e5ccdb..379746d3266f 100644
>> --- a/include/drm/drm_connector.h
>> +++ b/include/drm/drm_connector.h
>> @@ -590,6 +590,18 @@ struct drm_display_info {
>> * @monitor_range: Frequency range supported by monitor range descriptor
>> */
>> struct drm_monitor_range_info monitor_range;
>> +
>> + /**
>> + * @mso_stream_count: eDP Multi-SST Operation (MSO) stream count from
>> + * the DisplayID VESA vendor block. 0 for conventional Single-Stream
>> + * Transport (SST), or 2 or 4 MSO streams.
>> + */
>> + u8 mso_stream_count;
>> +
>> + /**
>> + * @mso_pixel_overlap: eDP MSO segment pixel overlap, 0-8 pixels.
>> + */
>> + u8 mso_pixel_overlap;
>> };
>>
>> int drm_display_info_set_bus_formats(struct drm_display_info *info,
>> diff --git a/include/drm/drm_displayid.h b/include/drm/drm_displayid.h
>> index 79771091771a..b18611e016a2 100644
>> --- a/include/drm/drm_displayid.h
>> +++ b/include/drm/drm_displayid.h
>> @@ -23,6 +23,7 @@
>> #define DRM_DISPLAYID_H
>>
>> #include <linux/types.h>
>> +#include <linux/bits.h>
>>
>> struct edid;
>>
>> @@ -126,6 +127,16 @@ struct displayid_detailed_timing_block {
>> struct displayid_detailed_timings_1 timings[];
>> };
>>
>> +#define DISPLAYID_VESA_MSO_OVERLAP GENMASK(3, 0)
>> +#define DISPLAYID_VESA_MSO_MODE GENMASK(6, 5)
>> +
>> +struct displayid_vesa_vendor_specific_block {
>> + struct displayid_block base;
>> + u8 oui[3];
>> + u8 data_structure_type;
>> + u8 mso;
>> +} __packed;
>> +
>> /* DisplayID iteration */
>> struct displayid_iter {
>> const struct edid *edid;
>> --
>> 2.20.1
--
Jani Nikula, Intel Open Source Graphics Center
^ permalink raw reply [flat|nested] 23+ messages in thread
* Re: [Intel-gfx] [PATCH 3/5] drm/edid: parse the DisplayID v2.0 VESA vendor block for MSO
@ 2021-08-31 8:10 ` Jani Nikula
0 siblings, 0 replies; 23+ messages in thread
From: Jani Nikula @ 2021-08-31 8:10 UTC (permalink / raw)
To: Ville Syrjälä; +Cc: intel-gfx, dri-devel
On Mon, 30 Aug 2021, Ville Syrjälä <ville.syrjala@linux.intel.com> wrote:
> On Mon, Aug 30, 2021 at 01:29:01PM +0300, Jani Nikula wrote:
>> The VESA Organization Vendor-Specific Data Block, defined in VESA
>> DisplayID Standard v2.0, specifies the eDP Multi-SST Operation (MSO)
>> stream count and segment pixel overlap.
>>
>> DisplayID v1.3 has Appendix B: DisplayID as an EDID Extension,
>> describing how DisplayID sections may be embedded in EDID extension
>> blocks. DisplayID v2.0 does not have such a section, perhaps implying
>> that DisplayID v2.0 data should not be included in EDID extensions, but
>> rather in a "pure" DisplayID structure at its own DDC address pair
>> A4h/A5h, as described in VESA E-DDC Standard v1.3 chapter 3.
>>
>> However, in practice, displays out in the field have embedded DisplayID
>> v2.0 data blocks in EDID extensions, including, in particular, some eDP
>> MSO displays, where a pure DisplayID structure is not available at all.
>>
>> Parse the MSO data from the DisplayID data block. Do it as part of
>> drm_add_display_info(), extending it to parse also DisplayID data to
>> avoid requiring extra calls to update the information.
>>
>> Signed-off-by: Jani Nikula <jani.nikula@intel.com>
>> ---
>> drivers/gpu/drm/drm_edid.c | 63 +++++++++++++++++++++++++++++++++++++
>> include/drm/drm_connector.h | 12 +++++++
>> include/drm/drm_displayid.h | 11 +++++++
>> 3 files changed, 86 insertions(+)
>>
>> diff --git a/drivers/gpu/drm/drm_edid.c b/drivers/gpu/drm/drm_edid.c
>> index 6325877c5fd6..7e8083068f3f 100644
>> --- a/drivers/gpu/drm/drm_edid.c
>> +++ b/drivers/gpu/drm/drm_edid.c
>> @@ -28,6 +28,7 @@
>> * DEALINGS IN THE SOFTWARE.
>> */
>>
>> +#include <linux/bitfield.h>
>> #include <linux/hdmi.h>
>> #include <linux/i2c.h>
>> #include <linux/kernel.h>
>> @@ -5148,6 +5149,62 @@ void drm_get_monitor_range(struct drm_connector *connector,
>> info->monitor_range.max_vfreq);
>> }
>>
>> +static void drm_parse_vesa_mso_data(struct drm_connector *connector,
>> + const struct displayid_block *block)
>> +{
>> + struct displayid_vesa_vendor_specific_block *vesa =
>> + (struct displayid_vesa_vendor_specific_block *)block;
>> + struct drm_display_info *info = &connector->display_info;
>> +
>> + if (sizeof(*vesa) != sizeof(*block) + block->num_bytes) {
>> + drm_dbg_kms(connector->dev, "Unexpected VESA vendor block size\n");
>> + return;
>> + }
>> +
>> + switch (FIELD_GET(DISPLAYID_VESA_MSO_MODE, vesa->mso)) {
>> + default:
>> + drm_dbg_kms(connector->dev, "Reserved MSO mode value\n");
>> + fallthrough;
>> + case 0:
>> + info->mso_stream_count = 0;
>> + break;
>> + case 1:
>> + info->mso_stream_count = 2; /* 2 or 4 links */
>> + break;
>> + case 2:
>> + info->mso_stream_count = 4; /* 4 links */
>> + break;
>> + }
>> +
>> + if (!info->mso_stream_count) {
>> + info->mso_pixel_overlap = 0;
>> + return;
>> + }
>> +
>> + info->mso_pixel_overlap = FIELD_GET(DISPLAYID_VESA_MSO_OVERLAP, vesa->mso);
>> + if (info->mso_pixel_overlap > 8) {
>> + drm_dbg_kms(connector->dev, "Reserved MSO pixel overlap value %u\n",
>> + info->mso_pixel_overlap);
>> + info->mso_pixel_overlap = 8;
>> + }
>> +
>> + drm_dbg_kms(connector->dev, "MSO stream count %u, pixel overlap %u\n",
>> + info->mso_stream_count, info->mso_pixel_overlap);
>> +}
>> +
>> +static void drm_update_mso(struct drm_connector *connector, const struct edid *edid)
>> +{
>> + const struct displayid_block *block;
>> + struct displayid_iter iter;
>> +
>> + displayid_iter_edid_begin(edid, &iter);
>> + displayid_iter_for_each(block, &iter) {
>> + if (block->tag == DATA_BLOCK_2_VENDOR_SPECIFIC)
>
> Don't we need to check the OUI to make sure the block is the right
> type? I don't have the v2 spec at hand atm, but I presume a vendor
> specific block could contain all kinds of different things?
You're right.
BR,
Jani.
>
>> + drm_parse_vesa_mso_data(connector, block);
>> + }
>> + displayid_iter_end(&iter);
>> +}
>> +
>> /* A connector has no EDID information, so we've got no EDID to compute quirks from. Reset
>> * all of the values which would have been set from EDID
>> */
>> @@ -5171,6 +5228,9 @@ drm_reset_display_info(struct drm_connector *connector)
>>
>> info->non_desktop = 0;
>> memset(&info->monitor_range, 0, sizeof(info->monitor_range));
>> +
>> + info->mso_stream_count = 0;
>> + info->mso_pixel_overlap = 0;
>> }
>>
>> u32 drm_add_display_info(struct drm_connector *connector, const struct edid *edid)
>> @@ -5249,6 +5309,9 @@ u32 drm_add_display_info(struct drm_connector *connector, const struct edid *edi
>> info->color_formats |= DRM_COLOR_FORMAT_YCRCB444;
>> if (edid->features & DRM_EDID_FEATURE_RGB_YCRCB422)
>> info->color_formats |= DRM_COLOR_FORMAT_YCRCB422;
>> +
>> + drm_update_mso(connector, edid);
>> +
>> return quirks;
>> }
>>
>> diff --git a/include/drm/drm_connector.h b/include/drm/drm_connector.h
>> index 79fa34e5ccdb..379746d3266f 100644
>> --- a/include/drm/drm_connector.h
>> +++ b/include/drm/drm_connector.h
>> @@ -590,6 +590,18 @@ struct drm_display_info {
>> * @monitor_range: Frequency range supported by monitor range descriptor
>> */
>> struct drm_monitor_range_info monitor_range;
>> +
>> + /**
>> + * @mso_stream_count: eDP Multi-SST Operation (MSO) stream count from
>> + * the DisplayID VESA vendor block. 0 for conventional Single-Stream
>> + * Transport (SST), or 2 or 4 MSO streams.
>> + */
>> + u8 mso_stream_count;
>> +
>> + /**
>> + * @mso_pixel_overlap: eDP MSO segment pixel overlap, 0-8 pixels.
>> + */
>> + u8 mso_pixel_overlap;
>> };
>>
>> int drm_display_info_set_bus_formats(struct drm_display_info *info,
>> diff --git a/include/drm/drm_displayid.h b/include/drm/drm_displayid.h
>> index 79771091771a..b18611e016a2 100644
>> --- a/include/drm/drm_displayid.h
>> +++ b/include/drm/drm_displayid.h
>> @@ -23,6 +23,7 @@
>> #define DRM_DISPLAYID_H
>>
>> #include <linux/types.h>
>> +#include <linux/bits.h>
>>
>> struct edid;
>>
>> @@ -126,6 +127,16 @@ struct displayid_detailed_timing_block {
>> struct displayid_detailed_timings_1 timings[];
>> };
>>
>> +#define DISPLAYID_VESA_MSO_OVERLAP GENMASK(3, 0)
>> +#define DISPLAYID_VESA_MSO_MODE GENMASK(6, 5)
>> +
>> +struct displayid_vesa_vendor_specific_block {
>> + struct displayid_block base;
>> + u8 oui[3];
>> + u8 data_structure_type;
>> + u8 mso;
>> +} __packed;
>> +
>> /* DisplayID iteration */
>> struct displayid_iter {
>> const struct edid *edid;
>> --
>> 2.20.1
--
Jani Nikula, Intel Open Source Graphics Center
^ permalink raw reply [flat|nested] 23+ messages in thread
* Re: [PATCH 3/5] drm/edid: parse the DisplayID v2.0 VESA vendor block for MSO
2021-08-31 8:10 ` [Intel-gfx] " Jani Nikula
@ 2021-08-31 14:19 ` Jani Nikula
-1 siblings, 0 replies; 23+ messages in thread
From: Jani Nikula @ 2021-08-31 14:19 UTC (permalink / raw)
To: Ville Syrjälä; +Cc: intel-gfx, dri-devel
On Tue, 31 Aug 2021, Jani Nikula <jani.nikula@intel.com> wrote:
> On Mon, 30 Aug 2021, Ville Syrjälä <ville.syrjala@linux.intel.com> wrote:
>> Don't we need to check the OUI to make sure the block is the right
>> type? I don't have the v2 spec at hand atm, but I presume a vendor
>> specific block could contain all kinds of different things?
>
> You're right.
I resent the entire series because I added an OUI helper patch. I don't
think patchwork could handle that as an in-reply-to update.
https://patchwork.freedesktop.org/series/94161/
BR,
Jani.
--
Jani Nikula, Intel Open Source Graphics Center
^ permalink raw reply [flat|nested] 23+ messages in thread
* Re: [Intel-gfx] [PATCH 3/5] drm/edid: parse the DisplayID v2.0 VESA vendor block for MSO
@ 2021-08-31 14:19 ` Jani Nikula
0 siblings, 0 replies; 23+ messages in thread
From: Jani Nikula @ 2021-08-31 14:19 UTC (permalink / raw)
To: Ville Syrjälä; +Cc: intel-gfx, dri-devel
On Tue, 31 Aug 2021, Jani Nikula <jani.nikula@intel.com> wrote:
> On Mon, 30 Aug 2021, Ville Syrjälä <ville.syrjala@linux.intel.com> wrote:
>> Don't we need to check the OUI to make sure the block is the right
>> type? I don't have the v2 spec at hand atm, but I presume a vendor
>> specific block could contain all kinds of different things?
>
> You're right.
I resent the entire series because I added an OUI helper patch. I don't
think patchwork could handle that as an in-reply-to update.
https://patchwork.freedesktop.org/series/94161/
BR,
Jani.
--
Jani Nikula, Intel Open Source Graphics Center
^ permalink raw reply [flat|nested] 23+ messages in thread
end of thread, other threads:[~2021-08-31 14:20 UTC | newest]
Thread overview: 23+ messages (download: mbox.gz / follow: Atom feed)
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2021-08-30 10:28 [PATCH 0/5] drm/displayid: VESA vendor block and drm/i915 MSO use of it Jani Nikula
2021-08-30 10:28 ` [Intel-gfx] " Jani Nikula
2021-08-30 10:28 ` [PATCH 1/5] drm/displayid: re-align data block macros Jani Nikula
2021-08-30 10:28 ` [Intel-gfx] " Jani Nikula
2021-08-30 10:29 ` [PATCH 2/5] drm/displayid: add DisplayID v2.0 data blocks and primary use cases Jani Nikula
2021-08-30 10:29 ` [Intel-gfx] " Jani Nikula
2021-08-30 10:29 ` [PATCH 3/5] drm/edid: parse the DisplayID v2.0 VESA vendor block for MSO Jani Nikula
2021-08-30 10:29 ` [Intel-gfx] " Jani Nikula
2021-08-30 10:43 ` Jani Nikula
2021-08-30 10:43 ` [Intel-gfx] " Jani Nikula
2021-08-30 15:10 ` Ville Syrjälä
2021-08-30 15:10 ` [Intel-gfx] " Ville Syrjälä
2021-08-31 8:10 ` Jani Nikula
2021-08-31 8:10 ` [Intel-gfx] " Jani Nikula
2021-08-31 14:19 ` Jani Nikula
2021-08-31 14:19 ` [Intel-gfx] " Jani Nikula
2021-08-30 10:29 ` [PATCH 4/5] drm/i915/edp: postpone MSO init until after EDID read Jani Nikula
2021-08-30 10:29 ` [Intel-gfx] " Jani Nikula
2021-08-30 10:29 ` [PATCH 5/5] drm/i915/edp: use MSO pixel overlap from DisplayID data Jani Nikula
2021-08-30 10:29 ` [Intel-gfx] " Jani Nikula
2021-08-30 12:31 ` [Intel-gfx] ✗ Fi.CI.SPARSE: warning for drm/displayid: VESA vendor block and drm/i915 MSO use of it Patchwork
2021-08-30 12:59 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2021-08-30 15:26 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork
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