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Sure. > >> Cc: Don Hiatt >> Cc: Andi Shyti >> Signed-off-by: Don Hiatt >> Signed-off-by: Badal Nilawar >> --- >> drivers/gpu/drm/i915/gt/intel_gt_pm_debugfs.c | 2 +- >> drivers/gpu/drm/i915/gt/intel_gt_regs.h | 5 +++++ >> drivers/gpu/drm/i915/gt/intel_rps.c | 17 ++++++++++++++++- >> drivers/gpu/drm/i915/gt/intel_rps.h | 1 + >> drivers/gpu/drm/i915/i915_pmu.c | 3 +-- >> 5 files changed, 24 insertions(+), 4 deletions(-) >> >> diff --git a/drivers/gpu/drm/i915/gt/intel_gt_pm_debugfs.c b/drivers/gpu/drm/i915/gt/intel_gt_pm_debugfs.c >> index 108b9e76c32e..96c03a1258e1 100644 >> --- a/drivers/gpu/drm/i915/gt/intel_gt_pm_debugfs.c >> +++ b/drivers/gpu/drm/i915/gt/intel_gt_pm_debugfs.c >> @@ -380,7 +380,7 @@ void intel_gt_pm_frequency_dump(struct intel_gt *gt, struct drm_printer *p) >> rpinclimit = intel_uncore_read(uncore, GEN6_RP_UP_THRESHOLD); >> rpdeclimit = intel_uncore_read(uncore, GEN6_RP_DOWN_THRESHOLD); >> >> - rpstat = intel_uncore_read(uncore, GEN6_RPSTAT1); >> + rpstat = intel_rps_read_rpstat(rps); >> rpcurupei = intel_uncore_read(uncore, GEN6_RP_CUR_UP_EI) & GEN6_CURICONT_MASK; >> rpcurup = intel_uncore_read(uncore, GEN6_RP_CUR_UP) & GEN6_CURBSYTAVG_MASK; >> rpprevup = intel_uncore_read(uncore, GEN6_RP_PREV_UP) & GEN6_CURBSYTAVG_MASK; >> diff --git a/drivers/gpu/drm/i915/gt/intel_gt_regs.h b/drivers/gpu/drm/i915/gt/intel_gt_regs.h >> index fb2c56777480..dac59c3e68db 100644 >> --- a/drivers/gpu/drm/i915/gt/intel_gt_regs.h >> +++ b/drivers/gpu/drm/i915/gt/intel_gt_regs.h >> @@ -1510,6 +1510,11 @@ >> #define VLV_RENDER_C0_COUNT _MMIO(0x138118) >> #define VLV_MEDIA_C0_COUNT _MMIO(0x13811c) >> >> +#define GEN12_RPSTAT1 _MMIO(0x1381b4) >> +#define GEN12_CAGF_SHIFT 11 >> +#define GEN12_CAGF_MASK REG_GENMASK(19, 11) >> +#define GEN12_VOLTAGE_MASK REG_GENMASK(10, 0) > > Let's remove GEN12_VOLTAGE_MASK, looks like it's not being used. Yes, not used. I will remove this. > >> + >> #define GEN11_GT_INTR_DW(x) _MMIO(0x190018 + ((x) * 4)) >> #define GEN11_CSME (31) >> #define GEN11_GUNIT (28) >> diff --git a/drivers/gpu/drm/i915/gt/intel_rps.c b/drivers/gpu/drm/i915/gt/intel_rps.c >> index 6fadde4ee7bf..341f96f536e8 100644 >> --- a/drivers/gpu/drm/i915/gt/intel_rps.c >> +++ b/drivers/gpu/drm/i915/gt/intel_rps.c >> @@ -2040,6 +2040,19 @@ void intel_rps_sanitize(struct intel_rps *rps) >> rps_disable_interrupts(rps); >> } >> >> +u32 intel_rps_read_rpstat(struct intel_rps *rps) >> +{ >> + struct drm_i915_private *i915 = rps_to_i915(rps); >> + u32 rpstat; >> + >> + if (GRAPHICS_VER(i915) >= 12) >> + rpstat = intel_uncore_read(rps_to_gt(rps)->uncore, GEN12_RPSTAT1); >> + else >> + rpstat = intel_uncore_read(rps_to_gt(rps)->uncore, GEN6_RPSTAT1); > > Probably nit but how about something like this: > > i915_reg_t rpstat; > > if (GRAPHICS_VER(i915) >= 12) > rpstat = GEN12_RPSTAT1; > else > rpstat = GEN6_RPSTAT1; > > return intel_uncore_read(rps_to_gt(rps)->uncore, rpstat); Ok >> + >> + return rpstat; >> +} >> + >> u32 intel_rps_get_cagf(struct intel_rps *rps, u32 rpstat) >> { >> struct drm_i915_private *i915 = rps_to_i915(rps); >> @@ -2047,6 +2060,8 @@ u32 intel_rps_get_cagf(struct intel_rps *rps, u32 rpstat) >> >> if (IS_VALLEYVIEW(i915) || IS_CHERRYVIEW(i915)) >> cagf = (rpstat >> 8) & 0xff; >> + else if (GRAPHICS_VER(i915) >= 12) >> + cagf = (rpstat & GEN12_CAGF_MASK) >> GEN12_CAGF_SHIFT; >> else if (GRAPHICS_VER(i915) >= 9) >> cagf = (rpstat & GEN9_CAGF_MASK) >> GEN9_CAGF_SHIFT; >> else if (IS_HASWELL(i915) || IS_BROADWELL(i915)) >> @@ -2071,7 +2086,7 @@ static u32 read_cagf(struct intel_rps *rps) >> freq = vlv_punit_read(i915, PUNIT_REG_GPU_FREQ_STS); >> vlv_punit_put(i915); >> } else if (GRAPHICS_VER(i915) >= 6) { >> - freq = intel_uncore_read(uncore, GEN6_RPSTAT1); >> + freq = intel_rps_read_rpstat(rps); >> } else { >> freq = intel_uncore_read(uncore, MEMSTAT_ILK); >> } >> diff --git a/drivers/gpu/drm/i915/gt/intel_rps.h b/drivers/gpu/drm/i915/gt/intel_rps.h >> index 4509dfdc52e0..08bae6d97870 100644 >> --- a/drivers/gpu/drm/i915/gt/intel_rps.h >> +++ b/drivers/gpu/drm/i915/gt/intel_rps.h >> @@ -47,6 +47,7 @@ u32 intel_rps_get_rp1_frequency(struct intel_rps *rps); >> u32 intel_rps_get_rpn_frequency(struct intel_rps *rps); >> u32 intel_rps_read_punit_req(struct intel_rps *rps); >> u32 intel_rps_read_punit_req_frequency(struct intel_rps *rps); >> +u32 intel_rps_read_rpstat(struct intel_rps *rps); >> void gen6_rps_get_freq_caps(struct intel_rps *rps, struct intel_rps_freq_caps *caps); >> void intel_rps_raise_unslice(struct intel_rps *rps); >> void intel_rps_lower_unslice(struct intel_rps *rps); >> diff --git a/drivers/gpu/drm/i915/i915_pmu.c b/drivers/gpu/drm/i915/i915_pmu.c >> index 958b37123bf1..a24704ec2c18 100644 >> --- a/drivers/gpu/drm/i915/i915_pmu.c >> +++ b/drivers/gpu/drm/i915/i915_pmu.c >> @@ -371,7 +371,6 @@ static void >> frequency_sample(struct intel_gt *gt, unsigned int period_ns) >> { >> struct drm_i915_private *i915 = gt->i915; >> - struct intel_uncore *uncore = gt->uncore; >> struct i915_pmu *pmu = &i915->pmu; >> struct intel_rps *rps = >->rps; >> >> @@ -394,7 +393,7 @@ frequency_sample(struct intel_gt *gt, unsigned int period_ns) >> * case we assume the system is running at the intended >> * frequency. Fortunately, the read should rarely fail! >> */ >> - val = intel_uncore_read_fw(uncore, GEN6_RPSTAT1); >> + val = intel_rps_read_rpstat(rps); > > Hmm, we got rid of _fw which the comment above refers to. Maybe we need a > fw flag to intel_rps_read_rpstat? Above function before reading rpstat it checks if gt is awake. So when gt is awake shouldn't matter if we read GEN6_RPSTAT1 with forcewake.In that case we can remove above comment. Let me know your thoughts on this. Regards, Badal Nilawar > >> if (val) >> val = intel_rps_get_cagf(rps, val); >> else >> -- >> 2.25.1 >>