From mboxrd@z Thu Jan 1 00:00:00 1970 From: Jaehoon Chung Date: Tue, 26 Jan 2021 07:22:27 +0900 Subject: [PATCH v3 07/20] mmc: am654_sdhci: Add support for writing to clkbuf_sel In-Reply-To: <20210121124052.3454-8-a-govindraju@ti.com> References: <20210121124052.3454-1-a-govindraju@ti.com> <20210121124052.3454-8-a-govindraju@ti.com> Message-ID: <1d5b5e31-fe56-6d9b-d779-ab280e3e110c@samsung.com> List-Id: MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit To: u-boot@lists.denx.de On 1/21/21 9:40 PM, Aswath Govindraju wrote: > From: Faiz Abbas > > Add support for writing new clock buffer select property for both > the am654x and j721e 4 bit IPs > > Signed-off-by: Faiz Abbas > Signed-off-by: Aswath Govindraju Reviewed-by: Jaehoon Chung Best Regards, Jaehoon Chung > --- > drivers/mmc/am654_sdhci.c | 11 +++++++++++ > 1 file changed, 11 insertions(+) > > diff --git a/drivers/mmc/am654_sdhci.c b/drivers/mmc/am654_sdhci.c > index b82558254ebb..e86ef1a8b218 100644 > --- a/drivers/mmc/am654_sdhci.c > +++ b/drivers/mmc/am654_sdhci.c > @@ -48,6 +48,8 @@ > #define SEL100_MASK BIT(SEL100_SHIFT) > #define FREQSEL_SHIFT 8 > #define FREQSEL_MASK GENMASK(10, 8) > +#define CLKBUFSEL_SHIFT 0 > +#define CLKBUFSEL_MASK GENMASK(2, 0) > #define DLL_TRIM_ICP_SHIFT 4 > #define DLL_TRIM_ICP_MASK GENMASK(7, 4) > #define DR_TY_SHIFT 20 > @@ -92,6 +94,7 @@ struct am654_sdhci_plat { > u32 trm_icp; > u32 drv_strength; > u32 strb_sel; > + u32 clkbuf_sel; > u32 flags; > #define DLL_PRESENT BIT(0) > #define IOMUX_PRESENT BIT(1) > @@ -295,6 +298,9 @@ static int am654_sdhci_set_ios_post(struct sdhci_host *host) > am654_sdhci_setup_delay_chain(plat, mode); > } > > + regmap_update_bits(plat->base, PHY_CTRL5, CLKBUFSEL_MASK, > + plat->clkbuf_sel); > + > return 0; > } > > @@ -395,6 +401,9 @@ static int j721e_4bit_sdhci_set_ios_post(struct sdhci_host *host) > val = (1 << OTAPDLYENA_SHIFT) | (otap_del_sel << OTAPDLYSEL_SHIFT); > regmap_update_bits(plat->base, PHY_CTRL4, mask, val); > > + regmap_update_bits(plat->base, PHY_CTRL5, CLKBUFSEL_MASK, > + plat->clkbuf_sel); > + > return 0; > } > > @@ -548,6 +557,8 @@ static int am654_sdhci_of_to_plat(struct udevice *dev) > } > } > > + dev_read_u32(dev, "ti,clkbuf-sel", &plat->clkbuf_sel); > + > ret = mmc_of_parse(dev, cfg); > if (ret) > return ret; >