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From: Michael Davidsaver <mdavidsaver@gmail.com>
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Date: Sat, 18 Feb 2017 12:45:51 -0500
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Subject: Re: [Qemu-devel] [PATCH 3/9] armv7m: Rewrite NVIC to not use any
 GIC code
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To: Peter Maydell <peter.maydell@linaro.org>
Cc: =?UTF-8?Q?Alex_Benn=c3=a9e?= <alex.bennee@linaro.org>, qemu-arm <qemu-arm@nongnu.org>, QEMU Developers <qemu-devel@nongnu.org>, "patches@linaro.org" <patches@linaro.org>, Liviu Ionescu <ilg@livius.net>

On 02/16/2017 09:11 AM, Peter Maydell wrote:
> I haven't actually checked real hardware behaviour, but I think
> we can fairly safely implement this as not checking the IPSR
> exception field. (We might as well go with the "reads 1 in
> handler mode" choice of UNKNOWN that the M3 documents, though.)

For what it's worth, I dug up my TI TM4C1294 eval board and re-ran
test10.c [1] which is designed to probe this behavior by nesting
exceptions PendSV within SVC.  RETTOBASE is 0x800 in ICSR.

> 1..12
> # BASEPRI mask 000000e0
> # DEBUG prio 000000e0
> ok 1 - 00000000 == 00000000 ICSR
> ok 2 - 00000000 == 00000000 SHCSR
> # Call SVC
> # In SVC
> ok 3 - 0000080b == 0000080b ICSR
> ok 4 - 00000080 == 00000080 SHCSR
> # In PendSV
> ok 5 - 0000000e == 0000000e ICSR
> ok 6 - 00000480 == 00000480 SHCSR
> # Back in SVC
> ok 7 - 00000003 == 00000003 Back in SVC
> ok 8 - 0000080b == 0000080b ICSR
> ok 9 - 00000080 == 00000080 SHCSR
> # Back in main
> ok 10 - 00000004 == 00000004 Back in main
> ok 11 - 00000000 == 00000000 ICSR
> ok 12 - 00000000 == 00000000 SHCSR
> # Done

[1] https://github.com/mdavidsaver/baremetal/blob/qemutest/test10.c