From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:49027) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1c7Ptf-00068L-Sd for qemu-devel@nongnu.org; Thu, 17 Nov 2016 11:50:48 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1c7Ptb-0008Ro-0d for qemu-devel@nongnu.org; Thu, 17 Nov 2016 11:50:47 -0500 Received: from mail.uni-paderborn.de ([131.234.142.9]:42776) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1c7Pta-0008Rd-Jz for qemu-devel@nongnu.org; Thu, 17 Nov 2016 11:50:42 -0500 References: <1479324335-2074-1-git-send-email-rth@twiddle.net> <1479324335-2074-17-git-send-email-rth@twiddle.net> From: Bastian Koppelmann Message-ID: <1e2e6eab-921a-f30b-93d4-66bd62f68dd1@mail.uni-paderborn.de> Date: Thu, 17 Nov 2016 17:50:40 +0100 MIME-Version: 1.0 In-Reply-To: <1479324335-2074-17-git-send-email-rth@twiddle.net> Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: 8bit Subject: Re: [Qemu-devel] [PATCH 16/25] tcg/i386: Handle ctz and clz opcodes List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Richard Henderson , qemu-devel@nongnu.org On 11/16/2016 08:25 PM, Richard Henderson wrote: > + > + OP_32_64(clz): > + if (const_args[2]) { > + tcg_debug_assert(have_bmi1); > + tcg_debug_assert(args[2] == (rexw ? 64 : 32)); > + tcg_out_modrm(s, OPC_LZCNT + rexw, args[0], args[1]); > + } else { > + /* ??? See above. */ > + tcg_out_modrm(s, OPC_BSR + rexw, args[0], args[1]); The Intel ISA manual states that it find the bit index of the most significant bit, where the least significant bit is index 0. So for the input 0x2 this should return 1. However this is not the number of leading zeros. Cheers, Bastian