From: Leizhen (ThunderTown) <thunder.leizhen@huawei.com>
To: kbuild-all@lists.01.org
Subject: Re: [PATCH RFC 5/8] iommu/arm-smmu-v3: Add support for ECMDQ register mode
Date: Mon, 28 Jun 2021 09:43:45 +0800 [thread overview]
Message-ID: <1e49dbc4-8ef8-388e-db4a-186f2fde3351@huawei.com> (raw)
In-Reply-To: <202106262309.9LHyHely-lkp@intel.com>
[-- Attachment #1: Type: text/plain, Size: 5843 bytes --]
On 2021/6/26 23:49, kernel test robot wrote:
> Hi Zhen,
>
> [FYI, it's a private test report for your RFC patch.]
> [auto build test WARNING on iommu/next]
> [also build test WARNING on arm-perf/for-next/perf v5.13-rc7 next-20210625]
> [If your patch is applied to the wrong git tree, kindly drop us a note.
> And when submitting patch, we suggest to use '--base' as documented in
OK, these patches is based on the latest linux-next.
> https://git-scm.com/docs/git-format-patch]
>
> url: https://github.com/0day-ci/linux/commits/Zhen-Lei/iommu-arm-smmu-v3-add-support-for-ECMDQ-register-mode/20210626-190316
> base: https://git.kernel.org/pub/scm/linux/kernel/git/joro/iommu.git next
> config: arm64-randconfig-r032-20210622 (attached as .config)
> compiler: clang version 13.0.0 (https://github.com/llvm/llvm-project 557b101ce714e39438ba1d39c4c50b03e12fcb96)
> reproduce (this is a W=1 build):
> wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross
> chmod +x ~/bin/make.cross
> # install arm64 cross compiling tool for clang build
> # apt-get install binutils-aarch64-linux-gnu
> # https://github.com/0day-ci/linux/commit/fb36a6675f695ca24d94d461a7a6521e4d798226
> git remote add linux-review https://github.com/0day-ci/linux
> git fetch --no-tags linux-review Zhen-Lei/iommu-arm-smmu-v3-add-support-for-ECMDQ-register-mode/20210626-190316
> git checkout fb36a6675f695ca24d94d461a7a6521e4d798226
> # save the attached .config to linux build tree
> COMPILER_INSTALL_PATH=$HOME/0day COMPILER=clang make.cross ARCH=arm64
>
> If you fix the issue, kindly add following tag as appropriate
> Reported-by: kernel test robot <lkp@intel.com>
>
> All warnings (new ones prefixed by >>):
>
>>> drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c:3578:39: warning: variable 'pre_addr' is uninitialized when used here [-Wuninitialized]
> if (i && ((val & ECMDQ_CP_ADDR) != (pre_addr + ECMDQ_CP_RRESET_SIZE))) {
> ^~~~~~~~
> drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c:3569:20: note: initialize the variable 'pre_addr' to silence this warning
> u64 val, pre_addr;
> ^
> = 0
> 1 warning generated.
>
>
> vim +/pre_addr +3578 drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c
>
> 3547
> 3548 static int arm_smmu_ecmdq_probe(struct arm_smmu_device *smmu)
> 3549 {
> 3550 int ret, cpu;
> 3551 u32 i, nump, numq, gap;
> 3552 u32 reg, shift_increment;
> 3553 u64 addr, smmu_dma_base;
> 3554 void __iomem *cp_regs, *cp_base;
> 3555
> 3556 /* IDR6 */
> 3557 reg = readl_relaxed(smmu->base + ARM_SMMU_IDR6);
> 3558 nump = 1 << FIELD_GET(IDR6_LOG2NUMP, reg);
> 3559 numq = 1 << FIELD_GET(IDR6_LOG2NUMQ, reg);
> 3560 smmu->nr_ecmdq = nump * numq;
> 3561 gap = ECMDQ_CP_RRESET_SIZE >> FIELD_GET(IDR6_LOG2NUMQ, reg);
> 3562
> 3563 smmu_dma_base = (vmalloc_to_pfn(smmu->base) << PAGE_SHIFT);
> 3564 cp_regs = ioremap(smmu_dma_base + ARM_SMMU_ECMDQ_CP_BASE, PAGE_SIZE);
> 3565 if (!cp_regs)
> 3566 return -ENOMEM;
> 3567
> 3568 for (i = 0; i < nump; i++) {
> 3569 u64 val, pre_addr;
> 3570
> 3571 val = readq_relaxed(cp_regs + 32 * i);
> 3572 if (!(val & ECMDQ_CP_PRESET)) {
> 3573 iounmap(cp_regs);
> 3574 dev_err(smmu->dev, "ecmdq control page %u is memory mode\n", i);
> 3575 return -EFAULT;
> 3576 }
> 3577
>> 3578 if (i && ((val & ECMDQ_CP_ADDR) != (pre_addr + ECMDQ_CP_RRESET_SIZE))) {
The condition 'i' ensures that 'pre_addr' is not used in the first cycle(i==0).
It seems necessary to add "= 0" to initialize 'pre_addr' to eliminate this false positive.
> 3579 iounmap(cp_regs);
> 3580 dev_err(smmu->dev, "ecmdq_cp memory region is not contiguous\n");
> 3581 return -EFAULT;
> 3582 }
> 3583
> 3584 pre_addr = val & ECMDQ_CP_ADDR;
> 3585 }
> 3586
> 3587 addr = readl_relaxed(cp_regs) & ECMDQ_CP_ADDR;
> 3588 iounmap(cp_regs);
> 3589
> 3590 cp_base = devm_ioremap(smmu->dev, smmu_dma_base + addr, ECMDQ_CP_RRESET_SIZE * nump);
> 3591 if (!cp_base)
> 3592 return -ENOMEM;
> 3593
> 3594 smmu->ecmdq = devm_alloc_percpu(smmu->dev, struct arm_smmu_ecmdq *);
> 3595 if (!smmu->ecmdq)
> 3596 return -ENOMEM;
> 3597
> 3598 ret = arm_smmu_ecmdq_layout(smmu);
> 3599 if (ret)
> 3600 return ret;
> 3601
> 3602 shift_increment = order_base_2(num_possible_cpus() / smmu->nr_ecmdq);
> 3603
> 3604 addr = 0;
> 3605 for_each_possible_cpu(cpu) {
> 3606 struct arm_smmu_ecmdq *ecmdq;
> 3607 struct arm_smmu_queue *q;
> 3608
> 3609 ecmdq = *per_cpu_ptr(smmu->ecmdq, cpu);
> 3610 ecmdq->base = cp_base + addr;
> 3611
> 3612 q = &ecmdq->cmdq.q;
> 3613
> 3614 q->llq.max_n_shift = ECMDQ_MAX_SZ_SHIFT + shift_increment;
> 3615 ret = arm_smmu_init_one_queue(smmu, q, ecmdq->base, ARM_SMMU_ECMDQ_PROD,
> 3616 ARM_SMMU_ECMDQ_CONS, CMDQ_ENT_DWORDS, "ecmdq");
> 3617 if (ret)
> 3618 return ret;
> 3619
> 3620 q->ecmdq_prod = ECMDQ_PROD_EN;
> 3621 rwlock_init(&q->ecmdq_lock);
> 3622
> 3623 ret = arm_smmu_ecmdq_init(&ecmdq->cmdq);
> 3624 if (ret) {
> 3625 dev_err(smmu->dev, "ecmdq[%d] init failed\n", i);
> 3626 return ret;
> 3627 }
> 3628
> 3629 addr += gap;
> 3630 }
> 3631
> 3632 return 0;
> 3633 }
> 3634
>
> ---
> 0-DAY CI Kernel Test Service, Intel Corporation
> https://lists.01.org/hyperkitty/list/kbuild-all(a)lists.01.org
>
next prev parent reply other threads:[~2021-06-28 1:43 UTC|newest]
Thread overview: 53+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-06-26 11:01 [PATCH RFC 0/8] iommu/arm-smmu-v3: add support for ECMDQ register mode Zhen Lei
2021-06-26 11:01 ` Zhen Lei
2021-06-26 11:01 ` Zhen Lei
2021-06-26 11:01 ` [PATCH RFC 1/8] iommu/arm-smmu-v3: Use command queue batching helpers to improve performance Zhen Lei
2021-06-26 11:01 ` Zhen Lei
2021-06-26 11:01 ` Zhen Lei
2021-06-26 11:01 ` [PATCH RFC 2/8] iommu/arm-smmu-v3: Add and use static helper function arm_smmu_cmdq_issue_cmd_with_sync() Zhen Lei
2021-06-26 11:01 ` Zhen Lei
2021-06-26 11:01 ` Zhen Lei
2021-08-10 18:24 ` Will Deacon
2021-08-10 18:24 ` Will Deacon
2021-08-10 18:24 ` Will Deacon
2021-08-11 2:16 ` Leizhen (ThunderTown)
2021-08-11 2:16 ` Leizhen (ThunderTown)
2021-08-11 2:16 ` Leizhen (ThunderTown)
2021-08-11 10:09 ` Will Deacon
2021-08-11 10:09 ` Will Deacon
2021-08-11 10:09 ` Will Deacon
2021-08-11 10:31 ` John Garry
2021-08-11 10:31 ` John Garry
2021-08-11 10:31 ` John Garry
2021-08-11 10:33 ` Will Deacon
2021-08-11 10:33 ` Will Deacon
2021-08-11 10:33 ` Will Deacon
2021-08-11 11:15 ` John Garry
2021-08-11 11:15 ` John Garry
2021-08-11 11:15 ` John Garry
2021-06-26 11:01 ` [PATCH RFC 3/8] iommu/arm-smmu-v3: Add and use static helper function arm_smmu_get_cmdq() Zhen Lei
2021-06-26 11:01 ` Zhen Lei
2021-06-26 11:01 ` Zhen Lei
2021-06-26 11:01 ` [PATCH RFC 4/8] iommu/arm-smmu-v3: Extract reusable function __arm_smmu_cmdq_skip_err() Zhen Lei
2021-06-26 11:01 ` Zhen Lei
2021-06-26 11:01 ` Zhen Lei
2021-06-26 11:01 ` [PATCH RFC 5/8] iommu/arm-smmu-v3: Add support for ECMDQ register mode Zhen Lei
2021-06-26 11:01 ` Zhen Lei
2021-06-26 11:01 ` Zhen Lei
2021-06-26 15:49 ` kernel test robot
2021-06-28 1:43 ` Leizhen [this message]
2021-06-26 11:01 ` [PATCH RFC 6/8] iommu/arm-smmu-v3: Ensure that a set of associated commands are inserted in the same ECMDQ Zhen Lei
2021-06-26 11:01 ` Zhen Lei
2021-06-26 11:01 ` Zhen Lei
2021-06-26 11:01 ` [PATCH RFC 7/8] iommu/arm-smmu-v3: Add arm_smmu_ecmdq_issue_cmdlist() for non-shared ECMDQ Zhen Lei
2021-06-26 11:01 ` Zhen Lei
2021-06-26 11:01 ` Zhen Lei
2021-06-26 11:01 ` [PATCH RFC 8/8] iommu/arm-smmu-v3: Add support for less than one ECMDQ per core Zhen Lei
2021-06-26 11:01 ` Zhen Lei
2021-06-26 11:01 ` Zhen Lei
2021-08-10 18:35 ` [PATCH RFC 0/8] iommu/arm-smmu-v3: add support for ECMDQ register mode Will Deacon
2021-08-10 18:35 ` Will Deacon
2021-08-10 18:35 ` Will Deacon
2021-08-11 2:07 ` Leizhen (ThunderTown)
2021-08-11 2:07 ` Leizhen (ThunderTown)
2021-08-11 2:07 ` Leizhen (ThunderTown)
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