From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from phobos.denx.de (phobos.denx.de [85.214.62.61]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 1BC13C433FE for ; Thu, 17 Mar 2022 11:58:39 +0000 (UTC) Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) by phobos.denx.de (Postfix) with ESMTP id 7D17783A29; Thu, 17 Mar 2022 12:58:36 +0100 (CET) Authentication-Results: phobos.denx.de; dmarc=none (p=none dis=none) header.from=denx.de Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=denx.de; s=phobos-20191101; t=1647518317; bh=mvgqPi+h8otDm1ofI3sEH/etfFD+JfLONIxce5D3OpM=; h=Date:Subject:To:Cc:References:From:In-Reply-To:List-Id: List-Unsubscribe:List-Archive:List-Post:List-Help:List-Subscribe: From; b=MgaU/baXsThrYN4wxSwFQwFyieA3pW/b3RI1rBViTr/cZmpvBc0hu2p9pyoFWFj13 zgcE05dtaPxb1YyKhMjeKXLIJ9MKBpCYS7wliSb0iFnWFLHUnPNDmvWDCBpD2EB1/E A3q2tzWVdKjoELbXJgXiIuqRpU0jvnQNOKK51D3JCTXvvN4OUbwSTIYf+rLzygmxSd 6McQLEEFa60CGJVCMYb0bjTHhUqyWlJ4vQ0O6xjKfDIPd2dKWEU0lYgRkPkJ+V8blk Kw6tS2ra5aio0AJ6frZjgSOUVBIshsbn6hVw1Ifyf9Fqt9IldCSSGekwbO+cwT3ogB ekVcIeNHUh83w== Received: from [127.0.0.1] (p578adb1c.dip0.t-ipconnect.de [87.138.219.28]) (using TLSv1.3 with cipher TLS_AES_128_GCM_SHA256 (128/128 bits)) (No client certificate requested) (Authenticated sender: marex@denx.de) by phobos.denx.de (Postfix) with ESMTPSA id 4587983CF2; Thu, 17 Mar 2022 12:58:32 +0100 (CET) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=denx.de; s=phobos-20191101; t=1647518313; bh=mvgqPi+h8otDm1ofI3sEH/etfFD+JfLONIxce5D3OpM=; h=Date:Subject:To:Cc:References:From:In-Reply-To:From; b=MLRHZrklS967Y8fWrsx2p+5c1g0/4vzynYiU6fn6OV+aQuDEXaxKidsmEbrT4eF5P qhNzY1VX3nW77RRNdJ0Nt26Wxd9OAdg3xs57ST7aeC9r33vUk2ElA/CuvFF1Z82yOI FFwK79kRYQYDBsu1j6P0uoBKDAK5ELbAIMMwyyWD2KT03jKoHYn29nrYzqzMh6/NWm DqRylvLyfRGejPgLxSspkvGhQOGhV6AqqRv/vtpOSiwicllw73NFqsHNxdMm7GE6Gs r8B7eSoygWG7Gz12RyAss0KnD6TvIFQQnbHcLmyC0Omfzig/YOg5FTYB0cY035hsRq 2H8tAv8Bw5buQ== Message-ID: <1ed2f6d2-1bd7-4737-dcd5-10d7b6eb9542@denx.de> Date: Thu, 17 Mar 2022 12:58:31 +0100 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:91.0) Gecko/20100101 Thunderbird/91.6.2 Subject: Re: [PATCH v2 4/9] arm: imx: imx8mm: add enable_pwm_clk function Content-Language: en-US To: Tommaso Merciai Cc: Stefano Babic , Fabio Estevam , "NXP i.MX U-Boot Team" , Peng Fan , Ye Li , Alice Guo , Andrey Zhizhikin , =?UTF-8?Q?Marek_Beh=c3=ban?= , u-boot@lists.denx.de References: <20220316152746.47768-1-tommaso.merciai@amarulasolutions.com> <20220316152746.47768-5-tommaso.merciai@amarulasolutions.com> <1225773a-10e9-d90b-d1b1-0b749c96129d@denx.de> <20220317073927.GC29139@tom-ThinkPad-T14s-Gen-2i> From: Marek Vasut In-Reply-To: <20220317073927.GC29139@tom-ThinkPad-T14s-Gen-2i> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.5 at phobos.denx.de X-Virus-Status: Clean On 3/17/22 08:39, Tommaso Merciai wrote: > On Wed, Mar 16, 2022 at 09:54:34PM +0100, Marek Vasut wrote: >> On 3/16/22 16:27, Tommaso Merciai wrote: >>> Add function enable_pwm_clk into in clock_imx8mm.c. This >>> function first configure, then enable pwm clock from clock control >>> register. The following configuration is used: >>> >>> source(0) -> 24 MHz ref clock >>> div(0) -> no division for this clock >>> >>> References: >>> - iMX8MMRM.pdf p 303 >>> >>> Signed-off-by: Tommaso Merciai >>> --- >>> Changes since v1: >>> - Fix enable_pwm_clk function implementation. Now is generic for all pwm clks >>> >>> arch/arm/mach-imx/imx8m/clock_imx8mm.c | 53 ++++++++++++++++++++++++++ >>> 1 file changed, 53 insertions(+) >> >> Why is this not in drivers/clk/imx/ DM driver ? > > Hi Marek, > All function that enable/configure clk from CCGR are in arch/arm/mach-imx/imx8m/clock_imx8mm.c. These seems to be CCGR: $ grep -C 2 '0x4[0-9a-f]\{3\}' drivers/clk/imx/clk-imx8mm.c | sed "s@^.@@" clk_dm(IMX8MM_CLK_ECSPI1_ROOT, imx_clk_gate4("ecspi1_root_clk", "ecspi1", base + 0x4070, 0)); clk_dm(IMX8MM_CLK_ECSPI2_ROOT, imx_clk_gate4("ecspi2_root_clk", "ecspi2", base + 0x4080, 0)); clk_dm(IMX8MM_CLK_ECSPI3_ROOT, imx_clk_gate4("ecspi3_root_clk", "ecspi3", base + 0x4090, 0)); clk_dm(IMX8MM_CLK_I2C1_ROOT, imx_clk_gate4("i2c1_root_clk", "i2c1", base + 0x4170, 0)); clk_dm(IMX8MM_CLK_I2C2_ROOT, imx_clk_gate4("i2c2_root_clk", "i2c2", base + 0x4180, 0)); clk_dm(IMX8MM_CLK_I2C3_ROOT, imx_clk_gate4("i2c3_root_clk", "i2c3", base + 0x4190, 0)); clk_dm(IMX8MM_CLK_I2C4_ROOT, imx_clk_gate4("i2c4_root_clk", "i2c4", base + 0x41a0, 0)); clk_dm(IMX8MM_CLK_OCOTP_ROOT, imx_clk_gate4("ocotp_root_clk", "ipg_root", base + 0x4220, 0)); clk_dm(IMX8MM_CLK_USDHC1_ROOT, imx_clk_gate4("usdhc1_root_clk", "usdhc1", base + 0x4510, 0)); clk_dm(IMX8MM_CLK_USDHC2_ROOT, imx_clk_gate4("usdhc2_root_clk", "usdhc2", base + 0x4520, 0)); clk_dm(IMX8MM_CLK_WDOG1_ROOT, imx_clk_gate4("wdog1_root_clk", "wdog", base + 0x4530, 0)); clk_dm(IMX8MM_CLK_WDOG2_ROOT, imx_clk_gate4("wdog2_root_clk", "wdog", base + 0x4540, 0)); clk_dm(IMX8MM_CLK_WDOG3_ROOT, imx_clk_gate4("wdog3_root_clk", "wdog", base + 0x4550, 0)); clk_dm(IMX8MM_CLK_USDHC3_ROOT, imx_clk_gate4("usdhc3_root_clk", "usdhc3", base + 0x45e0, 0)); clk_dm(IMX8MM_CLK_QSPI_ROOT, imx_clk_gate4("qspi_root_clk", "qspi", base + 0x42f0, 0)); clk_dm(IMX8MM_CLK_USB1_CTRL_ROOT, imx_clk_gate4("usb1_ctrl_root_clk", "usb_bus", base + 0x44d0, 0)); /* clks not needed in SPL stage */ - clk_dm(IMX8MM_CLK_ENET1_ROOT, imx_clk_gate4("enet1_root_clk", "enet_axi", base + 0x40a0, 0)); endif > For that I continue to put here the implementation. After we can port > the clk dm part to manipulate clock in drivers/clk/imx/ DM driver. > What do you think about? Let me know. Seems like the clk_dm part is already in place and all you have to do is extend it.