* [PATCH 00/10] Aspeed: 6.2 queue
@ 2021-08-09 13:15 Cédric Le Goater
2021-08-09 13:15 ` [PATCH 01/10] hw: arm: aspeed: Enable eth0 interface for aspeed-ast2600-evb Cédric Le Goater
` (9 more replies)
0 siblings, 10 replies; 19+ messages in thread
From: Cédric Le Goater @ 2021-08-09 13:15 UTC (permalink / raw)
To: Peter Maydell
Cc: Andrew Jeffery, Cédric Le Goater, qemu-arm, Joel Stanley,
qemu-devel
Hi,
As usual, a couple of fixes and small extensions. There is also a
minimal DPS310 sensor model, which needs a little more review.
Thanks,
C.
Andrew Jeffery (3):
watchdog: aspeed: Sanitize control register values
watchdog: aspeed: Fix sequential control writes
misc/pca9552: Fix LED status register indexing in pca955x_get_led()
Guenter Roeck (1):
hw: arm: aspeed: Enable eth0 interface for aspeed-ast2600-evb
Joel Stanley (6):
hw: aspeed_gpio: Simplify 1.8V defines
hw: aspeed_gpio: Clarify GPIO controller name
arm/aspeed: rainier: Add i2c eeproms and muxes
aspeed: Emulate the AST2600A3
hw/misc: Add Infineon DPS310 sensor model
arm/aspeed: Add DPS310 to Witherspoon and Rainier
include/hw/misc/aspeed_scu.h | 2 +
include/hw/watchdog/wdt_aspeed.h | 1 +
hw/arm/aspeed.c | 57 +++++++-
hw/arm/aspeed_ast2600.c | 6 +-
hw/gpio/aspeed_gpio.c | 97 +++++++------
hw/misc/aspeed_scu.c | 36 ++++-
hw/misc/dps310.c | 227 +++++++++++++++++++++++++++++++
hw/misc/pca9552.c | 2 +-
hw/watchdog/wdt_aspeed.c | 26 +++-
hw/arm/Kconfig | 1 +
hw/misc/Kconfig | 4 +
hw/misc/meson.build | 1 +
12 files changed, 392 insertions(+), 68 deletions(-)
create mode 100644 hw/misc/dps310.c
--
2.31.1
^ permalink raw reply [flat|nested] 19+ messages in thread
* [PATCH 01/10] hw: arm: aspeed: Enable eth0 interface for aspeed-ast2600-evb
2021-08-09 13:15 [PATCH 00/10] Aspeed: 6.2 queue Cédric Le Goater
@ 2021-08-09 13:15 ` Cédric Le Goater
2021-08-09 13:15 ` [PATCH 02/10] watchdog: aspeed: Sanitize control register values Cédric Le Goater
` (8 subsequent siblings)
9 siblings, 0 replies; 19+ messages in thread
From: Cédric Le Goater @ 2021-08-09 13:15 UTC (permalink / raw)
To: Peter Maydell
Cc: Andrew Jeffery, qemu-devel, qemu-arm, Cédric Le Goater,
Guenter Roeck, Joel Stanley
From: Guenter Roeck <linux@roeck-us.net>
Commit 7582591ae7 ("aspeed: Support AST2600A1 silicon revision") switched
the silicon revision for AST2600 to revision A1. On revision A1, the first
Ethernet interface is operational. Enable it.
Signed-off-by: Guenter Roeck <linux@roeck-us.net>
Reviewed-by: Joel Stanley <joel@jms.id.au>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Message-Id: <20210808200457.889955-1-linux@roeck-us.net>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
---
hw/arm/aspeed.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/hw/arm/aspeed.c b/hw/arm/aspeed.c
index 9d43e26c51bb..ecf0c9cfacb8 100644
--- a/hw/arm/aspeed.c
+++ b/hw/arm/aspeed.c
@@ -959,7 +959,8 @@ static void aspeed_machine_ast2600_evb_class_init(ObjectClass *oc, void *data)
amc->fmc_model = "w25q512jv";
amc->spi_model = "mx66u51235f";
amc->num_cs = 1;
- amc->macs_mask = ASPEED_MAC1_ON | ASPEED_MAC2_ON | ASPEED_MAC3_ON;
+ amc->macs_mask = ASPEED_MAC0_ON | ASPEED_MAC1_ON | ASPEED_MAC2_ON |
+ ASPEED_MAC3_ON;
amc->i2c_init = ast2600_evb_i2c_init;
mc->default_ram_size = 1 * GiB;
mc->default_cpus = mc->min_cpus = mc->max_cpus =
--
2.31.1
^ permalink raw reply related [flat|nested] 19+ messages in thread
* [PATCH 02/10] watchdog: aspeed: Sanitize control register values
2021-08-09 13:15 [PATCH 00/10] Aspeed: 6.2 queue Cédric Le Goater
2021-08-09 13:15 ` [PATCH 01/10] hw: arm: aspeed: Enable eth0 interface for aspeed-ast2600-evb Cédric Le Goater
@ 2021-08-09 13:15 ` Cédric Le Goater
2021-08-09 13:15 ` [PATCH 03/10] watchdog: aspeed: Fix sequential control writes Cédric Le Goater
` (7 subsequent siblings)
9 siblings, 0 replies; 19+ messages in thread
From: Cédric Le Goater @ 2021-08-09 13:15 UTC (permalink / raw)
To: Peter Maydell
Cc: Andrew Jeffery, Cédric Le Goater, qemu-arm, Joel Stanley,
qemu-devel
From: Andrew Jeffery <andrew@aj.id.au>
While some of the critical fields remain the same, there is variation in
the definition of the control register across the SoC generations.
Reserved regions are adjusted, while in other cases the mutability or
behaviour of fields change.
Introduce a callback to sanitize the value on writes to ensure model
behaviour reflects the hardware.
Fixes: 854123bf8d4b ("wdt: Add Aspeed watchdog device model")
Signed-off-by: Andrew Jeffery <andrew@aj.id.au>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Message-Id: <20210709053107.1829304-2-andrew@aj.id.au>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
---
include/hw/watchdog/wdt_aspeed.h | 1 +
hw/watchdog/wdt_aspeed.c | 24 ++++++++++++++++++++++--
2 files changed, 23 insertions(+), 2 deletions(-)
diff --git a/include/hw/watchdog/wdt_aspeed.h b/include/hw/watchdog/wdt_aspeed.h
index 80b03661e303..f945cd6c5833 100644
--- a/include/hw/watchdog/wdt_aspeed.h
+++ b/include/hw/watchdog/wdt_aspeed.h
@@ -44,6 +44,7 @@ struct AspeedWDTClass {
uint32_t reset_ctrl_reg;
void (*reset_pulse)(AspeedWDTState *s, uint32_t property);
void (*wdt_reload)(AspeedWDTState *s);
+ uint64_t (*sanitize_ctrl)(uint64_t data);
};
#endif /* WDT_ASPEED_H */
diff --git a/hw/watchdog/wdt_aspeed.c b/hw/watchdog/wdt_aspeed.c
index 6352ba1b0e5b..faa3d35fdf21 100644
--- a/hw/watchdog/wdt_aspeed.c
+++ b/hw/watchdog/wdt_aspeed.c
@@ -118,13 +118,27 @@ static void aspeed_wdt_reload_1mhz(AspeedWDTState *s)
}
}
+static uint64_t aspeed_2400_sanitize_ctrl(uint64_t data)
+{
+ return data & 0xffff;
+}
+
+static uint64_t aspeed_2500_sanitize_ctrl(uint64_t data)
+{
+ return (data & ~(0xfUL << 8)) | WDT_CTRL_1MHZ_CLK;
+}
+
+static uint64_t aspeed_2600_sanitize_ctrl(uint64_t data)
+{
+ return data & ~(0x7UL << 7);
+}
static void aspeed_wdt_write(void *opaque, hwaddr offset, uint64_t data,
unsigned size)
{
AspeedWDTState *s = ASPEED_WDT(opaque);
AspeedWDTClass *awc = ASPEED_WDT_GET_CLASS(s);
- bool enable = data & WDT_CTRL_ENABLE;
+ bool enable;
offset >>= 2;
@@ -144,6 +158,8 @@ static void aspeed_wdt_write(void *opaque, hwaddr offset, uint64_t data,
}
break;
case WDT_CTRL:
+ data = awc->sanitize_ctrl(data);
+ enable = data & WDT_CTRL_ENABLE;
if (enable && !aspeed_wdt_is_enabled(s)) {
s->regs[WDT_CTRL] = data;
awc->wdt_reload(s);
@@ -207,11 +223,12 @@ static const MemoryRegionOps aspeed_wdt_ops = {
static void aspeed_wdt_reset(DeviceState *dev)
{
AspeedWDTState *s = ASPEED_WDT(dev);
+ AspeedWDTClass *awc = ASPEED_WDT_GET_CLASS(s);
s->regs[WDT_STATUS] = 0x3EF1480;
s->regs[WDT_RELOAD_VALUE] = 0x03EF1480;
s->regs[WDT_RESTART] = 0;
- s->regs[WDT_CTRL] = 0;
+ s->regs[WDT_CTRL] = awc->sanitize_ctrl(0);
s->regs[WDT_RESET_WIDTH] = 0xFF;
timer_del(s->timer);
@@ -293,6 +310,7 @@ static void aspeed_2400_wdt_class_init(ObjectClass *klass, void *data)
awc->ext_pulse_width_mask = 0xff;
awc->reset_ctrl_reg = SCU_RESET_CONTROL1;
awc->wdt_reload = aspeed_wdt_reload;
+ awc->sanitize_ctrl = aspeed_2400_sanitize_ctrl;
}
static const TypeInfo aspeed_2400_wdt_info = {
@@ -328,6 +346,7 @@ static void aspeed_2500_wdt_class_init(ObjectClass *klass, void *data)
awc->reset_ctrl_reg = SCU_RESET_CONTROL1;
awc->reset_pulse = aspeed_2500_wdt_reset_pulse;
awc->wdt_reload = aspeed_wdt_reload_1mhz;
+ awc->sanitize_ctrl = aspeed_2500_sanitize_ctrl;
}
static const TypeInfo aspeed_2500_wdt_info = {
@@ -348,6 +367,7 @@ static void aspeed_2600_wdt_class_init(ObjectClass *klass, void *data)
awc->reset_ctrl_reg = AST2600_SCU_RESET_CONTROL1;
awc->reset_pulse = aspeed_2500_wdt_reset_pulse;
awc->wdt_reload = aspeed_wdt_reload_1mhz;
+ awc->sanitize_ctrl = aspeed_2600_sanitize_ctrl;
}
static const TypeInfo aspeed_2600_wdt_info = {
--
2.31.1
^ permalink raw reply related [flat|nested] 19+ messages in thread
* [PATCH 03/10] watchdog: aspeed: Fix sequential control writes
2021-08-09 13:15 [PATCH 00/10] Aspeed: 6.2 queue Cédric Le Goater
2021-08-09 13:15 ` [PATCH 01/10] hw: arm: aspeed: Enable eth0 interface for aspeed-ast2600-evb Cédric Le Goater
2021-08-09 13:15 ` [PATCH 02/10] watchdog: aspeed: Sanitize control register values Cédric Le Goater
@ 2021-08-09 13:15 ` Cédric Le Goater
2021-08-09 15:48 ` Philippe Mathieu-Daudé
2021-08-09 13:15 ` [PATCH 04/10] hw: aspeed_gpio: Simplify 1.8V defines Cédric Le Goater
` (6 subsequent siblings)
9 siblings, 1 reply; 19+ messages in thread
From: Cédric Le Goater @ 2021-08-09 13:15 UTC (permalink / raw)
To: Peter Maydell
Cc: Andrew Jeffery, Cédric Le Goater, qemu-arm, Joel Stanley,
qemu-devel
From: Andrew Jeffery <andrew@aj.id.au>
The logic in the handling for the control register required toggling the
enable state for writes to stick. Rework the condition chain to allow
sequential writes that do not update the enable state.
Fixes: 854123bf8d4b ("wdt: Add Aspeed watchdog device model")
Signed-off-by: Andrew Jeffery <andrew@aj.id.au>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Message-Id: <20210709053107.1829304-3-andrew@aj.id.au>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
---
hw/watchdog/wdt_aspeed.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/hw/watchdog/wdt_aspeed.c b/hw/watchdog/wdt_aspeed.c
index faa3d35fdf21..69c37af9a6e9 100644
--- a/hw/watchdog/wdt_aspeed.c
+++ b/hw/watchdog/wdt_aspeed.c
@@ -166,6 +166,8 @@ static void aspeed_wdt_write(void *opaque, hwaddr offset, uint64_t data,
} else if (!enable && aspeed_wdt_is_enabled(s)) {
s->regs[WDT_CTRL] = data;
timer_del(s->timer);
+ } else {
+ s->regs[WDT_CTRL] = data;
}
break;
case WDT_RESET_WIDTH:
--
2.31.1
^ permalink raw reply related [flat|nested] 19+ messages in thread
* [PATCH 04/10] hw: aspeed_gpio: Simplify 1.8V defines
2021-08-09 13:15 [PATCH 00/10] Aspeed: 6.2 queue Cédric Le Goater
` (2 preceding siblings ...)
2021-08-09 13:15 ` [PATCH 03/10] watchdog: aspeed: Fix sequential control writes Cédric Le Goater
@ 2021-08-09 13:15 ` Cédric Le Goater
2021-08-09 13:15 ` [PATCH 05/10] hw: aspeed_gpio: Clarify GPIO controller name Cédric Le Goater
` (5 subsequent siblings)
9 siblings, 0 replies; 19+ messages in thread
From: Cédric Le Goater @ 2021-08-09 13:15 UTC (permalink / raw)
To: Peter Maydell
Cc: Andrew Jeffery, qemu-devel, Philippe Mathieu-Daudé,
qemu-arm, Joel Stanley, Rashmica Gupta, Cédric Le Goater
From: Joel Stanley <joel@jms.id.au>
There's no need to define the registers relative to the 0x800 offset
where the controller is mapped, as the device is instantiated as it's
own model at the correct memory address.
Simplify the defines and remove the offset to save future confusion.
Signed-off-by: Joel Stanley <joel@jms.id.au>
Reviewed-by: Rashmica Gupta <rashmica.g@gmail.com>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-Id: <20210713065854.134634-3-joel@jms.id.au>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
---
hw/gpio/aspeed_gpio.c | 73 +++++++++++++++++++++----------------------
1 file changed, 36 insertions(+), 37 deletions(-)
diff --git a/hw/gpio/aspeed_gpio.c b/hw/gpio/aspeed_gpio.c
index b3dec4448009..dc721aec5da7 100644
--- a/hw/gpio/aspeed_gpio.c
+++ b/hw/gpio/aspeed_gpio.c
@@ -169,44 +169,43 @@
/* AST2600 only - 1.8V gpios */
/*
- * The AST2600 has same 3.6V gpios as the AST2400 (memory offsets 0x0-0x198)
- * and additional 1.8V gpios (memory offsets 0x800-0x9D4).
+ * The AST2600 two copies of the GPIO controller: the same 3.6V gpios as the
+ * AST2400 (memory offsets 0x0-0x198) and a second controller with 1.8V gpios
+ * (memory offsets 0x800-0x9D4).
*/
-#define GPIO_1_8V_REG_OFFSET 0x800
-#define GPIO_1_8V_ABCD_DATA_VALUE ((0x800 - GPIO_1_8V_REG_OFFSET) >> 2)
-#define GPIO_1_8V_ABCD_DIRECTION ((0x804 - GPIO_1_8V_REG_OFFSET) >> 2)
-#define GPIO_1_8V_ABCD_INT_ENABLE ((0x808 - GPIO_1_8V_REG_OFFSET) >> 2)
-#define GPIO_1_8V_ABCD_INT_SENS_0 ((0x80C - GPIO_1_8V_REG_OFFSET) >> 2)
-#define GPIO_1_8V_ABCD_INT_SENS_1 ((0x810 - GPIO_1_8V_REG_OFFSET) >> 2)
-#define GPIO_1_8V_ABCD_INT_SENS_2 ((0x814 - GPIO_1_8V_REG_OFFSET) >> 2)
-#define GPIO_1_8V_ABCD_INT_STATUS ((0x818 - GPIO_1_8V_REG_OFFSET) >> 2)
-#define GPIO_1_8V_ABCD_RESET_TOLERANT ((0x81C - GPIO_1_8V_REG_OFFSET) >> 2)
-#define GPIO_1_8V_E_DATA_VALUE ((0x820 - GPIO_1_8V_REG_OFFSET) >> 2)
-#define GPIO_1_8V_E_DIRECTION ((0x824 - GPIO_1_8V_REG_OFFSET) >> 2)
-#define GPIO_1_8V_E_INT_ENABLE ((0x828 - GPIO_1_8V_REG_OFFSET) >> 2)
-#define GPIO_1_8V_E_INT_SENS_0 ((0x82C - GPIO_1_8V_REG_OFFSET) >> 2)
-#define GPIO_1_8V_E_INT_SENS_1 ((0x830 - GPIO_1_8V_REG_OFFSET) >> 2)
-#define GPIO_1_8V_E_INT_SENS_2 ((0x834 - GPIO_1_8V_REG_OFFSET) >> 2)
-#define GPIO_1_8V_E_INT_STATUS ((0x838 - GPIO_1_8V_REG_OFFSET) >> 2)
-#define GPIO_1_8V_E_RESET_TOLERANT ((0x83C - GPIO_1_8V_REG_OFFSET) >> 2)
-#define GPIO_1_8V_ABCD_DEBOUNCE_1 ((0x840 - GPIO_1_8V_REG_OFFSET) >> 2)
-#define GPIO_1_8V_ABCD_DEBOUNCE_2 ((0x844 - GPIO_1_8V_REG_OFFSET) >> 2)
-#define GPIO_1_8V_E_DEBOUNCE_1 ((0x848 - GPIO_1_8V_REG_OFFSET) >> 2)
-#define GPIO_1_8V_E_DEBOUNCE_2 ((0x84C - GPIO_1_8V_REG_OFFSET) >> 2)
-#define GPIO_1_8V_DEBOUNCE_TIME_1 ((0x850 - GPIO_1_8V_REG_OFFSET) >> 2)
-#define GPIO_1_8V_DEBOUNCE_TIME_2 ((0x854 - GPIO_1_8V_REG_OFFSET) >> 2)
-#define GPIO_1_8V_DEBOUNCE_TIME_3 ((0x858 - GPIO_1_8V_REG_OFFSET) >> 2)
-#define GPIO_1_8V_ABCD_COMMAND_SRC_0 ((0x860 - GPIO_1_8V_REG_OFFSET) >> 2)
-#define GPIO_1_8V_ABCD_COMMAND_SRC_1 ((0x864 - GPIO_1_8V_REG_OFFSET) >> 2)
-#define GPIO_1_8V_E_COMMAND_SRC_0 ((0x868 - GPIO_1_8V_REG_OFFSET) >> 2)
-#define GPIO_1_8V_E_COMMAND_SRC_1 ((0x86C - GPIO_1_8V_REG_OFFSET) >> 2)
-#define GPIO_1_8V_ABCD_DATA_READ ((0x8C0 - GPIO_1_8V_REG_OFFSET) >> 2)
-#define GPIO_1_8V_E_DATA_READ ((0x8C4 - GPIO_1_8V_REG_OFFSET) >> 2)
-#define GPIO_1_8V_ABCD_INPUT_MASK ((0x9D0 - GPIO_1_8V_REG_OFFSET) >> 2)
-#define GPIO_1_8V_E_INPUT_MASK ((0x9D4 - GPIO_1_8V_REG_OFFSET) >> 2)
-#define GPIO_1_8V_MEM_SIZE 0x9D8
-#define GPIO_1_8V_REG_ARRAY_SIZE ((GPIO_1_8V_MEM_SIZE - \
- GPIO_1_8V_REG_OFFSET) >> 2)
+#define GPIO_1_8V_ABCD_DATA_VALUE (0x000 >> 2)
+#define GPIO_1_8V_ABCD_DIRECTION (0x004 >> 2)
+#define GPIO_1_8V_ABCD_INT_ENABLE (0x008 >> 2)
+#define GPIO_1_8V_ABCD_INT_SENS_0 (0x00C >> 2)
+#define GPIO_1_8V_ABCD_INT_SENS_1 (0x010 >> 2)
+#define GPIO_1_8V_ABCD_INT_SENS_2 (0x014 >> 2)
+#define GPIO_1_8V_ABCD_INT_STATUS (0x018 >> 2)
+#define GPIO_1_8V_ABCD_RESET_TOLERANT (0x01C >> 2)
+#define GPIO_1_8V_E_DATA_VALUE (0x020 >> 2)
+#define GPIO_1_8V_E_DIRECTION (0x024 >> 2)
+#define GPIO_1_8V_E_INT_ENABLE (0x028 >> 2)
+#define GPIO_1_8V_E_INT_SENS_0 (0x02C >> 2)
+#define GPIO_1_8V_E_INT_SENS_1 (0x030 >> 2)
+#define GPIO_1_8V_E_INT_SENS_2 (0x034 >> 2)
+#define GPIO_1_8V_E_INT_STATUS (0x038 >> 2)
+#define GPIO_1_8V_E_RESET_TOLERANT (0x03C >> 2)
+#define GPIO_1_8V_ABCD_DEBOUNCE_1 (0x040 >> 2)
+#define GPIO_1_8V_ABCD_DEBOUNCE_2 (0x044 >> 2)
+#define GPIO_1_8V_E_DEBOUNCE_1 (0x048 >> 2)
+#define GPIO_1_8V_E_DEBOUNCE_2 (0x04C >> 2)
+#define GPIO_1_8V_DEBOUNCE_TIME_1 (0x050 >> 2)
+#define GPIO_1_8V_DEBOUNCE_TIME_2 (0x054 >> 2)
+#define GPIO_1_8V_DEBOUNCE_TIME_3 (0x058 >> 2)
+#define GPIO_1_8V_ABCD_COMMAND_SRC_0 (0x060 >> 2)
+#define GPIO_1_8V_ABCD_COMMAND_SRC_1 (0x064 >> 2)
+#define GPIO_1_8V_E_COMMAND_SRC_0 (0x068 >> 2)
+#define GPIO_1_8V_E_COMMAND_SRC_1 (0x06C >> 2)
+#define GPIO_1_8V_ABCD_DATA_READ (0x0C0 >> 2)
+#define GPIO_1_8V_E_DATA_READ (0x0C4 >> 2)
+#define GPIO_1_8V_ABCD_INPUT_MASK (0x1D0 >> 2)
+#define GPIO_1_8V_E_INPUT_MASK (0x1D4 >> 2)
+#define GPIO_1_8V_MEM_SIZE 0x1D8
+#define GPIO_1_8V_REG_ARRAY_SIZE (GPIO_1_8V_MEM_SIZE >> 2)
static int aspeed_evaluate_irq(GPIOSets *regs, int gpio_prev_high, int gpio)
{
--
2.31.1
^ permalink raw reply related [flat|nested] 19+ messages in thread
* [PATCH 05/10] hw: aspeed_gpio: Clarify GPIO controller name
2021-08-09 13:15 [PATCH 00/10] Aspeed: 6.2 queue Cédric Le Goater
` (3 preceding siblings ...)
2021-08-09 13:15 ` [PATCH 04/10] hw: aspeed_gpio: Simplify 1.8V defines Cédric Le Goater
@ 2021-08-09 13:15 ` Cédric Le Goater
2021-08-09 13:15 ` [PATCH 06/10] misc/pca9552: Fix LED status register indexing in pca955x_get_led() Cédric Le Goater
` (4 subsequent siblings)
9 siblings, 0 replies; 19+ messages in thread
From: Cédric Le Goater @ 2021-08-09 13:15 UTC (permalink / raw)
To: Peter Maydell
Cc: Andrew Jeffery, qemu-devel, qemu-arm, Joel Stanley,
Rashmica Gupta, Cédric Le Goater
From: Joel Stanley <joel@jms.id.au>
There are two GPIO controllers in the ast2600; one is 3.3V and the other
is 1.8V.
Signed-off-by: Joel Stanley <joel@jms.id.au>
Reviewed-by: Rashmica Gupta <rashmica.g@gmail.com>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Message-Id: <20210713065854.134634-4-joel@jms.id.au>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
---
hw/gpio/aspeed_gpio.c | 26 +++++++++++++-------------
1 file changed, 13 insertions(+), 13 deletions(-)
diff --git a/hw/gpio/aspeed_gpio.c b/hw/gpio/aspeed_gpio.c
index dc721aec5da7..dfa6d6cb40a9 100644
--- a/hw/gpio/aspeed_gpio.c
+++ b/hw/gpio/aspeed_gpio.c
@@ -164,12 +164,12 @@
#define GPIO_YZAAAB_DIRECTION (0x1E4 >> 2)
#define GPIO_AC_DATA_VALUE (0x1E8 >> 2)
#define GPIO_AC_DIRECTION (0x1EC >> 2)
-#define GPIO_3_6V_MEM_SIZE 0x1F0
-#define GPIO_3_6V_REG_ARRAY_SIZE (GPIO_3_6V_MEM_SIZE >> 2)
+#define GPIO_3_3V_MEM_SIZE 0x1F0
+#define GPIO_3_3V_REG_ARRAY_SIZE (GPIO_3_3V_MEM_SIZE >> 2)
/* AST2600 only - 1.8V gpios */
/*
- * The AST2600 two copies of the GPIO controller: the same 3.6V gpios as the
+ * The AST2600 two copies of the GPIO controller: the same 3.3V gpios as the
* AST2400 (memory offsets 0x0-0x198) and a second controller with 1.8V gpios
* (memory offsets 0x800-0x9D4).
*/
@@ -380,7 +380,7 @@ static uint32_t update_value_control_source(GPIOSets *regs, uint32_t old_value,
return new_value;
}
-static const AspeedGPIOReg aspeed_3_6v_gpios[GPIO_3_6V_REG_ARRAY_SIZE] = {
+static const AspeedGPIOReg aspeed_3_3v_gpios[GPIO_3_3V_REG_ARRAY_SIZE] = {
/* Set ABCD */
[GPIO_ABCD_DATA_VALUE] = { 0, gpio_reg_data_value },
[GPIO_ABCD_DIRECTION] = { 0, gpio_reg_direction },
@@ -800,7 +800,7 @@ static const GPIOSetProperties ast2500_set_props[] = {
[7] = {0x000000ff, 0x000000ff, {"AC"} },
};
-static GPIOSetProperties ast2600_3_6v_set_props[] = {
+static GPIOSetProperties ast2600_3_3v_set_props[] = {
[0] = {0xffffffff, 0xffffffff, {"A", "B", "C", "D"} },
[1] = {0xffffffff, 0xffffffff, {"E", "F", "G", "H"} },
[2] = {0xffffffff, 0xffffffff, {"I", "J", "K", "L"} },
@@ -927,7 +927,7 @@ static void aspeed_gpio_ast2400_class_init(ObjectClass *klass, void *data)
agc->nr_gpio_pins = 216;
agc->nr_gpio_sets = 7;
agc->gap = 196;
- agc->reg_table = aspeed_3_6v_gpios;
+ agc->reg_table = aspeed_3_3v_gpios;
}
static void aspeed_gpio_2500_class_init(ObjectClass *klass, void *data)
@@ -938,17 +938,17 @@ static void aspeed_gpio_2500_class_init(ObjectClass *klass, void *data)
agc->nr_gpio_pins = 228;
agc->nr_gpio_sets = 8;
agc->gap = 220;
- agc->reg_table = aspeed_3_6v_gpios;
+ agc->reg_table = aspeed_3_3v_gpios;
}
-static void aspeed_gpio_ast2600_3_6v_class_init(ObjectClass *klass, void *data)
+static void aspeed_gpio_ast2600_3_3v_class_init(ObjectClass *klass, void *data)
{
AspeedGPIOClass *agc = ASPEED_GPIO_CLASS(klass);
- agc->props = ast2600_3_6v_set_props;
+ agc->props = ast2600_3_3v_set_props;
agc->nr_gpio_pins = 208;
agc->nr_gpio_sets = 7;
- agc->reg_table = aspeed_3_6v_gpios;
+ agc->reg_table = aspeed_3_3v_gpios;
}
static void aspeed_gpio_ast2600_1_8v_class_init(ObjectClass *klass, void *data)
@@ -984,10 +984,10 @@ static const TypeInfo aspeed_gpio_ast2500_info = {
.instance_init = aspeed_gpio_init,
};
-static const TypeInfo aspeed_gpio_ast2600_3_6v_info = {
+static const TypeInfo aspeed_gpio_ast2600_3_3v_info = {
.name = TYPE_ASPEED_GPIO "-ast2600",
.parent = TYPE_ASPEED_GPIO,
- .class_init = aspeed_gpio_ast2600_3_6v_class_init,
+ .class_init = aspeed_gpio_ast2600_3_3v_class_init,
.instance_init = aspeed_gpio_init,
};
@@ -1003,7 +1003,7 @@ static void aspeed_gpio_register_types(void)
type_register_static(&aspeed_gpio_info);
type_register_static(&aspeed_gpio_ast2400_info);
type_register_static(&aspeed_gpio_ast2500_info);
- type_register_static(&aspeed_gpio_ast2600_3_6v_info);
+ type_register_static(&aspeed_gpio_ast2600_3_3v_info);
type_register_static(&aspeed_gpio_ast2600_1_8v_info);
}
--
2.31.1
^ permalink raw reply related [flat|nested] 19+ messages in thread
* [PATCH 06/10] misc/pca9552: Fix LED status register indexing in pca955x_get_led()
2021-08-09 13:15 [PATCH 00/10] Aspeed: 6.2 queue Cédric Le Goater
` (4 preceding siblings ...)
2021-08-09 13:15 ` [PATCH 05/10] hw: aspeed_gpio: Clarify GPIO controller name Cédric Le Goater
@ 2021-08-09 13:15 ` Cédric Le Goater
2021-08-09 13:15 ` [PATCH 07/10] arm/aspeed: rainier: Add i2c eeproms and muxes Cédric Le Goater
` (3 subsequent siblings)
9 siblings, 0 replies; 19+ messages in thread
From: Cédric Le Goater @ 2021-08-09 13:15 UTC (permalink / raw)
To: Peter Maydell
Cc: Andrew Jeffery, Cédric Le Goater, qemu-arm, Joel Stanley,
qemu-devel
From: Andrew Jeffery <andrew@aj.id.au>
There was a bit of a thinko in the state calculation where every odd pin
in was reported in e.g. "pwm0" mode rather than "off". This was the
result of an incorrect bit shift for the 2-bit field representing each
LED state.
Fixes: a90d8f84674d ("misc/pca9552: Add qom set and get")
Signed-off-by: Andrew Jeffery <andrew@aj.id.au>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Message-Id: <20210723043624.348158-1-andrew@aj.id.au>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
---
hw/misc/pca9552.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/hw/misc/pca9552.c b/hw/misc/pca9552.c
index b7686e27d7fa..fff19e369a39 100644
--- a/hw/misc/pca9552.c
+++ b/hw/misc/pca9552.c
@@ -272,7 +272,7 @@ static void pca955x_get_led(Object *obj, Visitor *v, const char *name,
* reading the INPUTx reg
*/
reg = PCA9552_LS0 + led / 4;
- state = (pca955x_read(s, reg) >> (led % 8)) & 0x3;
+ state = (pca955x_read(s, reg) >> ((led % 4) * 2)) & 0x3;
visit_type_str(v, name, (char **)&led_state[state], errp);
}
--
2.31.1
^ permalink raw reply related [flat|nested] 19+ messages in thread
* [PATCH 07/10] arm/aspeed: rainier: Add i2c eeproms and muxes
2021-08-09 13:15 [PATCH 00/10] Aspeed: 6.2 queue Cédric Le Goater
` (5 preceding siblings ...)
2021-08-09 13:15 ` [PATCH 06/10] misc/pca9552: Fix LED status register indexing in pca955x_get_led() Cédric Le Goater
@ 2021-08-09 13:15 ` Cédric Le Goater
2021-08-09 13:15 ` [PATCH 08/10] aspeed: Emulate the AST2600A3 Cédric Le Goater
` (2 subsequent siblings)
9 siblings, 0 replies; 19+ messages in thread
From: Cédric Le Goater @ 2021-08-09 13:15 UTC (permalink / raw)
To: Peter Maydell
Cc: Andrew Jeffery, Cédric Le Goater, qemu-arm, Joel Stanley,
qemu-devel
From: Joel Stanley <joel@jms.id.au>
These are the devices documented by the Rainier device tree. With this
we can see the guest discovering the multiplexers and probing the eeprom
devices:
i2c i2c-2: Added multiplexed i2c bus 16
i2c i2c-2: Added multiplexed i2c bus 17
i2c i2c-2: Added multiplexed i2c bus 18
i2c i2c-2: Added multiplexed i2c bus 19
i2c-mux-gpio i2cmux: 4 port mux on 1e78a180.i2c-bus adapter
at24 20-0050: 8192 byte 24c64 EEPROM, writable, 1 bytes/write
i2c i2c-4: Added multiplexed i2c bus 20
at24 21-0051: 8192 byte 24c64 EEPROM, writable, 1 bytes/write
i2c i2c-4: Added multiplexed i2c bus 21
at24 22-0052: 8192 byte 24c64 EEPROM, writable, 1 bytes/write
Signed-off-by: Joel Stanley <joel@jms.id.au>
[ clg: Introduced aspeed_eeprom_init ]
Message-Id: <20210625050643.161042-1-joel@jms.id.au>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Message-Id: <20210629142336.750058-2-clg@kaod.org>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
---
hw/arm/aspeed.c | 44 ++++++++++++++++++++++++++++++++++++++++++++
1 file changed, 44 insertions(+)
diff --git a/hw/arm/aspeed.c b/hw/arm/aspeed.c
index ecf0c9cfacb8..c93941789fd4 100644
--- a/hw/arm/aspeed.c
+++ b/hw/arm/aspeed.c
@@ -674,9 +674,21 @@ static void g220a_bmc_i2c_init(AspeedMachineState *bmc)
eeprom_buf);
}
+static void aspeed_eeprom_init(I2CBus *bus, uint8_t addr, uint32_t rsize)
+{
+ I2CSlave *i2c_dev = i2c_slave_new("at24c-eeprom", addr);
+ DeviceState *dev = DEVICE(i2c_dev);
+
+ qdev_prop_set_uint32(dev, "rom-size", rsize);
+ i2c_slave_realize_and_unref(i2c_dev, bus, &error_abort);
+}
+
static void rainier_bmc_i2c_init(AspeedMachineState *bmc)
{
AspeedSoCState *soc = &bmc->soc;
+ I2CSlave *i2c_mux;
+
+ aspeed_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 0), 0x51, 32 * KiB);
/* The rainier expects a TMP275 but a TMP105 is compatible */
i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 4), TYPE_TMP105,
@@ -685,11 +697,20 @@ static void rainier_bmc_i2c_init(AspeedMachineState *bmc)
0x49);
i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 4), TYPE_TMP105,
0x4a);
+ i2c_mux = i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 4),
+ "pca9546", 0x70);
+ aspeed_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 0), 0x50, 64 * KiB);
+ aspeed_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 1), 0x51, 64 * KiB);
+ aspeed_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 2), 0x52, 64 * KiB);
i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 5), TYPE_TMP105,
0x48);
i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 5), TYPE_TMP105,
0x49);
+ i2c_mux = i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 5),
+ "pca9546", 0x70);
+ aspeed_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 0), 0x50, 64 * KiB);
+ aspeed_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 1), 0x51, 64 * KiB);
i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 6), TYPE_TMP105,
0x48);
@@ -697,6 +718,12 @@ static void rainier_bmc_i2c_init(AspeedMachineState *bmc)
0x4a);
i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 6), TYPE_TMP105,
0x4b);
+ i2c_mux = i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 6),
+ "pca9546", 0x70);
+ aspeed_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 0), 0x50, 64 * KiB);
+ aspeed_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 1), 0x51, 64 * KiB);
+ aspeed_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 2), 0x50, 64 * KiB);
+ aspeed_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 3), 0x51, 64 * KiB);
/* Bus 7: TODO dps310@76 */
/* Bus 7: TODO max31785@52 */
@@ -704,11 +731,15 @@ static void rainier_bmc_i2c_init(AspeedMachineState *bmc)
/* Bus 7: TODO si7021-a20@20 */
i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 7), TYPE_TMP105,
0x48);
+ aspeed_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 7), 0x50, 64 * KiB);
+ aspeed_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 7), 0x51, 64 * KiB);
i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 8), TYPE_TMP105,
0x48);
i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 8), TYPE_TMP105,
0x4a);
+ aspeed_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 8), 0x50, 64 * KiB);
+ aspeed_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 8), 0x51, 64 * KiB);
i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 8), "pca9552", 0x61);
/* Bus 8: ucd90320@11 */
/* Bus 8: ucd90320@b */
@@ -716,14 +747,27 @@ static void rainier_bmc_i2c_init(AspeedMachineState *bmc)
i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 9), "tmp423", 0x4c);
i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 9), "tmp423", 0x4d);
+ aspeed_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 9), 0x50, 128 * KiB);
i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 10), "tmp423", 0x4c);
i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 10), "tmp423", 0x4d);
+ aspeed_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 10), 0x50, 128 * KiB);
i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 11), TYPE_TMP105,
0x48);
i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 11), TYPE_TMP105,
0x49);
+ i2c_mux = i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 11),
+ "pca9546", 0x70);
+ aspeed_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 0), 0x50, 64 * KiB);
+ aspeed_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 1), 0x51, 64 * KiB);
+
+
+ aspeed_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 13), 0x50, 64 * KiB);
+
+ aspeed_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 14), 0x50, 64 * KiB);
+
+ aspeed_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 15), 0x50, 64 * KiB);
}
static bool aspeed_get_mmio_exec(Object *obj, Error **errp)
--
2.31.1
^ permalink raw reply related [flat|nested] 19+ messages in thread
* [PATCH 08/10] aspeed: Emulate the AST2600A3
2021-08-09 13:15 [PATCH 00/10] Aspeed: 6.2 queue Cédric Le Goater
` (6 preceding siblings ...)
2021-08-09 13:15 ` [PATCH 07/10] arm/aspeed: rainier: Add i2c eeproms and muxes Cédric Le Goater
@ 2021-08-09 13:15 ` Cédric Le Goater
2021-08-09 15:55 ` Philippe Mathieu-Daudé
2021-08-09 13:15 ` [PATCH 09/10] hw/misc: Add Infineon DPS310 sensor model Cédric Le Goater
2021-08-09 13:15 ` [PATCH 10/10] arm/aspeed: Add DPS310 to Witherspoon and Rainier Cédric Le Goater
9 siblings, 1 reply; 19+ messages in thread
From: Cédric Le Goater @ 2021-08-09 13:15 UTC (permalink / raw)
To: Peter Maydell
Cc: Andrew Jeffery, Cédric Le Goater, qemu-arm, Joel Stanley,
qemu-devel
From: Joel Stanley <joel@jms.id.au>
This is the latest revision of the ASPEED 2600 SoC. As there is no
need to model multiple revisions of the same SoC for the moment,
update the SCU AST2600 to model the A3 revision instead of the A1 and
adapt the AST2600 SoC and machines.
Reset values are taken from v8 of the datasheet.
Signed-off-by: Joel Stanley <joel@jms.id.au>
[ clg: - Introduced an Aspeed "ast2600-a3" SoC class
- Commit log update ]
Message-Id: <20210407171637.777743-21-clg@kaod.org>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Message-Id: <20210629142336.750058-3-clg@kaod.org>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
---
include/hw/misc/aspeed_scu.h | 2 ++
hw/arm/aspeed.c | 6 +++---
hw/arm/aspeed_ast2600.c | 6 +++---
hw/misc/aspeed_scu.c | 36 +++++++++++++++++++++++++++++-------
4 files changed, 37 insertions(+), 13 deletions(-)
diff --git a/include/hw/misc/aspeed_scu.h b/include/hw/misc/aspeed_scu.h
index d49bfb02fbdb..c14aff2bcbb5 100644
--- a/include/hw/misc/aspeed_scu.h
+++ b/include/hw/misc/aspeed_scu.h
@@ -43,6 +43,8 @@ struct AspeedSCUState {
#define AST2500_A1_SILICON_REV 0x04010303U
#define AST2600_A0_SILICON_REV 0x05000303U
#define AST2600_A1_SILICON_REV 0x05010303U
+#define AST2600_A2_SILICON_REV 0x05020303U
+#define AST2600_A3_SILICON_REV 0x05030303U
#define ASPEED_IS_AST2500(si_rev) ((((si_rev) >> 24) & 0xff) == 0x04)
diff --git a/hw/arm/aspeed.c b/hw/arm/aspeed.c
index c93941789fd4..1ea09584d1f6 100644
--- a/hw/arm/aspeed.c
+++ b/hw/arm/aspeed.c
@@ -997,7 +997,7 @@ static void aspeed_machine_ast2600_evb_class_init(ObjectClass *oc, void *data)
AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc);
mc->desc = "Aspeed AST2600 EVB (Cortex-A7)";
- amc->soc_name = "ast2600-a1";
+ amc->soc_name = "ast2600-a3";
amc->hw_strap1 = AST2600_EVB_HW_STRAP1;
amc->hw_strap2 = AST2600_EVB_HW_STRAP2;
amc->fmc_model = "w25q512jv";
@@ -1017,7 +1017,7 @@ static void aspeed_machine_tacoma_class_init(ObjectClass *oc, void *data)
AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc);
mc->desc = "OpenPOWER Tacoma BMC (Cortex-A7)";
- amc->soc_name = "ast2600-a1";
+ amc->soc_name = "ast2600-a3";
amc->hw_strap1 = TACOMA_BMC_HW_STRAP1;
amc->hw_strap2 = TACOMA_BMC_HW_STRAP2;
amc->fmc_model = "mx66l1g45g";
@@ -1054,7 +1054,7 @@ static void aspeed_machine_rainier_class_init(ObjectClass *oc, void *data)
AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc);
mc->desc = "IBM Rainier BMC (Cortex-A7)";
- amc->soc_name = "ast2600-a1";
+ amc->soc_name = "ast2600-a3";
amc->hw_strap1 = RAINIER_BMC_HW_STRAP1;
amc->hw_strap2 = RAINIER_BMC_HW_STRAP2;
amc->fmc_model = "mx66l1g45g";
diff --git a/hw/arm/aspeed_ast2600.c b/hw/arm/aspeed_ast2600.c
index e3013128c670..8e1993790e6f 100644
--- a/hw/arm/aspeed_ast2600.c
+++ b/hw/arm/aspeed_ast2600.c
@@ -516,9 +516,9 @@ static void aspeed_soc_ast2600_class_init(ObjectClass *oc, void *data)
dc->realize = aspeed_soc_ast2600_realize;
- sc->name = "ast2600-a1";
+ sc->name = "ast2600-a3";
sc->cpu_type = ARM_CPU_TYPE_NAME("cortex-a7");
- sc->silicon_rev = AST2600_A1_SILICON_REV;
+ sc->silicon_rev = AST2600_A3_SILICON_REV;
sc->sram_size = 0x16400;
sc->spis_num = 2;
sc->ehcis_num = 2;
@@ -530,7 +530,7 @@ static void aspeed_soc_ast2600_class_init(ObjectClass *oc, void *data)
}
static const TypeInfo aspeed_soc_ast2600_type_info = {
- .name = "ast2600-a1",
+ .name = "ast2600-a3",
.parent = TYPE_ASPEED_SOC,
.instance_size = sizeof(AspeedSoCState),
.instance_init = aspeed_soc_ast2600_init,
diff --git a/hw/misc/aspeed_scu.c b/hw/misc/aspeed_scu.c
index 40a38ebd8549..05edebedeb46 100644
--- a/hw/misc/aspeed_scu.c
+++ b/hw/misc/aspeed_scu.c
@@ -101,14 +101,24 @@
#define AST2600_CLK_STOP_CTRL_CLR TO_REG(0x84)
#define AST2600_CLK_STOP_CTRL2 TO_REG(0x90)
#define AST2600_CLK_STOP_CTRL2_CLR TO_REG(0x94)
+#define AST2600_DEBUG_CTRL TO_REG(0xC8)
+#define AST2600_DEBUG_CTRL2 TO_REG(0xD8)
#define AST2600_SDRAM_HANDSHAKE TO_REG(0x100)
#define AST2600_HPLL_PARAM TO_REG(0x200)
#define AST2600_HPLL_EXT TO_REG(0x204)
+#define AST2600_APLL_PARAM TO_REG(0x210)
+#define AST2600_APLL_EXT TO_REG(0x214)
+#define AST2600_MPLL_PARAM TO_REG(0x220)
#define AST2600_MPLL_EXT TO_REG(0x224)
+#define AST2600_EPLL_PARAM TO_REG(0x240)
#define AST2600_EPLL_EXT TO_REG(0x244)
+#define AST2600_DPLL_PARAM TO_REG(0x260)
+#define AST2600_DPLL_EXT TO_REG(0x264)
#define AST2600_CLK_SEL TO_REG(0x300)
#define AST2600_CLK_SEL2 TO_REG(0x304)
-#define AST2600_CLK_SEL3 TO_REG(0x310)
+#define AST2600_CLK_SEL3 TO_REG(0x308)
+#define AST2600_CLK_SEL4 TO_REG(0x310)
+#define AST2600_CLK_SEL5 TO_REG(0x314)
#define AST2600_HW_STRAP1 TO_REG(0x500)
#define AST2600_HW_STRAP1_CLR TO_REG(0x504)
#define AST2600_HW_STRAP1_PROT TO_REG(0x508)
@@ -433,6 +443,8 @@ static uint32_t aspeed_silicon_revs[] = {
AST2500_A1_SILICON_REV,
AST2600_A0_SILICON_REV,
AST2600_A1_SILICON_REV,
+ AST2600_A2_SILICON_REV,
+ AST2600_A3_SILICON_REV,
};
bool is_supported_silicon_rev(uint32_t silicon_rev)
@@ -651,16 +663,26 @@ static const MemoryRegionOps aspeed_ast2600_scu_ops = {
.valid.unaligned = false,
};
-static const uint32_t ast2600_a1_resets[ASPEED_AST2600_SCU_NR_REGS] = {
+static const uint32_t ast2600_a3_resets[ASPEED_AST2600_SCU_NR_REGS] = {
[AST2600_SYS_RST_CTRL] = 0xF7C3FED8,
- [AST2600_SYS_RST_CTRL2] = 0xFFFFFFFC,
+ [AST2600_SYS_RST_CTRL2] = 0x0DFFFFFC,
[AST2600_CLK_STOP_CTRL] = 0xFFFF7F8A,
[AST2600_CLK_STOP_CTRL2] = 0xFFF0FFF0,
+ [AST2600_DEBUG_CTRL] = 0x00000FFF,
+ [AST2600_DEBUG_CTRL2] = 0x000000FF,
[AST2600_SDRAM_HANDSHAKE] = 0x00000000,
- [AST2600_HPLL_PARAM] = 0x1000405F,
+ [AST2600_HPLL_PARAM] = 0x1000408F,
+ [AST2600_APLL_PARAM] = 0x1000405F,
+ [AST2600_MPLL_PARAM] = 0x1008405F,
+ [AST2600_EPLL_PARAM] = 0x1004077F,
+ [AST2600_DPLL_PARAM] = 0x1078405F,
+ [AST2600_CLK_SEL] = 0xF3940000,
+ [AST2600_CLK_SEL2] = 0x00700000,
+ [AST2600_CLK_SEL3] = 0x00000000,
+ [AST2600_CLK_SEL4] = 0xF3F40000,
+ [AST2600_CLK_SEL5] = 0x30000000,
[AST2600_CHIP_ID0] = 0x1234ABCD,
[AST2600_CHIP_ID1] = 0x88884444,
-
};
static void aspeed_ast2600_scu_reset(DeviceState *dev)
@@ -675,7 +697,7 @@ static void aspeed_ast2600_scu_reset(DeviceState *dev)
* of actual revision. QEMU and Linux only support A1 onwards so this is
* sufficient.
*/
- s->regs[AST2600_SILICON_REV] = AST2600_A1_SILICON_REV;
+ s->regs[AST2600_SILICON_REV] = AST2600_A3_SILICON_REV;
s->regs[AST2600_SILICON_REV2] = s->silicon_rev;
s->regs[AST2600_HW_STRAP1] = s->hw_strap1;
s->regs[AST2600_HW_STRAP2] = s->hw_strap2;
@@ -689,7 +711,7 @@ static void aspeed_2600_scu_class_init(ObjectClass *klass, void *data)
dc->desc = "ASPEED 2600 System Control Unit";
dc->reset = aspeed_ast2600_scu_reset;
- asc->resets = ast2600_a1_resets;
+ asc->resets = ast2600_a3_resets;
asc->calc_hpll = aspeed_2500_scu_calc_hpll; /* No change since AST2500 */
asc->apb_divider = 4;
asc->nr_regs = ASPEED_AST2600_SCU_NR_REGS;
--
2.31.1
^ permalink raw reply related [flat|nested] 19+ messages in thread
* [PATCH 09/10] hw/misc: Add Infineon DPS310 sensor model
2021-08-09 13:15 [PATCH 00/10] Aspeed: 6.2 queue Cédric Le Goater
` (7 preceding siblings ...)
2021-08-09 13:15 ` [PATCH 08/10] aspeed: Emulate the AST2600A3 Cédric Le Goater
@ 2021-08-09 13:15 ` Cédric Le Goater
2021-08-09 15:59 ` Philippe Mathieu-Daudé
2021-08-10 23:37 ` Corey Minyard
2021-08-09 13:15 ` [PATCH 10/10] arm/aspeed: Add DPS310 to Witherspoon and Rainier Cédric Le Goater
9 siblings, 2 replies; 19+ messages in thread
From: Cédric Le Goater @ 2021-08-09 13:15 UTC (permalink / raw)
To: Peter Maydell
Cc: Andrew Jeffery, Cédric Le Goater, qemu-arm, Joel Stanley,
qemu-devel
From: Joel Stanley <joel@jms.id.au>
This contains some hardcoded register values that were obtained from the
hardware after reading the temperature.
It does enough to test the Linux kernel driver. The FIFO mode, IRQs and
operation modes other than the default as used by Linux are not modelled.
Signed-off-by: Joel Stanley <joel@jms.id.au>
[ clg: Fix sequential reading ]
Message-Id: <20210616073358.750472-2-joel@jms.id.au>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Message-Id: <20210629142336.750058-4-clg@kaod.org>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
---
hw/misc/dps310.c | 227 ++++++++++++++++++++++++++++++++++++++++++++
hw/arm/Kconfig | 1 +
hw/misc/Kconfig | 4 +
hw/misc/meson.build | 1 +
4 files changed, 233 insertions(+)
create mode 100644 hw/misc/dps310.c
diff --git a/hw/misc/dps310.c b/hw/misc/dps310.c
new file mode 100644
index 000000000000..893521ab8516
--- /dev/null
+++ b/hw/misc/dps310.c
@@ -0,0 +1,227 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+/*
+ * Copyright 2017-2021 Joel Stanley <joel@jms.id.au>, IBM Corporation
+ *
+ * Infineon DPS310 temperature and humidity sensor
+ *
+ * https://www.infineon.com/cms/en/product/sensor/pressure-sensors/pressure-sensors-for-iot/dps310/
+ */
+
+#include "qemu/osdep.h"
+#include "qemu/log.h"
+#include "hw/hw.h"
+#include "hw/i2c/i2c.h"
+#include "qapi/error.h"
+#include "qapi/visitor.h"
+#include "migration/vmstate.h"
+
+#define NUM_REGISTERS 0x33
+
+typedef struct DPS310State {
+ /*< private >*/
+ I2CSlave i2c;
+
+ /*< public >*/
+ uint8_t regs[NUM_REGISTERS];
+
+ uint8_t len;
+ uint8_t pointer;
+
+} DPS310State;
+
+#define TYPE_DPS310 "dps310"
+#define DPS310(obj) OBJECT_CHECK(DPS310State, (obj), TYPE_DPS310)
+
+#define DPS310_PRS_B2 0x00
+#define DPS310_PRS_B1 0x01
+#define DPS310_PRS_B0 0x02
+#define DPS310_TMP_B2 0x03
+#define DPS310_TMP_B1 0x04
+#define DPS310_TMP_B0 0x05
+#define DPS310_PRS_CFG 0x06
+#define DPS310_TMP_CFG 0x07
+#define DPS310_TMP_RATE_BITS (0x70)
+#define DPS310_MEAS_CFG 0x08
+#define DPS310_MEAS_CTRL_BITS (0x07)
+#define DPS310_PRESSURE_EN BIT(0)
+#define DPS310_TEMP_EN BIT(1)
+#define DPS310_BACKGROUND BIT(2)
+#define DPS310_PRS_RDY BIT(4)
+#define DPS310_TMP_RDY BIT(5)
+#define DPS310_SENSOR_RDY BIT(6)
+#define DPS310_COEF_RDY BIT(7)
+#define DPS310_CFG_REG 0x09
+#define DPS310_RESET 0x0c
+#define DPS310_RESET_MAGIC (BIT(0) | BIT(3))
+#define DPS310_COEF_BASE 0x10
+#define DPS310_COEF_LAST 0x21
+#define DPS310_COEF_SRC 0x28
+
+static void dps310_reset(DeviceState *dev)
+{
+ DPS310State *s = DPS310(dev);
+
+ static const uint8_t regs_reset_state[] = {
+ 0xfe, 0x2f, 0xee, 0x02, 0x69, 0xa6, 0x00, 0x80, 0xc7, 0x00, 0x00, 0x00,
+ 0x00, 0x10, 0x00, 0x00, 0x0e, 0x1e, 0xdd, 0x13, 0xca, 0x5f, 0x21, 0x52,
+ 0xf9, 0xc6, 0x04, 0xd1, 0xdb, 0x47, 0x00, 0x5b, 0xfb, 0x3a, 0x00, 0x00,
+ 0x20, 0x49, 0x4e, 0xa5, 0x90, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x60, 0x15, 0x02
+ };
+
+ QEMU_BUILD_BUG_ON(sizeof(regs_reset_state) != sizeof(s->regs));
+
+ memcpy(s->regs, regs_reset_state, sizeof(s->regs));
+ s->pointer = 0;
+
+ /* TODO: assert these after some timeout ? */
+ s->regs[DPS310_MEAS_CFG] = DPS310_COEF_RDY | DPS310_SENSOR_RDY
+ | DPS310_TMP_RDY | DPS310_PRS_RDY;
+}
+
+static uint8_t dps310_read(DPS310State *s, uint8_t reg)
+{
+ if (reg >= sizeof(s->regs)) {
+ qemu_log_mask(LOG_GUEST_ERROR, "%s: register 0x%02x out of bounds\n",
+ __func__, s->pointer);
+ return 0xFF;
+ }
+
+ switch (reg) {
+ case DPS310_PRS_B2:
+ case DPS310_PRS_B1:
+ case DPS310_PRS_B0:
+ case DPS310_TMP_B2:
+ case DPS310_TMP_B1:
+ case DPS310_TMP_B0:
+ case DPS310_PRS_CFG:
+ case DPS310_TMP_CFG:
+ case DPS310_MEAS_CFG:
+ case DPS310_CFG_REG:
+ case DPS310_COEF_BASE...DPS310_COEF_LAST:
+ case DPS310_COEF_SRC:
+ case 0x32: /* Undocumented register to indicate workaround not required */
+ return s->regs[reg];
+ default:
+ qemu_log_mask(LOG_UNIMP, "%s: register 0x%02x unimplemented\n",
+ __func__, reg);
+ return 0xFF;
+ }
+}
+
+static void dps310_write(DPS310State *s, uint8_t reg, uint8_t data)
+{
+ if (reg >= sizeof(s->regs)) {
+ qemu_log_mask(LOG_GUEST_ERROR, "%s: register %d out of bounds\n",
+ __func__, s->pointer);
+ return;
+ }
+
+ switch (reg) {
+ case DPS310_RESET:
+ if (data == DPS310_RESET_MAGIC) {
+ device_cold_reset(DEVICE(s));
+ }
+ break;
+ case DPS310_PRS_CFG:
+ case DPS310_TMP_CFG:
+ case DPS310_MEAS_CFG:
+ case DPS310_CFG_REG:
+ s->regs[reg] = data;
+ break;
+ default:
+ qemu_log_mask(LOG_UNIMP, "%s: register 0x%02x unimplemented\n",
+ __func__, reg);
+ return;
+ }
+}
+
+static uint8_t dps310_rx(I2CSlave *i2c)
+{
+ DPS310State *s = DPS310(i2c);
+
+ if (s->len == 1) {
+ return dps310_read(s, s->pointer++);
+ } else {
+ return 0xFF;
+ }
+}
+
+static int dps310_tx(I2CSlave *i2c, uint8_t data)
+{
+ DPS310State *s = DPS310(i2c);
+
+ if (s->len == 0) {
+ /*
+ * first byte is the register pointer for a read or write
+ * operation
+ */
+ s->pointer = data;
+ s->len++;
+ } else if (s->len == 1) {
+ dps310_write(s, s->pointer++, data);
+ }
+
+ return 0;
+}
+
+static int dps310_event(I2CSlave *i2c, enum i2c_event event)
+{
+ DPS310State *s = DPS310(i2c);
+
+ switch (event) {
+ case I2C_START_SEND:
+ s->pointer = 0xFF;
+ s->len = 0;
+ break;
+ case I2C_START_RECV:
+ if (s->len != 1) {
+ qemu_log_mask(LOG_GUEST_ERROR, "%s: invalid recv sequence\n",
+ __func__);
+ }
+ break;
+ default:
+ break;
+ }
+
+ return 0;
+}
+
+static const VMStateDescription vmstate_dps310 = {
+ .name = "DPS310",
+ .version_id = 0,
+ .minimum_version_id = 0,
+ .fields = (VMStateField[]) {
+ VMSTATE_UINT8(len, DPS310State),
+ VMSTATE_UINT8_ARRAY(regs, DPS310State, NUM_REGISTERS),
+ VMSTATE_UINT8(pointer, DPS310State),
+ VMSTATE_I2C_SLAVE(i2c, DPS310State),
+ VMSTATE_END_OF_LIST()
+ }
+};
+
+static void dps310_class_init(ObjectClass *klass, void *data)
+{
+ DeviceClass *dc = DEVICE_CLASS(klass);
+ I2CSlaveClass *k = I2C_SLAVE_CLASS(klass);
+
+ k->event = dps310_event;
+ k->recv = dps310_rx;
+ k->send = dps310_tx;
+ dc->reset = dps310_reset;
+ dc->vmsd = &vmstate_dps310;
+}
+
+static const TypeInfo dps310_info = {
+ .name = TYPE_DPS310,
+ .parent = TYPE_I2C_SLAVE,
+ .instance_size = sizeof(DPS310State),
+ .class_init = dps310_class_init,
+};
+
+static void dps310_register_types(void)
+{
+ type_register_static(&dps310_info);
+}
+
+type_init(dps310_register_types)
diff --git a/hw/arm/Kconfig b/hw/arm/Kconfig
index 4ba0aca0676b..2c4e2df470d2 100644
--- a/hw/arm/Kconfig
+++ b/hw/arm/Kconfig
@@ -429,6 +429,7 @@ config ASPEED_SOC
select DS1338
select FTGMAC100
select I2C
+ select DPS310
select PCA9552
select SERIAL
select SMBUS_EEPROM
diff --git a/hw/misc/Kconfig b/hw/misc/Kconfig
index 507058d8bffb..1c913dc3b837 100644
--- a/hw/misc/Kconfig
+++ b/hw/misc/Kconfig
@@ -34,6 +34,10 @@ config EDU
default y if TEST_DEVICES
depends on PCI && MSI_NONBROKEN
+config DPS310
+ bool
+ depends on I2C
+
config PCA9552
bool
depends on I2C
diff --git a/hw/misc/meson.build b/hw/misc/meson.build
index a53b849a5a0b..93b90ecd39e4 100644
--- a/hw/misc/meson.build
+++ b/hw/misc/meson.build
@@ -1,4 +1,5 @@
softmmu_ss.add(when: 'CONFIG_APPLESMC', if_true: files('applesmc.c'))
+softmmu_ss.add(when: 'CONFIG_DPS310', if_true: files('dps310.c'))
softmmu_ss.add(when: 'CONFIG_EDU', if_true: files('edu.c'))
softmmu_ss.add(when: 'CONFIG_FW_CFG_DMA', if_true: files('vmcoreinfo.c'))
softmmu_ss.add(when: 'CONFIG_ISA_DEBUG', if_true: files('debugexit.c'))
--
2.31.1
^ permalink raw reply related [flat|nested] 19+ messages in thread
* [PATCH 10/10] arm/aspeed: Add DPS310 to Witherspoon and Rainier
2021-08-09 13:15 [PATCH 00/10] Aspeed: 6.2 queue Cédric Le Goater
` (8 preceding siblings ...)
2021-08-09 13:15 ` [PATCH 09/10] hw/misc: Add Infineon DPS310 sensor model Cédric Le Goater
@ 2021-08-09 13:15 ` Cédric Le Goater
9 siblings, 0 replies; 19+ messages in thread
From: Cédric Le Goater @ 2021-08-09 13:15 UTC (permalink / raw)
To: Peter Maydell
Cc: Andrew Jeffery, Cédric Le Goater, qemu-arm, Joel Stanley,
qemu-devel
From: Joel Stanley <joel@jms.id.au>
Witherspoon uses the DPS310 as a temperature sensor. Rainier uses it as
a temperature and humidity sensor.
Signed-off-by: Joel Stanley <joel@jms.id.au>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Message-Id: <20210616073358.750472-3-joel@jms.id.au>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Message-Id: <20210629142336.750058-5-clg@kaod.org>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
---
hw/arm/aspeed.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/hw/arm/aspeed.c b/hw/arm/aspeed.c
index 1ea09584d1f6..e2623c9d3a57 100644
--- a/hw/arm/aspeed.c
+++ b/hw/arm/aspeed.c
@@ -602,7 +602,6 @@ static void witherspoon_bmc_i2c_init(AspeedMachineState *bmc)
/* Bus 3: TODO bmp280@77 */
/* Bus 3: TODO max31785@52 */
- /* Bus 3: TODO dps310@76 */
dev = DEVICE(i2c_slave_new(TYPE_PCA9552, 0x60));
qdev_prop_set_string(dev, "description", "pca1");
i2c_slave_realize_and_unref(I2C_SLAVE(dev),
@@ -617,6 +616,7 @@ static void witherspoon_bmc_i2c_init(AspeedMachineState *bmc)
qdev_connect_gpio_out(dev, pca1_leds[i].gpio_id,
qdev_get_gpio_in(DEVICE(led), 0));
}
+ i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 3), "dps310", 0x76);
i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 4), "tmp423", 0x4c);
i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 5), "tmp423", 0x4c);
@@ -725,9 +725,9 @@ static void rainier_bmc_i2c_init(AspeedMachineState *bmc)
aspeed_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 2), 0x50, 64 * KiB);
aspeed_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 3), 0x51, 64 * KiB);
- /* Bus 7: TODO dps310@76 */
/* Bus 7: TODO max31785@52 */
i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 7), "pca9552", 0x61);
+ i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 7), "dps310", 0x76);
/* Bus 7: TODO si7021-a20@20 */
i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 7), TYPE_TMP105,
0x48);
--
2.31.1
^ permalink raw reply related [flat|nested] 19+ messages in thread
* Re: [PATCH 03/10] watchdog: aspeed: Fix sequential control writes
2021-08-09 13:15 ` [PATCH 03/10] watchdog: aspeed: Fix sequential control writes Cédric Le Goater
@ 2021-08-09 15:48 ` Philippe Mathieu-Daudé
0 siblings, 0 replies; 19+ messages in thread
From: Philippe Mathieu-Daudé @ 2021-08-09 15:48 UTC (permalink / raw)
To: Cédric Le Goater, Peter Maydell
Cc: Andrew Jeffery, qemu-arm, Joel Stanley, qemu-devel
On 8/9/21 3:15 PM, Cédric Le Goater wrote:
> From: Andrew Jeffery <andrew@aj.id.au>
>
> The logic in the handling for the control register required toggling the
> enable state for writes to stick. Rework the condition chain to allow
> sequential writes that do not update the enable state.
>
> Fixes: 854123bf8d4b ("wdt: Add Aspeed watchdog device model")
> Signed-off-by: Andrew Jeffery <andrew@aj.id.au>
> Reviewed-by: Cédric Le Goater <clg@kaod.org>
> Message-Id: <20210709053107.1829304-3-andrew@aj.id.au>
> Signed-off-by: Cédric Le Goater <clg@kaod.org>
> ---
> hw/watchdog/wdt_aspeed.c | 2 ++
> 1 file changed, 2 insertions(+)
>
> diff --git a/hw/watchdog/wdt_aspeed.c b/hw/watchdog/wdt_aspeed.c
> index faa3d35fdf21..69c37af9a6e9 100644
> --- a/hw/watchdog/wdt_aspeed.c
> +++ b/hw/watchdog/wdt_aspeed.c
> @@ -166,6 +166,8 @@ static void aspeed_wdt_write(void *opaque, hwaddr offset, uint64_t data,
> } else if (!enable && aspeed_wdt_is_enabled(s)) {
> s->regs[WDT_CTRL] = data;
> timer_del(s->timer);
> + } else {
> + s->regs[WDT_CTRL] = data;
> }
Alternatively easier to review:
} else {
if (!enable && aspeed_wdt_is_enabled(s)) {
timer_del(s->timer);
}
s->regs[WDT_CTRL] = data;
}
> break;
> case WDT_RESET_WIDTH:
>
^ permalink raw reply [flat|nested] 19+ messages in thread
* Re: [PATCH 08/10] aspeed: Emulate the AST2600A3
2021-08-09 13:15 ` [PATCH 08/10] aspeed: Emulate the AST2600A3 Cédric Le Goater
@ 2021-08-09 15:55 ` Philippe Mathieu-Daudé
2021-08-11 8:09 ` Cédric Le Goater
0 siblings, 1 reply; 19+ messages in thread
From: Philippe Mathieu-Daudé @ 2021-08-09 15:55 UTC (permalink / raw)
To: Cédric Le Goater, Peter Maydell
Cc: Andrew Jeffery, qemu-arm, Joel Stanley, qemu-devel
On 8/9/21 3:15 PM, Cédric Le Goater wrote:
> From: Joel Stanley <joel@jms.id.au>
>
> This is the latest revision of the ASPEED 2600 SoC. As there is no
> need to model multiple revisions of the same SoC for the moment,
> update the SCU AST2600 to model the A3 revision instead of the A1 and
> adapt the AST2600 SoC and machines.
>
> Reset values are taken from v8 of the datasheet.
>
> Signed-off-by: Joel Stanley <joel@jms.id.au>
> [ clg: - Introduced an Aspeed "ast2600-a3" SoC class
> - Commit log update ]
> Message-Id: <20210407171637.777743-21-clg@kaod.org>
> Signed-off-by: Cédric Le Goater <clg@kaod.org>
> Message-Id: <20210629142336.750058-3-clg@kaod.org>
> Signed-off-by: Cédric Le Goater <clg@kaod.org>
> ---
> include/hw/misc/aspeed_scu.h | 2 ++
> hw/arm/aspeed.c | 6 +++---
> hw/arm/aspeed_ast2600.c | 6 +++---
> hw/misc/aspeed_scu.c | 36 +++++++++++++++++++++++++++++-------
> 4 files changed, 37 insertions(+), 13 deletions(-)
> diff --git a/hw/misc/aspeed_scu.c b/hw/misc/aspeed_scu.c
> index 40a38ebd8549..05edebedeb46 100644
> --- a/hw/misc/aspeed_scu.c
> +++ b/hw/misc/aspeed_scu.c
> @@ -101,14 +101,24 @@
> #define AST2600_CLK_STOP_CTRL_CLR TO_REG(0x84)
> #define AST2600_CLK_STOP_CTRL2 TO_REG(0x90)
> #define AST2600_CLK_STOP_CTRL2_CLR TO_REG(0x94)
> +#define AST2600_DEBUG_CTRL TO_REG(0xC8)
> +#define AST2600_DEBUG_CTRL2 TO_REG(0xD8)
> #define AST2600_SDRAM_HANDSHAKE TO_REG(0x100)
> #define AST2600_HPLL_PARAM TO_REG(0x200)
> #define AST2600_HPLL_EXT TO_REG(0x204)
> +#define AST2600_APLL_PARAM TO_REG(0x210)
> +#define AST2600_APLL_EXT TO_REG(0x214)
> +#define AST2600_MPLL_PARAM TO_REG(0x220)
> #define AST2600_MPLL_EXT TO_REG(0x224)
> +#define AST2600_EPLL_PARAM TO_REG(0x240)
> #define AST2600_EPLL_EXT TO_REG(0x244)
> +#define AST2600_DPLL_PARAM TO_REG(0x260)
> +#define AST2600_DPLL_EXT TO_REG(0x264)
> #define AST2600_CLK_SEL TO_REG(0x300)
> #define AST2600_CLK_SEL2 TO_REG(0x304)
> -#define AST2600_CLK_SEL3 TO_REG(0x310)
> +#define AST2600_CLK_SEL3 TO_REG(0x308)
Is it a bugfix? Otherwise this is annoying.
Maybe:
#define AST2600A1_CLK_SEL3 TO_REG(0x310)
#define AST2600A3_CLK_SEL3 TO_REG(0x308)
and...
> +#define AST2600_CLK_SEL4 TO_REG(0x310)
> +#define AST2600_CLK_SEL5 TO_REG(0x314)
> #define AST2600_HW_STRAP1 TO_REG(0x500)
> #define AST2600_HW_STRAP1_CLR TO_REG(0x504)
> #define AST2600_HW_STRAP1_PROT TO_REG(0x508)
> @@ -433,6 +443,8 @@ static uint32_t aspeed_silicon_revs[] = {
> AST2500_A1_SILICON_REV,
> AST2600_A0_SILICON_REV,
> AST2600_A1_SILICON_REV,
> + AST2600_A2_SILICON_REV,
> + AST2600_A3_SILICON_REV,
> };
>
> bool is_supported_silicon_rev(uint32_t silicon_rev)
> @@ -651,16 +663,26 @@ static const MemoryRegionOps aspeed_ast2600_scu_ops = {
> .valid.unaligned = false,
> };
>
> -static const uint32_t ast2600_a1_resets[ASPEED_AST2600_SCU_NR_REGS] = {
> +static const uint32_t ast2600_a3_resets[ASPEED_AST2600_SCU_NR_REGS] = {
> [AST2600_SYS_RST_CTRL] = 0xF7C3FED8,
> - [AST2600_SYS_RST_CTRL2] = 0xFFFFFFFC,
> + [AST2600_SYS_RST_CTRL2] = 0x0DFFFFFC,
> [AST2600_CLK_STOP_CTRL] = 0xFFFF7F8A,
> [AST2600_CLK_STOP_CTRL2] = 0xFFF0FFF0,
> + [AST2600_DEBUG_CTRL] = 0x00000FFF,
> + [AST2600_DEBUG_CTRL2] = 0x000000FF,
> [AST2600_SDRAM_HANDSHAKE] = 0x00000000,
> - [AST2600_HPLL_PARAM] = 0x1000405F,
> + [AST2600_HPLL_PARAM] = 0x1000408F,
> + [AST2600_APLL_PARAM] = 0x1000405F,
> + [AST2600_MPLL_PARAM] = 0x1008405F,
> + [AST2600_EPLL_PARAM] = 0x1004077F,
> + [AST2600_DPLL_PARAM] = 0x1078405F,
> + [AST2600_CLK_SEL] = 0xF3940000,
> + [AST2600_CLK_SEL2] = 0x00700000,
> + [AST2600_CLK_SEL3] = 0x00000000,
... use AST2600A3_CLK_SEL3 here?
So someone wanting the emulate the A1 doesn't get
the nasty bug of having CLK_SEL3 misplaced.
> + [AST2600_CLK_SEL4] = 0xF3F40000,
> + [AST2600_CLK_SEL5] = 0x30000000,
> [AST2600_CHIP_ID0] = 0x1234ABCD,
> [AST2600_CHIP_ID1] = 0x88884444,
> -
> };
^ permalink raw reply [flat|nested] 19+ messages in thread
* Re: [PATCH 09/10] hw/misc: Add Infineon DPS310 sensor model
2021-08-09 13:15 ` [PATCH 09/10] hw/misc: Add Infineon DPS310 sensor model Cédric Le Goater
@ 2021-08-09 15:59 ` Philippe Mathieu-Daudé
2021-08-10 14:37 ` Cédric Le Goater
2021-08-10 23:37 ` Corey Minyard
1 sibling, 1 reply; 19+ messages in thread
From: Philippe Mathieu-Daudé @ 2021-08-09 15:59 UTC (permalink / raw)
To: Cédric Le Goater, Peter Maydell
Cc: Andrew Jeffery, qemu-arm, Joel Stanley, qemu-devel
On 8/9/21 3:15 PM, Cédric Le Goater wrote:
> From: Joel Stanley <joel@jms.id.au>
>
> This contains some hardcoded register values that were obtained from the
> hardware after reading the temperature.
>
> It does enough to test the Linux kernel driver. The FIFO mode, IRQs and
> operation modes other than the default as used by Linux are not modelled.
>
> Signed-off-by: Joel Stanley <joel@jms.id.au>
> [ clg: Fix sequential reading ]
> Message-Id: <20210616073358.750472-2-joel@jms.id.au>
> Signed-off-by: Cédric Le Goater <clg@kaod.org>
> Message-Id: <20210629142336.750058-4-clg@kaod.org>
> Signed-off-by: Cédric Le Goater <clg@kaod.org>
> ---
> hw/misc/dps310.c | 227 ++++++++++++++++++++++++++++++++++++++++++++
> hw/arm/Kconfig | 1 +
> hw/misc/Kconfig | 4 +
> hw/misc/meson.build | 1 +
> 4 files changed, 233 insertions(+)
> create mode 100644 hw/misc/dps310.c
>
> diff --git a/hw/misc/dps310.c b/hw/misc/dps310.c
> new file mode 100644
> index 000000000000..893521ab8516
> --- /dev/null
> +++ b/hw/misc/dps310.c
> @@ -0,0 +1,227 @@
> +// SPDX-License-Identifier: GPL-2.0-or-later
> +/*
> + * Copyright 2017-2021 Joel Stanley <joel@jms.id.au>, IBM Corporation
> + *
> + * Infineon DPS310 temperature and humidity sensor
> + *
> + * https://www.infineon.com/cms/en/product/sensor/pressure-sensors/pressure-sensors-for-iot/dps310/
> + */
> +
> +#include "qemu/osdep.h"
> +#include "qemu/log.h"
> +#include "hw/hw.h"
> +#include "hw/i2c/i2c.h"
> +#include "qapi/error.h"
> +#include "qapi/visitor.h"
> +#include "migration/vmstate.h"
> +
> +#define NUM_REGISTERS 0x33
> +
> +typedef struct DPS310State {
> + /*< private >*/
> + I2CSlave i2c;
> +
> + /*< public >*/
> + uint8_t regs[NUM_REGISTERS];
> +
> + uint8_t len;
> + uint8_t pointer;
> +
> +} DPS310State;
> +static void dps310_reset(DeviceState *dev)
> +{
> + DPS310State *s = DPS310(dev);
> +
> + static const uint8_t regs_reset_state[] = {
static const uint8_t regs_reset_state[NUM_REGISTERS] = {
> + 0xfe, 0x2f, 0xee, 0x02, 0x69, 0xa6, 0x00, 0x80, 0xc7, 0x00, 0x00, 0x00,
> + 0x00, 0x10, 0x00, 0x00, 0x0e, 0x1e, 0xdd, 0x13, 0xca, 0x5f, 0x21, 0x52,
> + 0xf9, 0xc6, 0x04, 0xd1, 0xdb, 0x47, 0x00, 0x5b, 0xfb, 0x3a, 0x00, 0x00,
> + 0x20, 0x49, 0x4e, 0xa5, 0x90, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
> + 0x60, 0x15, 0x02
> + };
> +
> + QEMU_BUILD_BUG_ON(sizeof(regs_reset_state) != sizeof(s->regs));
and drop QEMU_BUILD_BUG_ON?
> +
> + memcpy(s->regs, regs_reset_state, sizeof(s->regs));
> + s->pointer = 0;
> +
> + /* TODO: assert these after some timeout ? */
> + s->regs[DPS310_MEAS_CFG] = DPS310_COEF_RDY | DPS310_SENSOR_RDY
> + | DPS310_TMP_RDY | DPS310_PRS_RDY;
> +}
^ permalink raw reply [flat|nested] 19+ messages in thread
* Re: [PATCH 09/10] hw/misc: Add Infineon DPS310 sensor model
2021-08-09 15:59 ` Philippe Mathieu-Daudé
@ 2021-08-10 14:37 ` Cédric Le Goater
0 siblings, 0 replies; 19+ messages in thread
From: Cédric Le Goater @ 2021-08-10 14:37 UTC (permalink / raw)
To: Philippe Mathieu-Daudé, Peter Maydell
Cc: Andrew Jeffery, qemu-arm, Joel Stanley, qemu-devel
On 8/9/21 5:59 PM, Philippe Mathieu-Daudé wrote:
> On 8/9/21 3:15 PM, Cédric Le Goater wrote:
>> From: Joel Stanley <joel@jms.id.au>
>>
>> This contains some hardcoded register values that were obtained from the
>> hardware after reading the temperature.
>>
>> It does enough to test the Linux kernel driver. The FIFO mode, IRQs and
>> operation modes other than the default as used by Linux are not modelled.
>>
>> Signed-off-by: Joel Stanley <joel@jms.id.au>
>> [ clg: Fix sequential reading ]
>> Message-Id: <20210616073358.750472-2-joel@jms.id.au>
>> Signed-off-by: Cédric Le Goater <clg@kaod.org>
>> Message-Id: <20210629142336.750058-4-clg@kaod.org>
>> Signed-off-by: Cédric Le Goater <clg@kaod.org>
>> ---
>> hw/misc/dps310.c | 227 ++++++++++++++++++++++++++++++++++++++++++++
>> hw/arm/Kconfig | 1 +
>> hw/misc/Kconfig | 4 +
>> hw/misc/meson.build | 1 +
>> 4 files changed, 233 insertions(+)
>> create mode 100644 hw/misc/dps310.c
>>
>> diff --git a/hw/misc/dps310.c b/hw/misc/dps310.c
>> new file mode 100644
>> index 000000000000..893521ab8516
>> --- /dev/null
>> +++ b/hw/misc/dps310.c
>> @@ -0,0 +1,227 @@
>> +// SPDX-License-Identifier: GPL-2.0-or-later
>> +/*
>> + * Copyright 2017-2021 Joel Stanley <joel@jms.id.au>, IBM Corporation
>> + *
>> + * Infineon DPS310 temperature and humidity sensor
>> + *
>> + * https://www.infineon.com/cms/en/product/sensor/pressure-sensors/pressure-sensors-for-iot/dps310/
>> + */
>> +
>> +#include "qemu/osdep.h"
>> +#include "qemu/log.h"
>> +#include "hw/hw.h"
>> +#include "hw/i2c/i2c.h"
>> +#include "qapi/error.h"
>> +#include "qapi/visitor.h"
>> +#include "migration/vmstate.h"
>> +
>> +#define NUM_REGISTERS 0x33
>> +
>> +typedef struct DPS310State {
>> + /*< private >*/
>> + I2CSlave i2c;
>> +
>> + /*< public >*/
>> + uint8_t regs[NUM_REGISTERS];
>> +
>> + uint8_t len;
>> + uint8_t pointer;
>> +
>> +} DPS310State;
>
>> +static void dps310_reset(DeviceState *dev)
>> +{
>> + DPS310State *s = DPS310(dev);
>> +
>> + static const uint8_t regs_reset_state[] = {
>
> static const uint8_t regs_reset_state[NUM_REGISTERS] = {
How about :
static const uint8_t regs_reset_state[sizeof(s->regs)] = {
I wonder if that compiles always. I will try with a gitlab CI.
>> + 0xfe, 0x2f, 0xee, 0x02, 0x69, 0xa6, 0x00, 0x80, 0xc7, 0x00, 0x00, 0x00,
>> + 0x00, 0x10, 0x00, 0x00, 0x0e, 0x1e, 0xdd, 0x13, 0xca, 0x5f, 0x21, 0x52,
>> + 0xf9, 0xc6, 0x04, 0xd1, 0xdb, 0x47, 0x00, 0x5b, 0xfb, 0x3a, 0x00, 0x00,
>> + 0x20, 0x49, 0x4e, 0xa5, 0x90, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
>> + 0x60, 0x15, 0x02
>> + };
>> +
>> + QEMU_BUILD_BUG_ON(sizeof(regs_reset_state) != sizeof(s->regs));
>
> and drop QEMU_BUILD_BUG_ON?
yes.
thanks,
C.
>> +
>> + memcpy(s->regs, regs_reset_state, sizeof(s->regs));
>> + s->pointer = 0;
>> +
>> + /* TODO: assert these after some timeout ? */
>> + s->regs[DPS310_MEAS_CFG] = DPS310_COEF_RDY | DPS310_SENSOR_RDY
>> + | DPS310_TMP_RDY | DPS310_PRS_RDY;
>> +}
^ permalink raw reply [flat|nested] 19+ messages in thread
* Re: [PATCH 09/10] hw/misc: Add Infineon DPS310 sensor model
2021-08-09 13:15 ` [PATCH 09/10] hw/misc: Add Infineon DPS310 sensor model Cédric Le Goater
2021-08-09 15:59 ` Philippe Mathieu-Daudé
@ 2021-08-10 23:37 ` Corey Minyard
2021-08-11 1:25 ` Joel Stanley
1 sibling, 1 reply; 19+ messages in thread
From: Corey Minyard @ 2021-08-10 23:37 UTC (permalink / raw)
To: Cédric Le Goater
Cc: Andrew Jeffery, Peter Maydell, qemu-arm, Joel Stanley, qemu-devel
On Mon, Aug 09, 2021 at 03:15:55PM +0200, Cédric Le Goater wrote:
> From: Joel Stanley <joel@jms.id.au>
>
> This contains some hardcoded register values that were obtained from the
> hardware after reading the temperature.
>
> It does enough to test the Linux kernel driver. The FIFO mode, IRQs and
> operation modes other than the default as used by Linux are not modelled.
>
> Signed-off-by: Joel Stanley <joel@jms.id.au>
> [ clg: Fix sequential reading ]
> Message-Id: <20210616073358.750472-2-joel@jms.id.au>
> Signed-off-by: Cédric Le Goater <clg@kaod.org>
> Message-Id: <20210629142336.750058-4-clg@kaod.org>
> Signed-off-by: Cédric Le Goater <clg@kaod.org>
> ---
> hw/misc/dps310.c | 227 ++++++++++++++++++++++++++++++++++++++++++++
Can this go into hw/sensor?
-corey
> hw/arm/Kconfig | 1 +
> hw/misc/Kconfig | 4 +
> hw/misc/meson.build | 1 +
> 4 files changed, 233 insertions(+)
> create mode 100644 hw/misc/dps310.c
>
> diff --git a/hw/misc/dps310.c b/hw/misc/dps310.c
> new file mode 100644
> index 000000000000..893521ab8516
> --- /dev/null
> +++ b/hw/misc/dps310.c
> @@ -0,0 +1,227 @@
> +// SPDX-License-Identifier: GPL-2.0-or-later
> +/*
> + * Copyright 2017-2021 Joel Stanley <joel@jms.id.au>, IBM Corporation
> + *
> + * Infineon DPS310 temperature and humidity sensor
> + *
> + * https://www.infineon.com/cms/en/product/sensor/pressure-sensors/pressure-sensors-for-iot/dps310/
> + */
> +
> +#include "qemu/osdep.h"
> +#include "qemu/log.h"
> +#include "hw/hw.h"
> +#include "hw/i2c/i2c.h"
> +#include "qapi/error.h"
> +#include "qapi/visitor.h"
> +#include "migration/vmstate.h"
> +
> +#define NUM_REGISTERS 0x33
> +
> +typedef struct DPS310State {
> + /*< private >*/
> + I2CSlave i2c;
> +
> + /*< public >*/
> + uint8_t regs[NUM_REGISTERS];
> +
> + uint8_t len;
> + uint8_t pointer;
> +
> +} DPS310State;
> +
> +#define TYPE_DPS310 "dps310"
> +#define DPS310(obj) OBJECT_CHECK(DPS310State, (obj), TYPE_DPS310)
> +
> +#define DPS310_PRS_B2 0x00
> +#define DPS310_PRS_B1 0x01
> +#define DPS310_PRS_B0 0x02
> +#define DPS310_TMP_B2 0x03
> +#define DPS310_TMP_B1 0x04
> +#define DPS310_TMP_B0 0x05
> +#define DPS310_PRS_CFG 0x06
> +#define DPS310_TMP_CFG 0x07
> +#define DPS310_TMP_RATE_BITS (0x70)
> +#define DPS310_MEAS_CFG 0x08
> +#define DPS310_MEAS_CTRL_BITS (0x07)
> +#define DPS310_PRESSURE_EN BIT(0)
> +#define DPS310_TEMP_EN BIT(1)
> +#define DPS310_BACKGROUND BIT(2)
> +#define DPS310_PRS_RDY BIT(4)
> +#define DPS310_TMP_RDY BIT(5)
> +#define DPS310_SENSOR_RDY BIT(6)
> +#define DPS310_COEF_RDY BIT(7)
> +#define DPS310_CFG_REG 0x09
> +#define DPS310_RESET 0x0c
> +#define DPS310_RESET_MAGIC (BIT(0) | BIT(3))
> +#define DPS310_COEF_BASE 0x10
> +#define DPS310_COEF_LAST 0x21
> +#define DPS310_COEF_SRC 0x28
> +
> +static void dps310_reset(DeviceState *dev)
> +{
> + DPS310State *s = DPS310(dev);
> +
> + static const uint8_t regs_reset_state[] = {
> + 0xfe, 0x2f, 0xee, 0x02, 0x69, 0xa6, 0x00, 0x80, 0xc7, 0x00, 0x00, 0x00,
> + 0x00, 0x10, 0x00, 0x00, 0x0e, 0x1e, 0xdd, 0x13, 0xca, 0x5f, 0x21, 0x52,
> + 0xf9, 0xc6, 0x04, 0xd1, 0xdb, 0x47, 0x00, 0x5b, 0xfb, 0x3a, 0x00, 0x00,
> + 0x20, 0x49, 0x4e, 0xa5, 0x90, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
> + 0x60, 0x15, 0x02
> + };
> +
> + QEMU_BUILD_BUG_ON(sizeof(regs_reset_state) != sizeof(s->regs));
> +
> + memcpy(s->regs, regs_reset_state, sizeof(s->regs));
> + s->pointer = 0;
> +
> + /* TODO: assert these after some timeout ? */
> + s->regs[DPS310_MEAS_CFG] = DPS310_COEF_RDY | DPS310_SENSOR_RDY
> + | DPS310_TMP_RDY | DPS310_PRS_RDY;
> +}
> +
> +static uint8_t dps310_read(DPS310State *s, uint8_t reg)
> +{
> + if (reg >= sizeof(s->regs)) {
> + qemu_log_mask(LOG_GUEST_ERROR, "%s: register 0x%02x out of bounds\n",
> + __func__, s->pointer);
> + return 0xFF;
> + }
> +
> + switch (reg) {
> + case DPS310_PRS_B2:
> + case DPS310_PRS_B1:
> + case DPS310_PRS_B0:
> + case DPS310_TMP_B2:
> + case DPS310_TMP_B1:
> + case DPS310_TMP_B0:
> + case DPS310_PRS_CFG:
> + case DPS310_TMP_CFG:
> + case DPS310_MEAS_CFG:
> + case DPS310_CFG_REG:
> + case DPS310_COEF_BASE...DPS310_COEF_LAST:
> + case DPS310_COEF_SRC:
> + case 0x32: /* Undocumented register to indicate workaround not required */
> + return s->regs[reg];
> + default:
> + qemu_log_mask(LOG_UNIMP, "%s: register 0x%02x unimplemented\n",
> + __func__, reg);
> + return 0xFF;
> + }
> +}
> +
> +static void dps310_write(DPS310State *s, uint8_t reg, uint8_t data)
> +{
> + if (reg >= sizeof(s->regs)) {
> + qemu_log_mask(LOG_GUEST_ERROR, "%s: register %d out of bounds\n",
> + __func__, s->pointer);
> + return;
> + }
> +
> + switch (reg) {
> + case DPS310_RESET:
> + if (data == DPS310_RESET_MAGIC) {
> + device_cold_reset(DEVICE(s));
> + }
> + break;
> + case DPS310_PRS_CFG:
> + case DPS310_TMP_CFG:
> + case DPS310_MEAS_CFG:
> + case DPS310_CFG_REG:
> + s->regs[reg] = data;
> + break;
> + default:
> + qemu_log_mask(LOG_UNIMP, "%s: register 0x%02x unimplemented\n",
> + __func__, reg);
> + return;
> + }
> +}
> +
> +static uint8_t dps310_rx(I2CSlave *i2c)
> +{
> + DPS310State *s = DPS310(i2c);
> +
> + if (s->len == 1) {
> + return dps310_read(s, s->pointer++);
> + } else {
> + return 0xFF;
> + }
> +}
> +
> +static int dps310_tx(I2CSlave *i2c, uint8_t data)
> +{
> + DPS310State *s = DPS310(i2c);
> +
> + if (s->len == 0) {
> + /*
> + * first byte is the register pointer for a read or write
> + * operation
> + */
> + s->pointer = data;
> + s->len++;
> + } else if (s->len == 1) {
> + dps310_write(s, s->pointer++, data);
> + }
> +
> + return 0;
> +}
> +
> +static int dps310_event(I2CSlave *i2c, enum i2c_event event)
> +{
> + DPS310State *s = DPS310(i2c);
> +
> + switch (event) {
> + case I2C_START_SEND:
> + s->pointer = 0xFF;
> + s->len = 0;
> + break;
> + case I2C_START_RECV:
> + if (s->len != 1) {
> + qemu_log_mask(LOG_GUEST_ERROR, "%s: invalid recv sequence\n",
> + __func__);
> + }
> + break;
> + default:
> + break;
> + }
> +
> + return 0;
> +}
> +
> +static const VMStateDescription vmstate_dps310 = {
> + .name = "DPS310",
> + .version_id = 0,
> + .minimum_version_id = 0,
> + .fields = (VMStateField[]) {
> + VMSTATE_UINT8(len, DPS310State),
> + VMSTATE_UINT8_ARRAY(regs, DPS310State, NUM_REGISTERS),
> + VMSTATE_UINT8(pointer, DPS310State),
> + VMSTATE_I2C_SLAVE(i2c, DPS310State),
> + VMSTATE_END_OF_LIST()
> + }
> +};
> +
> +static void dps310_class_init(ObjectClass *klass, void *data)
> +{
> + DeviceClass *dc = DEVICE_CLASS(klass);
> + I2CSlaveClass *k = I2C_SLAVE_CLASS(klass);
> +
> + k->event = dps310_event;
> + k->recv = dps310_rx;
> + k->send = dps310_tx;
> + dc->reset = dps310_reset;
> + dc->vmsd = &vmstate_dps310;
> +}
> +
> +static const TypeInfo dps310_info = {
> + .name = TYPE_DPS310,
> + .parent = TYPE_I2C_SLAVE,
> + .instance_size = sizeof(DPS310State),
> + .class_init = dps310_class_init,
> +};
> +
> +static void dps310_register_types(void)
> +{
> + type_register_static(&dps310_info);
> +}
> +
> +type_init(dps310_register_types)
> diff --git a/hw/arm/Kconfig b/hw/arm/Kconfig
> index 4ba0aca0676b..2c4e2df470d2 100644
> --- a/hw/arm/Kconfig
> +++ b/hw/arm/Kconfig
> @@ -429,6 +429,7 @@ config ASPEED_SOC
> select DS1338
> select FTGMAC100
> select I2C
> + select DPS310
> select PCA9552
> select SERIAL
> select SMBUS_EEPROM
> diff --git a/hw/misc/Kconfig b/hw/misc/Kconfig
> index 507058d8bffb..1c913dc3b837 100644
> --- a/hw/misc/Kconfig
> +++ b/hw/misc/Kconfig
> @@ -34,6 +34,10 @@ config EDU
> default y if TEST_DEVICES
> depends on PCI && MSI_NONBROKEN
>
> +config DPS310
> + bool
> + depends on I2C
> +
> config PCA9552
> bool
> depends on I2C
> diff --git a/hw/misc/meson.build b/hw/misc/meson.build
> index a53b849a5a0b..93b90ecd39e4 100644
> --- a/hw/misc/meson.build
> +++ b/hw/misc/meson.build
> @@ -1,4 +1,5 @@
> softmmu_ss.add(when: 'CONFIG_APPLESMC', if_true: files('applesmc.c'))
> +softmmu_ss.add(when: 'CONFIG_DPS310', if_true: files('dps310.c'))
> softmmu_ss.add(when: 'CONFIG_EDU', if_true: files('edu.c'))
> softmmu_ss.add(when: 'CONFIG_FW_CFG_DMA', if_true: files('vmcoreinfo.c'))
> softmmu_ss.add(when: 'CONFIG_ISA_DEBUG', if_true: files('debugexit.c'))
> --
> 2.31.1
>
>
^ permalink raw reply [flat|nested] 19+ messages in thread
* Re: [PATCH 09/10] hw/misc: Add Infineon DPS310 sensor model
2021-08-10 23:37 ` Corey Minyard
@ 2021-08-11 1:25 ` Joel Stanley
2021-08-12 15:15 ` Cédric Le Goater
0 siblings, 1 reply; 19+ messages in thread
From: Joel Stanley @ 2021-08-11 1:25 UTC (permalink / raw)
To: Corey Minyard
Cc: Andrew Jeffery, Peter Maydell, qemu-arm, Cédric Le Goater,
QEMU Developers
On Tue, 10 Aug 2021 at 23:37, Corey Minyard <minyard@acm.org> wrote:
>
> On Mon, Aug 09, 2021 at 03:15:55PM +0200, Cédric Le Goater wrote:
> > From: Joel Stanley <joel@jms.id.au>
> >
> > This contains some hardcoded register values that were obtained from the
> > hardware after reading the temperature.
> >
> > It does enough to test the Linux kernel driver. The FIFO mode, IRQs and
> > operation modes other than the default as used by Linux are not modelled.
> >
> > Signed-off-by: Joel Stanley <joel@jms.id.au>
> > [ clg: Fix sequential reading ]
> > Message-Id: <20210616073358.750472-2-joel@jms.id.au>
> > Signed-off-by: Cédric Le Goater <clg@kaod.org>
> > Message-Id: <20210629142336.750058-4-clg@kaod.org>
> > Signed-off-by: Cédric Le Goater <clg@kaod.org>
> > ---
> > hw/misc/dps310.c | 227 ++++++++++++++++++++++++++++++++++++++++++++
>
> Can this go into hw/sensor?
For sure. I wrote it four years ago, when obviously hw/sensor didn't exist.
>
> -corey
>
> > hw/arm/Kconfig | 1 +
> > hw/misc/Kconfig | 4 +
> > hw/misc/meson.build | 1 +
> > 4 files changed, 233 insertions(+)
> > create mode 100644 hw/misc/dps310.c
> >
> > diff --git a/hw/misc/dps310.c b/hw/misc/dps310.c
> > new file mode 100644
> > index 000000000000..893521ab8516
> > --- /dev/null
> > +++ b/hw/misc/dps310.c
> > @@ -0,0 +1,227 @@
> > +// SPDX-License-Identifier: GPL-2.0-or-later
> > +/*
> > + * Copyright 2017-2021 Joel Stanley <joel@jms.id.au>, IBM Corporation
> > + *
> > + * Infineon DPS310 temperature and humidity sensor
> > + *
> > + * https://www.infineon.com/cms/en/product/sensor/pressure-sensors/pressure-sensors-for-iot/dps310/
> > + */
> > +
> > +#include "qemu/osdep.h"
> > +#include "qemu/log.h"
> > +#include "hw/hw.h"
> > +#include "hw/i2c/i2c.h"
> > +#include "qapi/error.h"
> > +#include "qapi/visitor.h"
> > +#include "migration/vmstate.h"
> > +
> > +#define NUM_REGISTERS 0x33
> > +
> > +typedef struct DPS310State {
> > + /*< private >*/
> > + I2CSlave i2c;
> > +
> > + /*< public >*/
> > + uint8_t regs[NUM_REGISTERS];
> > +
> > + uint8_t len;
> > + uint8_t pointer;
> > +
> > +} DPS310State;
> > +
> > +#define TYPE_DPS310 "dps310"
> > +#define DPS310(obj) OBJECT_CHECK(DPS310State, (obj), TYPE_DPS310)
> > +
> > +#define DPS310_PRS_B2 0x00
> > +#define DPS310_PRS_B1 0x01
> > +#define DPS310_PRS_B0 0x02
> > +#define DPS310_TMP_B2 0x03
> > +#define DPS310_TMP_B1 0x04
> > +#define DPS310_TMP_B0 0x05
> > +#define DPS310_PRS_CFG 0x06
> > +#define DPS310_TMP_CFG 0x07
> > +#define DPS310_TMP_RATE_BITS (0x70)
> > +#define DPS310_MEAS_CFG 0x08
> > +#define DPS310_MEAS_CTRL_BITS (0x07)
> > +#define DPS310_PRESSURE_EN BIT(0)
> > +#define DPS310_TEMP_EN BIT(1)
> > +#define DPS310_BACKGROUND BIT(2)
> > +#define DPS310_PRS_RDY BIT(4)
> > +#define DPS310_TMP_RDY BIT(5)
> > +#define DPS310_SENSOR_RDY BIT(6)
> > +#define DPS310_COEF_RDY BIT(7)
> > +#define DPS310_CFG_REG 0x09
> > +#define DPS310_RESET 0x0c
> > +#define DPS310_RESET_MAGIC (BIT(0) | BIT(3))
> > +#define DPS310_COEF_BASE 0x10
> > +#define DPS310_COEF_LAST 0x21
> > +#define DPS310_COEF_SRC 0x28
> > +
> > +static void dps310_reset(DeviceState *dev)
> > +{
> > + DPS310State *s = DPS310(dev);
> > +
> > + static const uint8_t regs_reset_state[] = {
> > + 0xfe, 0x2f, 0xee, 0x02, 0x69, 0xa6, 0x00, 0x80, 0xc7, 0x00, 0x00, 0x00,
> > + 0x00, 0x10, 0x00, 0x00, 0x0e, 0x1e, 0xdd, 0x13, 0xca, 0x5f, 0x21, 0x52,
> > + 0xf9, 0xc6, 0x04, 0xd1, 0xdb, 0x47, 0x00, 0x5b, 0xfb, 0x3a, 0x00, 0x00,
> > + 0x20, 0x49, 0x4e, 0xa5, 0x90, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
> > + 0x60, 0x15, 0x02
> > + };
> > +
> > + QEMU_BUILD_BUG_ON(sizeof(regs_reset_state) != sizeof(s->regs));
> > +
> > + memcpy(s->regs, regs_reset_state, sizeof(s->regs));
> > + s->pointer = 0;
> > +
> > + /* TODO: assert these after some timeout ? */
> > + s->regs[DPS310_MEAS_CFG] = DPS310_COEF_RDY | DPS310_SENSOR_RDY
> > + | DPS310_TMP_RDY | DPS310_PRS_RDY;
> > +}
> > +
> > +static uint8_t dps310_read(DPS310State *s, uint8_t reg)
> > +{
> > + if (reg >= sizeof(s->regs)) {
> > + qemu_log_mask(LOG_GUEST_ERROR, "%s: register 0x%02x out of bounds\n",
> > + __func__, s->pointer);
> > + return 0xFF;
> > + }
> > +
> > + switch (reg) {
> > + case DPS310_PRS_B2:
> > + case DPS310_PRS_B1:
> > + case DPS310_PRS_B0:
> > + case DPS310_TMP_B2:
> > + case DPS310_TMP_B1:
> > + case DPS310_TMP_B0:
> > + case DPS310_PRS_CFG:
> > + case DPS310_TMP_CFG:
> > + case DPS310_MEAS_CFG:
> > + case DPS310_CFG_REG:
> > + case DPS310_COEF_BASE...DPS310_COEF_LAST:
> > + case DPS310_COEF_SRC:
> > + case 0x32: /* Undocumented register to indicate workaround not required */
> > + return s->regs[reg];
> > + default:
> > + qemu_log_mask(LOG_UNIMP, "%s: register 0x%02x unimplemented\n",
> > + __func__, reg);
> > + return 0xFF;
> > + }
> > +}
> > +
> > +static void dps310_write(DPS310State *s, uint8_t reg, uint8_t data)
> > +{
> > + if (reg >= sizeof(s->regs)) {
> > + qemu_log_mask(LOG_GUEST_ERROR, "%s: register %d out of bounds\n",
> > + __func__, s->pointer);
> > + return;
> > + }
> > +
> > + switch (reg) {
> > + case DPS310_RESET:
> > + if (data == DPS310_RESET_MAGIC) {
> > + device_cold_reset(DEVICE(s));
> > + }
> > + break;
> > + case DPS310_PRS_CFG:
> > + case DPS310_TMP_CFG:
> > + case DPS310_MEAS_CFG:
> > + case DPS310_CFG_REG:
> > + s->regs[reg] = data;
> > + break;
> > + default:
> > + qemu_log_mask(LOG_UNIMP, "%s: register 0x%02x unimplemented\n",
> > + __func__, reg);
> > + return;
> > + }
> > +}
> > +
> > +static uint8_t dps310_rx(I2CSlave *i2c)
> > +{
> > + DPS310State *s = DPS310(i2c);
> > +
> > + if (s->len == 1) {
> > + return dps310_read(s, s->pointer++);
> > + } else {
> > + return 0xFF;
> > + }
> > +}
> > +
> > +static int dps310_tx(I2CSlave *i2c, uint8_t data)
> > +{
> > + DPS310State *s = DPS310(i2c);
> > +
> > + if (s->len == 0) {
> > + /*
> > + * first byte is the register pointer for a read or write
> > + * operation
> > + */
> > + s->pointer = data;
> > + s->len++;
> > + } else if (s->len == 1) {
> > + dps310_write(s, s->pointer++, data);
> > + }
> > +
> > + return 0;
> > +}
> > +
> > +static int dps310_event(I2CSlave *i2c, enum i2c_event event)
> > +{
> > + DPS310State *s = DPS310(i2c);
> > +
> > + switch (event) {
> > + case I2C_START_SEND:
> > + s->pointer = 0xFF;
> > + s->len = 0;
> > + break;
> > + case I2C_START_RECV:
> > + if (s->len != 1) {
> > + qemu_log_mask(LOG_GUEST_ERROR, "%s: invalid recv sequence\n",
> > + __func__);
> > + }
> > + break;
> > + default:
> > + break;
> > + }
> > +
> > + return 0;
> > +}
> > +
> > +static const VMStateDescription vmstate_dps310 = {
> > + .name = "DPS310",
> > + .version_id = 0,
> > + .minimum_version_id = 0,
> > + .fields = (VMStateField[]) {
> > + VMSTATE_UINT8(len, DPS310State),
> > + VMSTATE_UINT8_ARRAY(regs, DPS310State, NUM_REGISTERS),
> > + VMSTATE_UINT8(pointer, DPS310State),
> > + VMSTATE_I2C_SLAVE(i2c, DPS310State),
> > + VMSTATE_END_OF_LIST()
> > + }
> > +};
> > +
> > +static void dps310_class_init(ObjectClass *klass, void *data)
> > +{
> > + DeviceClass *dc = DEVICE_CLASS(klass);
> > + I2CSlaveClass *k = I2C_SLAVE_CLASS(klass);
> > +
> > + k->event = dps310_event;
> > + k->recv = dps310_rx;
> > + k->send = dps310_tx;
> > + dc->reset = dps310_reset;
> > + dc->vmsd = &vmstate_dps310;
> > +}
> > +
> > +static const TypeInfo dps310_info = {
> > + .name = TYPE_DPS310,
> > + .parent = TYPE_I2C_SLAVE,
> > + .instance_size = sizeof(DPS310State),
> > + .class_init = dps310_class_init,
> > +};
> > +
> > +static void dps310_register_types(void)
> > +{
> > + type_register_static(&dps310_info);
> > +}
> > +
> > +type_init(dps310_register_types)
> > diff --git a/hw/arm/Kconfig b/hw/arm/Kconfig
> > index 4ba0aca0676b..2c4e2df470d2 100644
> > --- a/hw/arm/Kconfig
> > +++ b/hw/arm/Kconfig
> > @@ -429,6 +429,7 @@ config ASPEED_SOC
> > select DS1338
> > select FTGMAC100
> > select I2C
> > + select DPS310
> > select PCA9552
> > select SERIAL
> > select SMBUS_EEPROM
> > diff --git a/hw/misc/Kconfig b/hw/misc/Kconfig
> > index 507058d8bffb..1c913dc3b837 100644
> > --- a/hw/misc/Kconfig
> > +++ b/hw/misc/Kconfig
> > @@ -34,6 +34,10 @@ config EDU
> > default y if TEST_DEVICES
> > depends on PCI && MSI_NONBROKEN
> >
> > +config DPS310
> > + bool
> > + depends on I2C
> > +
> > config PCA9552
> > bool
> > depends on I2C
> > diff --git a/hw/misc/meson.build b/hw/misc/meson.build
> > index a53b849a5a0b..93b90ecd39e4 100644
> > --- a/hw/misc/meson.build
> > +++ b/hw/misc/meson.build
> > @@ -1,4 +1,5 @@
> > softmmu_ss.add(when: 'CONFIG_APPLESMC', if_true: files('applesmc.c'))
> > +softmmu_ss.add(when: 'CONFIG_DPS310', if_true: files('dps310.c'))
> > softmmu_ss.add(when: 'CONFIG_EDU', if_true: files('edu.c'))
> > softmmu_ss.add(when: 'CONFIG_FW_CFG_DMA', if_true: files('vmcoreinfo.c'))
> > softmmu_ss.add(when: 'CONFIG_ISA_DEBUG', if_true: files('debugexit.c'))
> > --
> > 2.31.1
> >
> >
^ permalink raw reply [flat|nested] 19+ messages in thread
* Re: [PATCH 08/10] aspeed: Emulate the AST2600A3
2021-08-09 15:55 ` Philippe Mathieu-Daudé
@ 2021-08-11 8:09 ` Cédric Le Goater
0 siblings, 0 replies; 19+ messages in thread
From: Cédric Le Goater @ 2021-08-11 8:09 UTC (permalink / raw)
To: Philippe Mathieu-Daudé, Peter Maydell
Cc: Andrew Jeffery, qemu-arm, Joel Stanley, qemu-devel
On 8/9/21 5:55 PM, Philippe Mathieu-Daudé wrote:
> On 8/9/21 3:15 PM, Cédric Le Goater wrote:
>> From: Joel Stanley <joel@jms.id.au>
>>
>> This is the latest revision of the ASPEED 2600 SoC. As there is no
>> need to model multiple revisions of the same SoC for the moment,
>> update the SCU AST2600 to model the A3 revision instead of the A1 and
>> adapt the AST2600 SoC and machines.
>>
>> Reset values are taken from v8 of the datasheet.
>>
>> Signed-off-by: Joel Stanley <joel@jms.id.au>
>> [ clg: - Introduced an Aspeed "ast2600-a3" SoC class
>> - Commit log update ]
>> Message-Id: <20210407171637.777743-21-clg@kaod.org>
>> Signed-off-by: Cédric Le Goater <clg@kaod.org>
>> Message-Id: <20210629142336.750058-3-clg@kaod.org>
>> Signed-off-by: Cédric Le Goater <clg@kaod.org>
>> ---
>> include/hw/misc/aspeed_scu.h | 2 ++
>> hw/arm/aspeed.c | 6 +++---
>> hw/arm/aspeed_ast2600.c | 6 +++---
>> hw/misc/aspeed_scu.c | 36 +++++++++++++++++++++++++++++-------
>> 4 files changed, 37 insertions(+), 13 deletions(-)
>
>> diff --git a/hw/misc/aspeed_scu.c b/hw/misc/aspeed_scu.c
>> index 40a38ebd8549..05edebedeb46 100644
>> --- a/hw/misc/aspeed_scu.c
>> +++ b/hw/misc/aspeed_scu.c
>> @@ -101,14 +101,24 @@
>> #define AST2600_CLK_STOP_CTRL_CLR TO_REG(0x84)
>> #define AST2600_CLK_STOP_CTRL2 TO_REG(0x90)
>> #define AST2600_CLK_STOP_CTRL2_CLR TO_REG(0x94)
>> +#define AST2600_DEBUG_CTRL TO_REG(0xC8)
>> +#define AST2600_DEBUG_CTRL2 TO_REG(0xD8)
>> #define AST2600_SDRAM_HANDSHAKE TO_REG(0x100)
>> #define AST2600_HPLL_PARAM TO_REG(0x200)
>> #define AST2600_HPLL_EXT TO_REG(0x204)
>> +#define AST2600_APLL_PARAM TO_REG(0x210)
>> +#define AST2600_APLL_EXT TO_REG(0x214)
>> +#define AST2600_MPLL_PARAM TO_REG(0x220)
>> #define AST2600_MPLL_EXT TO_REG(0x224)
>> +#define AST2600_EPLL_PARAM TO_REG(0x240)
>> #define AST2600_EPLL_EXT TO_REG(0x244)
>> +#define AST2600_DPLL_PARAM TO_REG(0x260)
>> +#define AST2600_DPLL_EXT TO_REG(0x264)
>> #define AST2600_CLK_SEL TO_REG(0x300)
>> #define AST2600_CLK_SEL2 TO_REG(0x304)
>> -#define AST2600_CLK_SEL3 TO_REG(0x310)
>> +#define AST2600_CLK_SEL3 TO_REG(0x308)
>
> Is it a bugfix? Otherwise this is annoying.
This is a bug in the model. These registers have the same layout
on the A1.
Thanks,
C.
>
> Maybe:
>
> #define AST2600A1_CLK_SEL3 TO_REG(0x310)
> #define AST2600A3_CLK_SEL3 TO_REG(0x308)
>
> and...
>
>> +#define AST2600_CLK_SEL4 TO_REG(0x310)
>> +#define AST2600_CLK_SEL5 TO_REG(0x314)
>> #define AST2600_HW_STRAP1 TO_REG(0x500)
>> #define AST2600_HW_STRAP1_CLR TO_REG(0x504)
>> #define AST2600_HW_STRAP1_PROT TO_REG(0x508)
>> @@ -433,6 +443,8 @@ static uint32_t aspeed_silicon_revs[] = {
>> AST2500_A1_SILICON_REV,
>> AST2600_A0_SILICON_REV,
>> AST2600_A1_SILICON_REV,
>> + AST2600_A2_SILICON_REV,
>> + AST2600_A3_SILICON_REV,
>> };
>>
>> bool is_supported_silicon_rev(uint32_t silicon_rev)
>> @@ -651,16 +663,26 @@ static const MemoryRegionOps aspeed_ast2600_scu_ops = {
>> .valid.unaligned = false,
>> };
>>
>> -static const uint32_t ast2600_a1_resets[ASPEED_AST2600_SCU_NR_REGS] = {
>> +static const uint32_t ast2600_a3_resets[ASPEED_AST2600_SCU_NR_REGS] = {
>> [AST2600_SYS_RST_CTRL] = 0xF7C3FED8,
>> - [AST2600_SYS_RST_CTRL2] = 0xFFFFFFFC,
>> + [AST2600_SYS_RST_CTRL2] = 0x0DFFFFFC,
>> [AST2600_CLK_STOP_CTRL] = 0xFFFF7F8A,
>> [AST2600_CLK_STOP_CTRL2] = 0xFFF0FFF0,
>> + [AST2600_DEBUG_CTRL] = 0x00000FFF,
>> + [AST2600_DEBUG_CTRL2] = 0x000000FF,
>> [AST2600_SDRAM_HANDSHAKE] = 0x00000000,
>> - [AST2600_HPLL_PARAM] = 0x1000405F,
>> + [AST2600_HPLL_PARAM] = 0x1000408F,
>> + [AST2600_APLL_PARAM] = 0x1000405F,
>> + [AST2600_MPLL_PARAM] = 0x1008405F,
>> + [AST2600_EPLL_PARAM] = 0x1004077F,
>> + [AST2600_DPLL_PARAM] = 0x1078405F,
>> + [AST2600_CLK_SEL] = 0xF3940000,
>> + [AST2600_CLK_SEL2] = 0x00700000,
>> + [AST2600_CLK_SEL3] = 0x00000000,
>
> ... use AST2600A3_CLK_SEL3 here?
>
> So someone wanting the emulate the A1 doesn't get
> the nasty bug of having CLK_SEL3 misplaced.
>
>> + [AST2600_CLK_SEL4] = 0xF3F40000,
>> + [AST2600_CLK_SEL5] = 0x30000000,
>> [AST2600_CHIP_ID0] = 0x1234ABCD,
>> [AST2600_CHIP_ID1] = 0x88884444,
>> -
>> };
^ permalink raw reply [flat|nested] 19+ messages in thread
* Re: [PATCH 09/10] hw/misc: Add Infineon DPS310 sensor model
2021-08-11 1:25 ` Joel Stanley
@ 2021-08-12 15:15 ` Cédric Le Goater
0 siblings, 0 replies; 19+ messages in thread
From: Cédric Le Goater @ 2021-08-12 15:15 UTC (permalink / raw)
To: Joel Stanley, Corey Minyard
Cc: Andrew Jeffery, Peter Maydell, qemu-arm, QEMU Developers
On 8/11/21 3:25 AM, Joel Stanley wrote:
> On Tue, 10 Aug 2021 at 23:37, Corey Minyard <minyard@acm.org> wrote:
>>
>> On Mon, Aug 09, 2021 at 03:15:55PM +0200, Cédric Le Goater wrote:
>>> From: Joel Stanley <joel@jms.id.au>
>>>
>>> This contains some hardcoded register values that were obtained from the
>>> hardware after reading the temperature.
>>>
>>> It does enough to test the Linux kernel driver. The FIFO mode, IRQs and
>>> operation modes other than the default as used by Linux are not modelled.
>>>
>>> Signed-off-by: Joel Stanley <joel@jms.id.au>
>>> [ clg: Fix sequential reading ]
>>> Message-Id: <20210616073358.750472-2-joel@jms.id.au>
>>> Signed-off-by: Cédric Le Goater <clg@kaod.org>
>>> Message-Id: <20210629142336.750058-4-clg@kaod.org>
>>> Signed-off-by: Cédric Le Goater <clg@kaod.org>
>>> ---
>>> hw/misc/dps310.c | 227 ++++++++++++++++++++++++++++++++++++++++++++
>>
>> Can this go into hw/sensor?
>
> For sure. I wrote it four years ago, when obviously hw/sensor didn't exist.
I moved it under hw/sensor.
C.
^ permalink raw reply [flat|nested] 19+ messages in thread
end of thread, other threads:[~2021-08-12 15:17 UTC | newest]
Thread overview: 19+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2021-08-09 13:15 [PATCH 00/10] Aspeed: 6.2 queue Cédric Le Goater
2021-08-09 13:15 ` [PATCH 01/10] hw: arm: aspeed: Enable eth0 interface for aspeed-ast2600-evb Cédric Le Goater
2021-08-09 13:15 ` [PATCH 02/10] watchdog: aspeed: Sanitize control register values Cédric Le Goater
2021-08-09 13:15 ` [PATCH 03/10] watchdog: aspeed: Fix sequential control writes Cédric Le Goater
2021-08-09 15:48 ` Philippe Mathieu-Daudé
2021-08-09 13:15 ` [PATCH 04/10] hw: aspeed_gpio: Simplify 1.8V defines Cédric Le Goater
2021-08-09 13:15 ` [PATCH 05/10] hw: aspeed_gpio: Clarify GPIO controller name Cédric Le Goater
2021-08-09 13:15 ` [PATCH 06/10] misc/pca9552: Fix LED status register indexing in pca955x_get_led() Cédric Le Goater
2021-08-09 13:15 ` [PATCH 07/10] arm/aspeed: rainier: Add i2c eeproms and muxes Cédric Le Goater
2021-08-09 13:15 ` [PATCH 08/10] aspeed: Emulate the AST2600A3 Cédric Le Goater
2021-08-09 15:55 ` Philippe Mathieu-Daudé
2021-08-11 8:09 ` Cédric Le Goater
2021-08-09 13:15 ` [PATCH 09/10] hw/misc: Add Infineon DPS310 sensor model Cédric Le Goater
2021-08-09 15:59 ` Philippe Mathieu-Daudé
2021-08-10 14:37 ` Cédric Le Goater
2021-08-10 23:37 ` Corey Minyard
2021-08-11 1:25 ` Joel Stanley
2021-08-12 15:15 ` Cédric Le Goater
2021-08-09 13:15 ` [PATCH 10/10] arm/aspeed: Add DPS310 to Witherspoon and Rainier Cédric Le Goater
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