From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-2.8 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI,PDS_BAD_THREAD_QP_64, SPF_HELO_NONE,SPF_PASS autolearn=no autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id DFBBCC433ED for ; Tue, 11 May 2021 20:12:18 +0000 (UTC) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 3F7D461139 for ; Tue, 11 May 2021 20:12:18 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 3F7D461139 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=huawei.com Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Received: from localhost ([::1]:42136 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1lgYjp-0000vx-8H for qemu-devel@archiver.kernel.org; Tue, 11 May 2021 16:12:17 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:35236) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lgWXi-0001UI-Tb; Tue, 11 May 2021 13:51:38 -0400 Received: from szxga01-in.huawei.com ([45.249.212.187]:2483) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lgWXY-00021U-SG; Tue, 11 May 2021 13:51:38 -0400 Received: from dggeml756-chm.china.huawei.com (unknown [172.30.72.53]) by szxga01-in.huawei.com (SkyGuard) with ESMTP id 4Ffljg1wjVzWhKk; Wed, 12 May 2021 01:47:03 +0800 (CST) Received: from dggpemm100008.china.huawei.com (7.185.36.125) by dggeml756-chm.china.huawei.com (10.1.199.158) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2176.2; Wed, 12 May 2021 01:51:17 +0800 Received: from dggpemm500011.china.huawei.com (7.185.36.110) by dggpemm100008.china.huawei.com (7.185.36.125) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2176.2; Wed, 12 May 2021 01:51:17 +0800 Received: from dggpemm500011.china.huawei.com ([7.185.36.110]) by dggpemm500011.china.huawei.com ([7.185.36.110]) with mapi id 15.01.2176.012; Wed, 12 May 2021 01:51:17 +0800 From: Andrey Shinkevich To: "qemu-devel@nongnu.org" Subject: GICv3 for MTTCG Thread-Topic: GICv3 for MTTCG Thread-Index: AQHXRo49QQoDTg/5kkqOfm/tGkugzg== Date: Tue, 11 May 2021 17:51:17 +0000 Message-ID: <1f157423cc544731beb743287a4be5cb@huawei.com> Accept-Language: en-US, zh-CN Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-originating-ip: [10.227.155.55] Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-CFilter-Loop: Reflected Received-SPF: pass client-ip=45.249.212.187; envelope-from=andrey.shinkevich@huawei.com; helo=szxga01-in.huawei.com X-Spam_score_int: -41 X-Spam_score: -4.2 X-Spam_bar: ---- X-Spam_report: (-4.2 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-Mailman-Approved-At: Tue, 11 May 2021 16:11:23 -0400 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: "peter.maydell@linaro.org" , "drjones@redhat.com" , "richard.henderson@linaro.org" , "qemu-arm@nongnu.org" , "Chengen \(William, FixNet\)" , "alex.bennee@linaro.org" Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" Dear colleagues,=0A= =0A= I am looking for ways to accelerate the MTTCG for ARM guest on x86-64 host.= =0A= The maximum number of CPUs for MTTCG that uses GICv2 is limited by 8:=0A= =0A= include/hw/intc/arm_gic_common.h:#define GIC_NCPU 8=0A= =0A= The version 3 of the Generic Interrupt Controller (GICv3) is not=0A= supported in QEMU for some reason unknown to me. It would allow to=0A= increase the limit of CPUs and accelerate the MTTCG performance on a=0A= multiple core hypervisor.=0A= I have got an idea to implement the Interrupt Translation Service (ITS)=0A= for using by MTTCG for ARM architecture.=0A= =0A= Do you find that idea useful and feasible?=0A= If yes, how much time do you estimate for such a project to complete by=0A= one developer?=0A= If no, what are reasons for not implementing GICv3 for MTTCG in QEMU?=0A= =0A= Best regards,=0A= Andrey Shinkevich=0A=