From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-8.2 required=3.0 tests=HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH,MAILING_LIST_MULTI,SIGNED_OFF_BY,SPF_HELO_NONE,SPF_PASS, URIBL_BLOCKED,USER_AGENT_SANE_1 autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 18A4FC7619F for ; Mon, 17 Feb 2020 09:12:05 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id E1F8F2067D for ; Mon, 17 Feb 2020 09:12:04 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728786AbgBQJMD (ORCPT ); Mon, 17 Feb 2020 04:12:03 -0500 Received: from szxga06-in.huawei.com ([45.249.212.32]:43474 "EHLO huawei.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1728681AbgBQJMD (ORCPT ); Mon, 17 Feb 2020 04:12:03 -0500 Received: from DGGEMS411-HUB.china.huawei.com (unknown [172.30.72.59]) by Forcepoint Email with ESMTP id C17C2B5DC1BA1A12947B; Mon, 17 Feb 2020 17:11:55 +0800 (CST) Received: from [127.0.0.1] (10.173.222.27) by DGGEMS411-HUB.china.huawei.com (10.3.19.211) with Microsoft SMTP Server id 14.3.439.0; Mon, 17 Feb 2020 17:11:48 +0800 Subject: Re: [PATCH v4 01/20] irqchip/gic-v4.1: Skip absent CPUs while iterating over redistributors To: Marc Zyngier , , , , CC: Lorenzo Pieralisi , Jason Cooper , Robert Richter , "Thomas Gleixner" , Eric Auger , "James Morse" , Julien Thierry , Suzuki K Poulose References: <20200214145736.18550-1-maz@kernel.org> <20200214145736.18550-2-maz@kernel.org> From: Zenghui Yu Message-ID: <1f86bcdd-01ca-4925-3163-d47e17d006ab@huawei.com> Date: Mon, 17 Feb 2020 17:11:47 +0800 User-Agent: Mozilla/5.0 (Windows NT 10.0; WOW64; rv:68.0) Gecko/20100101 Thunderbird/68.2.0 MIME-Version: 1.0 In-Reply-To: <20200214145736.18550-2-maz@kernel.org> Content-Type: text/plain; charset="utf-8"; format=flowed Content-Language: en-US Content-Transfer-Encoding: 7bit X-Originating-IP: [10.173.222.27] X-CFilter-Loop: Reflected Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Hi Marc, On 2020/2/14 22:57, Marc Zyngier wrote: > In a system that is only sparsly populated with CPUs, we can end-up with > redistributors structures that are not initialized. Let's make sure we > don't try and access those when iterating over them (in this case when > checking we have a L2 VPE table). > > Fixes: 4e6437f12d6e ("irqchip/gic-v4.1: Ensure L2 vPE table is allocated at RD level") > Signed-off-by: Marc Zyngier > --- > drivers/irqchip/irq-gic-v3-its.c | 4 ++++ > 1 file changed, 4 insertions(+) > > diff --git a/drivers/irqchip/irq-gic-v3-its.c b/drivers/irqchip/irq-gic-v3-its.c > index 83b1186ffcad..da883a691028 100644 > --- a/drivers/irqchip/irq-gic-v3-its.c > +++ b/drivers/irqchip/irq-gic-v3-its.c > @@ -2452,6 +2452,10 @@ static bool allocate_vpe_l2_table(int cpu, u32 id) > if (!gic_rdists->has_rvpeid) > return true; > > + /* Skip non-present CPUs */ > + if (!base) > + return true; > + Thanks for fixing this, Reviewed-by: Zenghui Yu > val = gicr_read_vpropbaser(base + SZ_128K + GICR_VPROPBASER); > > esz = FIELD_GET(GICR_VPROPBASER_4_1_ENTRY_SIZE, val) + 1; > From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-8.2 required=3.0 tests=HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH,MAILING_LIST_MULTI,SIGNED_OFF_BY,SPF_HELO_NONE,SPF_PASS, URIBL_BLOCKED,USER_AGENT_SANE_1 autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 536F6C7619D for ; Mon, 17 Feb 2020 09:12:06 +0000 (UTC) Received: from mm01.cs.columbia.edu (mm01.cs.columbia.edu [128.59.11.253]) by mail.kernel.org (Postfix) with ESMTP id D48E22067D for ; Mon, 17 Feb 2020 09:12:05 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org D48E22067D Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=huawei.com Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=kvmarm-bounces@lists.cs.columbia.edu Received: from localhost (localhost [127.0.0.1]) by mm01.cs.columbia.edu (Postfix) with ESMTP id 503284AF2B; Mon, 17 Feb 2020 04:12:05 -0500 (EST) X-Virus-Scanned: at lists.cs.columbia.edu Received: from mm01.cs.columbia.edu ([127.0.0.1]) by localhost (mm01.cs.columbia.edu [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id OIAlsvWFLO47; Mon, 17 Feb 2020 04:12:04 -0500 (EST) Received: from mm01.cs.columbia.edu (localhost [127.0.0.1]) by mm01.cs.columbia.edu (Postfix) with ESMTP id 4ED864AF36; Mon, 17 Feb 2020 04:12:04 -0500 (EST) Received: from localhost (localhost [127.0.0.1]) by mm01.cs.columbia.edu (Postfix) with ESMTP id 053674AF29 for ; Mon, 17 Feb 2020 04:12:03 -0500 (EST) X-Virus-Scanned: at lists.cs.columbia.edu Received: from mm01.cs.columbia.edu ([127.0.0.1]) by localhost (mm01.cs.columbia.edu [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id a+Y4mihEVRs1 for ; Mon, 17 Feb 2020 04:12:01 -0500 (EST) Received: from huawei.com (szxga06-in.huawei.com [45.249.212.32]) by mm01.cs.columbia.edu (Postfix) with ESMTPS id A91944A7FE for ; Mon, 17 Feb 2020 04:12:01 -0500 (EST) Received: from DGGEMS411-HUB.china.huawei.com (unknown [172.30.72.59]) by Forcepoint Email with ESMTP id C17C2B5DC1BA1A12947B; Mon, 17 Feb 2020 17:11:55 +0800 (CST) Received: from [127.0.0.1] (10.173.222.27) by DGGEMS411-HUB.china.huawei.com (10.3.19.211) with Microsoft SMTP Server id 14.3.439.0; Mon, 17 Feb 2020 17:11:48 +0800 Subject: Re: [PATCH v4 01/20] irqchip/gic-v4.1: Skip absent CPUs while iterating over redistributors To: Marc Zyngier , , , , References: <20200214145736.18550-1-maz@kernel.org> <20200214145736.18550-2-maz@kernel.org> From: Zenghui Yu Message-ID: <1f86bcdd-01ca-4925-3163-d47e17d006ab@huawei.com> Date: Mon, 17 Feb 2020 17:11:47 +0800 User-Agent: Mozilla/5.0 (Windows NT 10.0; WOW64; rv:68.0) Gecko/20100101 Thunderbird/68.2.0 MIME-Version: 1.0 In-Reply-To: <20200214145736.18550-2-maz@kernel.org> Content-Language: en-US X-Originating-IP: [10.173.222.27] X-CFilter-Loop: Reflected Cc: Lorenzo Pieralisi , Jason Cooper , Robert Richter , Thomas Gleixner X-BeenThere: kvmarm@lists.cs.columbia.edu X-Mailman-Version: 2.1.14 Precedence: list List-Id: Where KVM/ARM decisions are made List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Transfer-Encoding: 7bit Content-Type: text/plain; charset="us-ascii"; Format="flowed" Errors-To: kvmarm-bounces@lists.cs.columbia.edu Sender: kvmarm-bounces@lists.cs.columbia.edu Hi Marc, On 2020/2/14 22:57, Marc Zyngier wrote: > In a system that is only sparsly populated with CPUs, we can end-up with > redistributors structures that are not initialized. Let's make sure we > don't try and access those when iterating over them (in this case when > checking we have a L2 VPE table). > > Fixes: 4e6437f12d6e ("irqchip/gic-v4.1: Ensure L2 vPE table is allocated at RD level") > Signed-off-by: Marc Zyngier > --- > drivers/irqchip/irq-gic-v3-its.c | 4 ++++ > 1 file changed, 4 insertions(+) > > diff --git a/drivers/irqchip/irq-gic-v3-its.c b/drivers/irqchip/irq-gic-v3-its.c > index 83b1186ffcad..da883a691028 100644 > --- a/drivers/irqchip/irq-gic-v3-its.c > +++ b/drivers/irqchip/irq-gic-v3-its.c > @@ -2452,6 +2452,10 @@ static bool allocate_vpe_l2_table(int cpu, u32 id) > if (!gic_rdists->has_rvpeid) > return true; > > + /* Skip non-present CPUs */ > + if (!base) > + return true; > + Thanks for fixing this, Reviewed-by: Zenghui Yu > val = gicr_read_vpropbaser(base + SZ_128K + GICR_VPROPBASER); > > esz = FIELD_GET(GICR_VPROPBASER_4_1_ENTRY_SIZE, val) + 1; > _______________________________________________ kvmarm mailing list kvmarm@lists.cs.columbia.edu https://lists.cs.columbia.edu/mailman/listinfo/kvmarm From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-8.3 required=3.0 tests=DKIMWL_WL_HIGH,DKIM_SIGNED, DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_PATCH,MAILING_LIST_MULTI, SIGNED_OFF_BY,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_SANE_1 autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 8F959C7619D for ; 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Mon, 17 Feb 2020 17:11:48 +0800 Subject: Re: [PATCH v4 01/20] irqchip/gic-v4.1: Skip absent CPUs while iterating over redistributors To: Marc Zyngier , , , , References: <20200214145736.18550-1-maz@kernel.org> <20200214145736.18550-2-maz@kernel.org> From: Zenghui Yu Message-ID: <1f86bcdd-01ca-4925-3163-d47e17d006ab@huawei.com> Date: Mon, 17 Feb 2020 17:11:47 +0800 User-Agent: Mozilla/5.0 (Windows NT 10.0; WOW64; rv:68.0) Gecko/20100101 Thunderbird/68.2.0 MIME-Version: 1.0 In-Reply-To: <20200214145736.18550-2-maz@kernel.org> Content-Language: en-US X-Originating-IP: [10.173.222.27] X-CFilter-Loop: Reflected X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20200217_011201_582391_9E880BA8 X-CRM114-Status: GOOD ( 14.89 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Lorenzo Pieralisi , Jason Cooper , Suzuki K Poulose , Eric Auger , Robert Richter , James Morse , Thomas Gleixner , Julien Thierry Content-Transfer-Encoding: 7bit Content-Type: text/plain; charset="us-ascii"; Format="flowed" Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+infradead-linux-arm-kernel=archiver.kernel.org@lists.infradead.org Hi Marc, On 2020/2/14 22:57, Marc Zyngier wrote: > In a system that is only sparsly populated with CPUs, we can end-up with > redistributors structures that are not initialized. Let's make sure we > don't try and access those when iterating over them (in this case when > checking we have a L2 VPE table). > > Fixes: 4e6437f12d6e ("irqchip/gic-v4.1: Ensure L2 vPE table is allocated at RD level") > Signed-off-by: Marc Zyngier > --- > drivers/irqchip/irq-gic-v3-its.c | 4 ++++ > 1 file changed, 4 insertions(+) > > diff --git a/drivers/irqchip/irq-gic-v3-its.c b/drivers/irqchip/irq-gic-v3-its.c > index 83b1186ffcad..da883a691028 100644 > --- a/drivers/irqchip/irq-gic-v3-its.c > +++ b/drivers/irqchip/irq-gic-v3-its.c > @@ -2452,6 +2452,10 @@ static bool allocate_vpe_l2_table(int cpu, u32 id) > if (!gic_rdists->has_rvpeid) > return true; > > + /* Skip non-present CPUs */ > + if (!base) > + return true; > + Thanks for fixing this, Reviewed-by: Zenghui Yu > val = gicr_read_vpropbaser(base + SZ_128K + GICR_VPROPBASER); > > esz = FIELD_GET(GICR_VPROPBASER_4_1_ENTRY_SIZE, val) + 1; > _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel