Re: [Qemu-devel] [PATCH v2 6/7] target/mips: Add opcodes for nanoMIPS EVA instructions

["Philippe Mathieu-Daudé" <philmd@redhat.com>]

On 05/10/2018 17:19, Aleksandar Markovic wrote:
> From: Dimitrije Nikolic <dnikolic@wavecomp.com>
> 
> Add opcodes for nanoMIPS EVA instructions: CACHEE, LBE, LBUE, LHE,
> LHUE, LLE, LLWPE, LWE, PREFE, SBE, SCE, SCWPE, SHE, SWE.

B.44 of "nanoMIPS32 Instruction Set Technical Reference Manual"

> Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>

Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>

> ---
>  target/mips/translate.c | 16 ++++++++++++++++
>  1 file changed, 16 insertions(+)
> 
> diff --git a/target/mips/translate.c b/target/mips/translate.c
> index d64a1da..b0b2f40 100644
> --- a/target/mips/translate.c
> +++ b/target/mips/translate.c
> @@ -16499,6 +16499,22 @@ enum {
>      NM_P_SC      = 0x0b,
>  };
>  
> +/* P.LS.E0 instruction pool */
> +enum {
> +    NM_LBE      = 0x00,
> +    NM_SBE      = 0x01,
> +    NM_LBUE     = 0x02,
> +    NM_P_PREFE  = 0x03,
> +    NM_LHE      = 0x04,
> +    NM_SHE      = 0x05,
> +    NM_LHUE     = 0x06,
> +    NM_CACHEE   = 0x07,
> +    NM_LWE      = 0x08,
> +    NM_SWE      = 0x09,
> +    NM_P_LLE    = 0x0a,
> +    NM_P_SCE    = 0x0b,
> +};
> +
>  /* P.LS.WM instruction pool */
>  enum {
>      NM_LWM       = 0x00,
>