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[90.63.244.31]) by smtp.gmail.com with ESMTPSA id f197sm6043371wme.33.2020.07.09.10.16.30 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 09 Jul 2020 10:16:30 -0700 (PDT) References: <20200629203904.2989007-1-martin.blumenstingl@googlemail.com> User-agent: mu4e 1.3.3; emacs 26.3 From: Jerome Brunet To: Martin Blumenstingl , linux-amlogic@lists.infradead.org Cc: narmstrong@baylibre.com, linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: Re: [PATCH 0/2] clk: meson8b: add two missing gate clocks In-reply-to: <20200629203904.2989007-1-martin.blumenstingl@googlemail.com> Date: Thu, 09 Jul 2020 19:16:29 +0200 Message-ID: <1jk0zcip76.fsf@starbuckisacylon.baylibre.com> MIME-Version: 1.0 Content-Type: text/plain Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Mon 29 Jun 2020 at 22:39, Martin Blumenstingl wrote: > While trying to figure out how to set up the video clocks on the 32-bit > SoCs I found that the current clock tree is missing two gates. This adds > the missing gates based on evidence found in the public S805 datasheet, > the GXBB clock driver and 3.10 vendor kernel. > > I didn't add any Fixes tag because this clock tree is still read-only > and the HDMI PLL (the top-most clock in this tree) needs more work as > well. > > > Martin Blumenstingl (2): > clk: meson: meson8b: add the vclk_en gate clock > clk: meson: meson8b: add the vclk2_en gate clock > > drivers/clk/meson/meson8b.c | 60 ++++++++++++++++++++++++++++++------- > drivers/clk/meson/meson8b.h | 4 ++- > 2 files changed, 53 insertions(+), 11 deletions(-) Applied Thx. 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[90.63.244.31]) by smtp.gmail.com with ESMTPSA id f197sm6043371wme.33.2020.07.09.10.16.30 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 09 Jul 2020 10:16:30 -0700 (PDT) References: <20200629203904.2989007-1-martin.blumenstingl@googlemail.com> User-agent: mu4e 1.3.3; emacs 26.3 From: Jerome Brunet To: Martin Blumenstingl , linux-amlogic@lists.infradead.org Subject: Re: [PATCH 0/2] clk: meson8b: add two missing gate clocks In-reply-to: <20200629203904.2989007-1-martin.blumenstingl@googlemail.com> Date: Thu, 09 Jul 2020 19:16:29 +0200 Message-ID: <1jk0zcip76.fsf@starbuckisacylon.baylibre.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20200709_131634_317700_08BBE295 X-CRM114-Status: GOOD ( 10.88 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org, narmstrong@baylibre.com Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Mon 29 Jun 2020 at 22:39, Martin Blumenstingl wrote: > While trying to figure out how to set up the video clocks on the 32-bit > SoCs I found that the current clock tree is missing two gates. This adds > the missing gates based on evidence found in the public S805 datasheet, > the GXBB clock driver and 3.10 vendor kernel. > > I didn't add any Fixes tag because this clock tree is still read-only > and the HDMI PLL (the top-most clock in this tree) needs more work as > well. > > > Martin Blumenstingl (2): > clk: meson: meson8b: add the vclk_en gate clock > clk: meson: meson8b: add the vclk2_en gate clock > > drivers/clk/meson/meson8b.c | 60 ++++++++++++++++++++++++++++++------- > drivers/clk/meson/meson8b.h | 4 ++- > 2 files changed, 53 insertions(+), 11 deletions(-) Applied Thx. _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-0.8 required=3.0 tests=DKIMWL_WL_HIGH,DKIM_SIGNED, DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI,SPF_HELO_NONE, SPF_PASS,URIBL_BLOCKED autolearn=no autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id A22E7C433DF for ; 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[90.63.244.31]) by smtp.gmail.com with ESMTPSA id f197sm6043371wme.33.2020.07.09.10.16.30 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 09 Jul 2020 10:16:30 -0700 (PDT) References: <20200629203904.2989007-1-martin.blumenstingl@googlemail.com> User-agent: mu4e 1.3.3; emacs 26.3 From: Jerome Brunet To: Martin Blumenstingl , linux-amlogic@lists.infradead.org Subject: Re: [PATCH 0/2] clk: meson8b: add two missing gate clocks In-reply-to: <20200629203904.2989007-1-martin.blumenstingl@googlemail.com> Date: Thu, 09 Jul 2020 19:16:29 +0200 Message-ID: <1jk0zcip76.fsf@starbuckisacylon.baylibre.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20200709_131634_013763_22467635 X-CRM114-Status: UNSURE ( 9.40 ) X-CRM114-Notice: Please train this message. X-BeenThere: linux-amlogic@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org, narmstrong@baylibre.com Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-amlogic" Errors-To: linux-amlogic-bounces+linux-amlogic=archiver.kernel.org@lists.infradead.org On Mon 29 Jun 2020 at 22:39, Martin Blumenstingl wrote: > While trying to figure out how to set up the video clocks on the 32-bit > SoCs I found that the current clock tree is missing two gates. This adds > the missing gates based on evidence found in the public S805 datasheet, > the GXBB clock driver and 3.10 vendor kernel. > > I didn't add any Fixes tag because this clock tree is still read-only > and the HDMI PLL (the top-most clock in this tree) needs more work as > well. > > > Martin Blumenstingl (2): > clk: meson: meson8b: add the vclk_en gate clock > clk: meson: meson8b: add the vclk2_en gate clock > > drivers/clk/meson/meson8b.c | 60 ++++++++++++++++++++++++++++++------- > drivers/clk/meson/meson8b.h | 4 ++- > 2 files changed, 53 insertions(+), 11 deletions(-) Applied Thx. _______________________________________________ linux-amlogic mailing list linux-amlogic@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-amlogic