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Date: Mon, 2 Feb 2004 16:23:07 +0100
From: Ralf Baechle <ralf@linux-mips.org>
To: "Maciej W. Rozycki" <macro@ds2.pg.gda.pl>
Cc: linux-mips@linux-mips.org
Subject: Re: CVS Update@-mips.org: linux
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On Mon, Feb 02, 2004 at 04:13:28PM +0100, Maciej W. Rozycki wrote:

> > 	PMC-Sierra says that the workaround for errata #18 of the R4600 V1.7
> > 	and a similar erratum in V2.0 don't require disabling of interrupts,
> > 	so remove that code.
> 
>  How do we assure tails of interrupt handlers don't trigger the errata?

The problem can only be triggered if instructions surrounding the
cacheop use the dcache; exceptions such as interrupts are not relevant.

Which I'm really happy about.  Disabling interrupts is a problem in cases
were we can't avoid page faults.

  Ralf