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From: Arnd Bergmann <arnd@arndb.de>
To: cbe-oss-dev@ozlabs.org
Subject: Re: [Cbe-oss-dev] [PATCH] powerpc: Introduce address space "slices"
Date: Mon, 19 Feb 2007 17:49:03 +0100
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Cc: Olof Johansson <olof@lixom.net>,
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On Monday 19 February 2007 16:33, Olof Johansson wrote:
>=20
> > =A0- SPE local store mappings using 64K pages on a 4K base page size
> > kernel on Cell
>=20
> Why? What is the reason they can't use 4K pages?
>=20
Performance: On a system with 16 SPEs, you have 4MB of local store memory.
Assuming you have an application running on them that has basically random
access with DMA to all of them, that is 1024 4k pages, while a single SPE
has only 256 TLB entries. This means you get a high overhead from loading
the PTEs, and (worse) handling all the hash miss faults, and even then
you end up thrashing your TLB.
With 64k pages, you can easily fit all the mappings for local store into
the TLB of one SPE.

Note that for regular memory, we can avoid that problem by using
16MB hugepages, which is not possible for the local store.

	Arnd <><