From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mailman by lists.gnu.org with tmda-scanned (Exim 4.43) id 1Igge1-0005Cv-4Q for qemu-devel@nongnu.org; Sat, 13 Oct 2007 09:03:05 -0400 Received: from exim by lists.gnu.org with spam-scanned (Exim 4.43) id 1Iggdz-00059n-6s for qemu-devel@nongnu.org; Sat, 13 Oct 2007 09:03:04 -0400 Received: from [199.232.76.173] (helo=monty-python.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1Iggdy-00059c-UP for qemu-devel@nongnu.org; Sat, 13 Oct 2007 09:03:03 -0400 Received: from relay01.mx.bawue.net ([193.7.176.67]) by monty-python.gnu.org with esmtps (TLS-1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.60) (envelope-from ) id 1Iggdy-0003dk-BA for qemu-devel@nongnu.org; Sat, 13 Oct 2007 09:03:02 -0400 Date: Sat, 13 Oct 2007 14:02:53 +0100 From: Thiemo Seufer Subject: Re: [Qemu-devel] RFC: reverse-endian softmmu memory accessors Message-ID: <20071013130253.GN3379@networkno.de> References: <1192269372.9976.305.camel@rapid> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: Reply-To: qemu-devel@nongnu.org List-Id: qemu-devel.nongnu.org List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Blue Swirl Cc: qemu-devel@nongnu.org Blue Swirl wrote: > On 10/13/07, J. Mayer wrote: > > The problem: > > some CPU architectures, namely PowerPC and maybe others, offers > > facilities to access the memory or I/O in the reverse endianness, ie > > little-endian instead of big-endian for PowerPC, or provide instruction > > to make memory accesses in the "reverse-endian". This is implemented as > > a global flag on some CPU. This case is already handled by the PowerPC > > emulation but is is far from being optimal. Some other implementations > > allow the OS to store an "reverse-endian" flag in the TLB or the segment > > descriptors, thus providing per-page or per-segment endianness control. > > This is mostly used to ease driver migration from a PC platform to > > PowerPC without taking any care of the device endianness in the driver > > code (yes, this is bad...). > > Nice, this may be useful for Sparc64. It has a global CPU flag for > endianness, individual pages can be marked as reverse endian, and > finally there are instructions that access memory in reverse endian. > The end result is a XOR of all these reverses. Though I don't know if > any of these features are used at all. Likewise for the MIPS reverse endianness global flag. > Other memory access functions could be merged too. Is the 32 bit load > with sign extension to 64 bits used in other architectures? Yes for MIPS. Thiemo