Re: DTS file PCI / i8259 for Xilinx ML510

From: "Roderick Colenbrander" <thunderbird2k@gmx.net>
To: "Gerhard Pircher" <gerhard_pircher@gmx.net>, linuxppc-dev@ozlabs.org
Subject: Re: DTS file PCI / i8259 for Xilinx ML510
Date: Sun, 15 Mar 2009 12:00:17 +0100	[thread overview]
Message-ID: <20090315110017.202010@gmx.net> (raw)
In-Reply-To: <20090315104313.72510@gmx.net>

> > I got the i8259 south bridge working now after adding an io_base_virt
> > offset to all inb/outb lines in sysdev/i8259.c. Would it be worth all
> > the troubles to add ppc32 support to isa-bridge.c? The whole point of
> > the code is basically to remap the io memory to low addresses for these
> > 64-bit ppc systems (mainly freescale boards with a i8259 and pseries
> > systems with a i8259).
> pci_process_bridge_OF_ranges() should "ioremap" io_base_virt for you,
> if your board has only one PCI I/O space. It also sets isa_io_base to
> io_base_virt on PPC32, but expects that the ISA I/O space is mapped to
> PCI I/O address 0x0. Isn't that the case for your board?
> 

Ah then perhaps that is my problem. I'm using my own pci implementation for Xilinx their plbv46 soft core. The soft core might be compatible with a generic ibm plb-pci bridge (sysdev/ppc44x_pci.c). Basically I'm doing something like which is done in powermac/pci.c e.g. creating the pci_controller and filling it with cfg_addr / cfg_data pointers, io ranges, resource ranges and so on. The data is obtained from the dts file but from some xilinx generated fields and doesn't have the generic ranges fields and some others. I guess it is time to fix this part of the DTS file.

Some other issue I had which might be related to my DTS file bugs is some i/o port conflict. The M1553 south bridge is just a peripheral on the ML510 primary pci bus there are no PCI slots connected to it. There are four other pci slots of which two are directly connected to the fpga (they are on the same bus as the M1553) and two are connected using a pci-to-pci bridge because they use 5V instead of 3.3V. The bridge chip wanted 0x0-0xfff while some south bridge devices wanted low addresses (if I remember correctly the IDE controller wants 0x1f0-0x1f1 and some 0x3** ports). This generated some "Cannot allocate resource region .. will remap" messages from kernel/pci-common.c. This remapping didn't happen. Should a proper DTS file prevent this issue? If not where is the remapping done (I didn't see it). For that reason I'm ignoring the pci-to-pci bridge for now.

Thanks,
Roderick Colenbrander
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