From mboxrd@z Thu Jan 1 00:00:00 1970 From: Yuji Shimada Subject: [PATCH 0/3] save/restore PCI configuration space in pciback. Date: Wed, 22 Apr 2009 11:11:51 +0900 Message-ID: <20090422105816.32A4.27C06F64@necst.nec.co.jp> Mime-Version: 1.0 Content-Type: text/plain; charset="US-ASCII" Content-Transfer-Encoding: 7bit Return-path: List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Sender: xen-devel-bounces@lists.xensource.com Errors-To: xen-devel-bounces@lists.xensource.com To: Keir Fraser , Ian Jackson , Kouya Shimura , xen-devel@lists.xensource.com List-Id: xen-devel@lists.xenproject.org This series of patches enables saving/restoring PCI configuration space in pciback. Xend saves/restores PCI configuration space on current Xen. But it's not better place to save/restore. Because devices should be configured by device driver. And Shimura-san's D-state problem will be resolved with this patch. Because I modify the timing of saving/restoring configuration space like below. When pciback is bound to devices. - Pciback saves configuration space. When pciback is unbound to devices. - Pciback restores configuration space. When guest OS boots or a device is hotadded. - Pciback restores configuration space. - Pciback changes state of backend device to Initialised/Reconfigured. - Xend waits for the transition to Initialised/Reconfigured. When guest OS shutdowns or a device is hotremoved. - Pciback restores configuration space. - Xend resets devices. * If D-state of the device is not D0, the state is changed to D0 before resetting the device. - Xend deassigns devices. * Essentially, devices should be reset before configuration space is restored. But it needs big modifications. Applying these patches, configuration space is restored when guest OS boots, a device is hotadded or pciback is unbound. So it has no matter. The following registers are saved/restored by pciback. Configuration Space - Base Address Register set - Cache-line size Register - Latency timer Register - Enable SERR Bit / Enable PERR Bit in Control Register - Device Control Register (PCI Express Capability) - Link Control Register (PCI Express Capability) - Device Control 2 Register (PCI Express Capability) - Link Control 2 Register (PCI Express Capability) AER - Uncorrectable Error Mask Register - Uncorrectable Error Severity Register - Correctable Error Mask Register - Advanced Error Capabilities and Control Register Thanks, -- Yuji Shimada