Re: [PATCH 6/10 -tip] x86: early_init_intel() user of Advanced Power Management features

From: Andreas Herrmann <andreas.herrmann3@amd.com>
To: Jaswinder Singh Rajput <jaswinder@kernel.org>
Cc: Ingo Molnar <mingo@elte.hu>, "H. Peter Anvin" <hpa@kernel.org>,
	Robert Richter <robert.richter@amd.com>,
	Dave Jones <davej@redhat.com>,
	LKML <linux-kernel@vger.kernel.org>,
	x86 maintainers <x86@kernel.org>
Subject: Re: [PATCH 6/10 -tip] x86: early_init_intel() user of Advanced Power Management features
Date: Wed, 13 May 2009 08:18:01 +0200	[thread overview]
Message-ID: <20090513061801.GD9991@alberich.amd.com> (raw)
In-Reply-To: <1242142908.2547.20.camel@ht.satnam>

On Tue, May 12, 2009 at 09:11:48PM +0530, Jaswinder Singh Rajput wrote:
> 
> use X86_FEATURE_CONSTANT_TSC to determine TSC Invariance
> 
> Signed-off-by: Jaswinder Singh Rajput <jaswinderrajput@gmail.com>

I'd like to NAK this as well.

You didn't get to the point what's the difference between
X86_FEATURE_CONSTANT_TSC and X86_FEATURE_NONSTOP_TSC, did you?
I guess you never checked the related commit messages. (I.e. using git
blame to see how code evolved over time and _why_ was it changed.)
In this case it would have been commit 40fb17152c50a69dc304dd632131c2f41281ce44
(x86: support always running TSC on Intel CPUs), see
http://git.kernel.org/?p=linux/kernel/git/torvalds/linux-2.6.git;a=commit;h=40fb17152c50a69dc304dd632131c2f41281ce44

>  arch/x86/kernel/cpu/intel.c |    8 ++++----
>  1 files changed, 4 insertions(+), 4 deletions(-)
> 
> diff --git a/arch/x86/kernel/cpu/intel.c b/arch/x86/kernel/cpu/intel.c
> index 7437fa1..62130a0 100644
> --- a/arch/x86/kernel/cpu/intel.c
> +++ b/arch/x86/kernel/cpu/intel.c
> @@ -61,14 +61,14 @@ static void __cpuinit early_init_intel(struct cpuinfo_x86 *c)
>  		c->x86_phys_bits = 36;
>  
>  	/*
> -	 * c->x86_power is 8000_0007 edx. Bit 8 is TSC runs at constant rate
> -	 * with P/T states and does not stop in deep C-states.
> +	 * Advanced power management is 8000_0007 edx.
> +	 * Bit 8 is TSC runs at constant rate with P/T states
> +	 * and does not stop in deep C-states.
>  	 *
>  	 * It is also reliable across cores and sockets. (but not across
>  	 * cabinets - we turn it off in that case explicitly.)
>  	 */
> -	if (c->x86_power & (1 << 8)) {
> -		set_cpu_cap(c, X86_FEATURE_CONSTANT_TSC);
> +	if (cpu_has(c, X86_FEATURE_CONSTANT_TSC)) {
>  		set_cpu_cap(c, X86_FEATURE_NONSTOP_TSC);
>  		set_cpu_cap(c, X86_FEATURE_TSC_RELIABLE);
>  		sched_clock_stable = 1;

This code would mark some Intel CPUs as having
X86_FEATURE_NONSTOP_TSC which is certainly wrong in some cases.

You missed this snippet.

        if ((c->x86 == 0xf && c->x86_model >= 0x03) ||
                (c->x86 == 0x6 && c->x86_model >= 0x0e))
                set_cpu_cap(c, X86_FEATURE_CONSTANT_TSC);

in early_init_intel().

Regards,
Andreas

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